CN113540019A - Variable capacitor and method for forming variable capacitor - Google Patents
Variable capacitor and method for forming variable capacitor Download PDFInfo
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- CN113540019A CN113540019A CN202010311748.9A CN202010311748A CN113540019A CN 113540019 A CN113540019 A CN 113540019A CN 202010311748 A CN202010311748 A CN 202010311748A CN 113540019 A CN113540019 A CN 113540019A
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- 238000000034 method Methods 0.000 title claims abstract description 67
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- 239000010941 cobalt Substances 0.000 claims description 32
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- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
- H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
- H01L27/0733—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors in combination with capacitors only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract
A variable capacitor and a method for forming the same, the structure includes: the substrate comprises a first area and second areas positioned on two sides of the first area, and the first area is provided with a plurality of fin structures; a gate structure located on the first region; the first dummy gate structure is positioned on the second region and is parallel to the gate structure; the second dummy gate structure is positioned on the first region and positioned on two sides of the gate structure; a source-drain doped region located in the fin portion structure between the gate structure and the second dummy gate structure; the first plug is positioned on the source drain doping region and electrically connected with the source drain doping region; the second plug is positioned on the first dummy gate structure and electrically connected with the first dummy gate structure; and the first conducting layer is positioned on the first plug and the second plug, electrically connected with the first plug and electrically connected with the second plug. The performance of the variable capacitor is improved.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a variable capacitor and a method for forming the same.
Background
With the development of semiconductor manufacturing technology, integrated circuits with higher performance and higher functionality require greater element density, and the size, dimension and space of each component, element or each element itself also need to be further reduced (currently reaching the nanometer level), and with the reduction of the size of semiconductor devices, various microscopic effects are highlighted, and in order to meet the demand of device development, those skilled in the art are actively exploring new semiconductor manufacturing processes.
The quality factor (energy storage/energy loss) is an important parameter to determine whether a device is efficient or not. In the variable capacitor, a higher quality factor value represents a small energy loss when the device operates, and the variable capacitor operates with high efficiency. And parasitic devices in the variable capacitor structure make the quality factor of the variable capacitor low.
Therefore, it is necessary to improve the quality factor of the variable capacitor.
Disclosure of Invention
The invention provides a variable capacitor and a forming method thereof, which are used for improving the performance of the variable capacitor.
In order to solve the above technical problem, a technical solution of the present invention provides a variable capacitor, including: the substrate comprises a first area and a second area, wherein the first area is positioned between the adjacent second areas, the first area is provided with a plurality of fin structures, and the fin structures are arranged along a first direction parallel to the surface of the substrate; the grid electrode structure is positioned on the first area and spans the fin part structures; a first dummy gate structure located on the second region, the first dummy gate structure being parallel to the gate structure; the second dummy gate structure is positioned on the first region, positioned on two sides of the gate structure and crossed over the fin structures, and parallel to the gate structure; the source-drain doped regions are positioned in the fin part structures on the two sides of the grid structure and are positioned between the grid structure and the second pseudo grid structure; the first plug is positioned on the source drain doping region and electrically connected with the source drain doping region; a second plug located on the first dummy gate structure, the second plug being electrically connected to the first dummy gate structure; a first conductive layer on the first plug and on the second plug, the first conductive layer electrically connected to the first plug, and the first conductive layer electrically connected to the second plug.
Optionally, the method further includes: an isolation structure on the substrate, the isolation structure located on the gate structure top surface and sidewall surface, the first dummy gate structure top surface and sidewall surface, and the second dummy gate structure top surface and sidewall surface; the isolation structure covers the first plug and the second plug; the first conductive layer is also located on the isolation structure.
Optionally, the method further includes: a first dielectric layer located between the isolation structure and the first conductive layer; a second conductive layer within the first dielectric layer, the second conductive layer electrically connected to the first plug; and the third conducting layer is positioned in the first dielectric layer and is electrically connected with the second plug.
Optionally, the method further includes: a second dielectric layer located between the first dielectric layer and the first conductive layer; the plurality of third plugs are positioned in the second dielectric layer, the plurality of third plugs are respectively and electrically connected with the second conducting layer, and the plurality of third plugs are respectively and electrically connected with the third conducting layer; the first conductive layer is electrically connected to the third plug.
Optionally, the method further includes: and the fourth plug is positioned in the isolation structure on the surface of the top of the grid structure and is electrically connected with the top of the grid structure.
Optionally, the method further includes: and the fourth conducting layer is positioned in the first dielectric layer on the top surface of the fourth plug and is electrically connected with the fourth plug.
Optionally, the method further includes: and the first dummy conductive layer is positioned in the first dielectric layer between the first dummy gate structure and the second dummy gate structure and is parallel to the second conductive layer.
Optionally, the method further includes: and the second dummy conductive layer is positioned in the first dielectric layer on the top surface of the second dummy gate structure.
Optionally, the material of the first plug includes a metal, and the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, and titanium nitride; the material of the second plug comprises a metal comprising: one or more combinations of copper, aluminum, tungsten, cobalt, and titanium nitride.
Optionally, the material of the first conductive layer includes a metal, and the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, and titanium nitride; the material of the second conductive layer comprises a metal comprising: combinations of one or more of copper, aluminum, tungsten, cobalt, and titanium nitride; the material of the third conductive layer comprises a metal comprising: one or more combinations of copper, aluminum, tungsten, cobalt, and titanium nitride.
Correspondingly, the technical scheme of the invention also provides a method for forming the variable capacitor, which comprises the following steps: providing a substrate, wherein the substrate comprises a first area and a second area, the first area is positioned between the adjacent second areas, the first area is provided with a plurality of fin structures, and the fin structures are arranged along a first direction parallel to the surface of the substrate; forming a gate structure on the first region, wherein the gate structure spans the fin structures; forming a first dummy gate structure on the second region, the first dummy gate structure being parallel to the gate structure; forming a second dummy gate structure on the first region, wherein the second dummy gate structure is positioned on two sides of the gate structure, the second dummy gate structure crosses over the fin structures, and the second dummy gate structure is parallel to the gate structure; forming source and drain doped regions in the fin part structures on two sides of the grid structure, wherein the source and drain doped regions are positioned between the grid structure and the second pseudo grid structure; forming a first plug on the source drain doping region, wherein the first plug is electrically connected with the source drain doping region; forming a second plug on the first dummy gate structure, wherein the second plug is electrically connected with the first dummy gate structure; and forming a first conductive layer on the first plug and the second plug, wherein the first conductive layer is electrically connected with the first plug, and the first conductive layer is electrically connected with the second plug.
Optionally, after forming the source-drain doped region and before forming the first plug and the second plug, the method further includes: and forming an isolation structure on the substrate, wherein the isolation structure is positioned on the side wall surface of the grid structure, the side wall surface of the first dummy grid structure and the side wall surface of the second dummy grid structure.
Optionally, the first and second plugs are located within the isolation structure; the first conductive layer is also located on the isolation structure.
Optionally, before forming the first conductive layer, the method further includes: forming a first dielectric layer on the isolation structure; forming a second conductive layer in the first dielectric layer, wherein the second conductive layer is electrically connected with the first plug; and forming a third conductive layer in the first dielectric layer, wherein the third conductive layer is electrically connected with the second plug.
Optionally, before forming the first conductive layer, the method further includes: forming a second dielectric layer on the first dielectric layer; forming a plurality of third plugs in the second dielectric layer, wherein the plurality of third plugs are respectively electrically connected with the second conductive layer, and the plurality of third plugs are respectively electrically connected with the third conductive layer; the first conductive layer is electrically connected to the third plug.
Optionally, before forming the first conductive layer, the method further includes: and forming a fourth plug in the isolation structure, wherein the fourth plug is positioned in the isolation structure on the surface of the top of the gate structure and is electrically connected with the top of the gate structure.
Optionally, the method further includes: and forming a fourth conducting layer in the first dielectric layer, wherein the fourth conducting layer is positioned in the first dielectric layer on the top surface of the fourth plug, and the fourth conducting layer is electrically connected with the fourth plug.
Optionally, the method further includes: and forming a first pseudo conductive layer in the first dielectric layer between the first pseudo gate structure and the second pseudo gate structure, wherein the first pseudo conductive layer is parallel to the second conductive layer.
Optionally, the material of the first plug includes a metal, and the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, and titanium nitride; the material of the second plug comprises a metal comprising: one or more combinations of copper, aluminum, tungsten, cobalt, and titanium nitride.
Optionally, the material of the first conductive layer includes a metal, and the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, and titanium nitride; the material of the second conductive layer comprises a metal comprising: combinations of one or more of copper, aluminum, tungsten, cobalt, and titanium nitride; the material of the third conductive layer comprises a metal comprising: one or more combinations of copper, aluminum, tungsten, cobalt, and titanium nitride.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
in the variable capacitor according to the technical scheme of the invention, the first conductive layer is electrically connected with the first plug, and the first conductive layer is electrically connected with the second plug, that is, the first dummy gate structure is electrically connected with the source drain doped region, so that the second dummy gate structure crossing the fin structure becomes a floating gate. The second pseudo gate structure becomes a floating gate, on one hand, the first pseudo gate structure is electrically connected with the source drain doped region, and the distance between the first pseudo gate structure and the gate structure is increased, so that the parasitic capacitance of the variable capacitor structure is reduced, and the situation that the first pseudo gate structure and the gate structure generate larger parasitic capacitance when the first pseudo gate structure and the second pseudo gate structure are simultaneously and electrically connected with the source drain doped region is avoided; on the other hand, only the second dummy gate structure becomes a floating gate, so that the coupling capacitance of the variable capacitor structure is reduced, and the situation that large coupling capacitance is generated between the first dummy gate structure and the gate structure and between the second dummy gate structure and the gate structure when the first dummy gate structure and the second dummy gate structure become floating gates at the same time is avoided. Parasitic capacitance and coupling capacitance in the variable capacitor structure reach a balanced state, so that the whole capacitance of the variable capacitor is controllable, and the effective working state of the variable capacitor circuit is improved. In conclusion, the performance of the variable capacitor is improved.
In the method for forming the variable capacitor, the first conductive layer is electrically connected with the first plug, and the first conductive layer is electrically connected with the second plug, so that the first dummy gate structure is electrically connected with the source drain doped region, and the second dummy gate structure crossing the fin structure becomes a floating gate. The second pseudo gate structure becomes a floating gate, on one hand, the first pseudo gate structure is electrically connected with the source drain doped region, and the distance between the first pseudo gate structure and the gate structure is increased, so that the parasitic capacitance of the variable capacitor structure is reduced, and the situation that the first pseudo gate structure and the gate structure generate larger parasitic capacitance when the first pseudo gate structure and the second pseudo gate structure are simultaneously and electrically connected with the source drain doped region is avoided; on the other hand, only the second dummy gate structure becomes a floating gate, so that the coupling capacitance of the variable capacitor structure is reduced, and the situation that large coupling capacitance is generated between the first dummy gate structure and the gate structure and between the second dummy gate structure and the gate structure when the first dummy gate structure and the second dummy gate structure become floating gates at the same time is avoided. The method ensures that the parasitic capacitance and the coupling capacitance in the variable capacitor structure reach a balanced state, so that the whole capacitance of the variable capacitor is controllable, and the effective working state of the variable capacitor circuit is improved. In conclusion, the performance of the variable capacitor is improved.
Drawings
Fig. 1 and 2 are schematic structural views of a process of forming a variable capacitor in one embodiment;
fig. 3 to 12 are schematic structural diagrams illustrating a process of forming a variable capacitor according to an embodiment of the present invention.
Detailed Description
As described in the background, there is a need to improve the quality factor of variable capacitors. The analysis will now be described with reference to specific examples.
Fig. 1 and 2 are schematic diagrams illustrating a process of forming a variable capacitor according to an embodiment.
Referring to fig. 1, fig. 1 is a top view of a variable capacitor with a dielectric structure omitted, including: a substrate 100, the substrate 100 comprising a first region I and a second region II, the first region I being located between adjacent second regions II; a plurality of fin structures (not labeled) located on the first region I; the gate structure 101 is positioned on the first region I, and the gate structure 101 crosses the fin structure; the first dummy gate structure 102 is positioned on the first region I, and the first dummy gate structure 102 is positioned at two sides of the gate structure 101; a second dummy gate structure 103 located on the second region II; source and drain doped regions (not shown) in the fin structures at both sides of the gate structure 101, the source and drain doped regions being located between the first dummy gate structure 102 and the gate structure 101; a first metal layer 104 located in a first dielectric layer (not shown) on the top surface of the gate structure 101, wherein the first metal layer 104 is electrically connected to the top of the gate structure 101; a second metal layer 105 located in a first dielectric layer (not shown) on the top surface of the first dummy gate structure 102, wherein the second metal layer 105 is electrically connected to the top of the first dummy gate structure 102; a third metal layer 106 located in the first dielectric layer (not shown) on the top surface of the second dummy gate structure 103, wherein the third metal layer 106 is electrically connected to the top of the second dummy gate structure 103; and the fourth metal layer 107 is positioned in the first dielectric layer (not shown) on the surface of the source-drain doped region, and the fourth metal layer 107 is electrically connected with the source-drain doped region.
Referring to fig. 2, a second dielectric layer (not shown) is formed on the surface of the first metal layer 104, the surface of the second metal layer 105, the surface of the third metal layer 106 and the surface of the fourth metal layer 107; and forming a fifth metal layer 108 in the second dielectric layer, wherein the fifth metal layer 108 is electrically connected with the fourth metal layer 107, and the fifth metal layer 108 is electrically connected with the second metal layer 105 and the third metal layer 106.
In the variable capacitor, in the process of forming the gate structure 101, a first dummy gate structure 102 is formed on the first region I, the first dummy gate structure 102 crosses over the fin structure, and a second dummy gate structure 103 is formed on the second region II. On one hand, the patterns for forming the first dummy gate structure 102 and the second dummy gate structure 103 are added in the pattern for forming the gate structure 101, so that the density of the pattern for forming the gate structure 101 is more uniform, and the size uniformity of the formed gate structure 101 is better; on the other hand, the source-drain doped region is located in the fin portion structure between the gate structure 101 and the first dummy gate structure 102, so that when the source-drain doped region is formed, a complete seed layer can be formed in the fin portion structure between the gate structure 101 and the first dummy gate structure 102, the seed layer can grow into the source-drain doped region with uniform size, and the situation that the source-drain doped region with poor appearance is formed in the fin portion structure when the first dummy gate structure 102 is not formed is avoided.
However, the first dummy gate structure 102 and the second dummy gate structure 103 are structures that do not actually work in the variable capacitor, and in order to avoid unnecessary electric potentials generated in the circuit by the first dummy gate structure 102 and the second dummy gate structure 103, in a back-end process, if the first dummy gate structure 102 and the second dummy gate structure 103 are made to be floating gates, that is, the peripheries of the first dummy gate structure 102 and the second dummy gate structure 103 are isolated from other structures, and after a back-gate process, the first dummy gate structure 102 and the second dummy gate structure 103 are both metal gates, the metal floating gates may generate coupling capacitance with the gate structure 101, so that the electric potential variation of the variable capacitor is uncontrollable, and the working state of the effective circuit of the variable capacitor is affected. Therefore, it is a common method to connect the first dummy gate structure 102 and the second dummy gate structure 103 to a certain potential of a circuit, and usually, the first dummy gate structure 102 and the second dummy gate structure 103 are electrically connected to the source/drain doped region through the fifth conductive layer 108.
However, with the further reduction of the device size, after the first dummy gate structure 102 and the second dummy gate structure 103 are electrically connected to the source-drain doped region, when the circuit is turned on, the first dummy gate structure 102 also has a turn-on voltage along with the voltage variation of the source-drain doped region, so that the first dummy gate structure 102 becomes a parasitic device, and the circuit of the variable capacitor has a parasitic capacitance, thereby affecting the response speed of the variable capacitor.
In order to solve the above problems, the present invention provides a variable capacitor and a method for forming a variable capacitor, in which the first conductive layer is electrically connected to the first plug and the second conductive layer is electrically connected to the second plug, so that the first conductive layer is simultaneously electrically connected to the first dummy gate structure and the source-drain doped region, and the second dummy gate structure crossing the fin structure is a floating gate. The second pseudo gate structure becomes a floating gate, on one hand, the first pseudo gate structure is electrically connected with the source drain doped region, and the distance between the first pseudo gate structure and the gate structure is increased, so that the parasitic capacitance of the variable capacitor structure is reduced, and the situation that the first pseudo gate structure and the gate structure generate larger parasitic capacitance when the first pseudo gate structure and the second pseudo gate structure are simultaneously and electrically connected with the source drain doped region is avoided; on the other hand, only the second dummy gate structure becomes a floating gate, so that the coupling capacitance of the variable capacitor structure is reduced, and the situation that large coupling capacitance is generated between the first dummy gate structure and the gate structure and between the second dummy gate structure and the gate structure when the first dummy gate structure and the second dummy gate structure become floating gates at the same time is avoided. The method ensures that the parasitic capacitance and the coupling capacitance in the variable capacitor structure reach a balanced state, so that the whole capacitance of the variable capacitor is controllable, and the effective working state of the variable capacitor circuit is improved. In conclusion, the performance of the variable capacitor is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
FIGS. 3 to 12 are schematic structural diagrams illustrating a process of forming a variable capacitor according to an embodiment of the present invention
Referring to fig. 3 and 4, fig. 3 is a top view of fig. 4 with the first isolation layer omitted, fig. 4 is a schematic cross-sectional structure view along a section line AA' of fig. 3, and a substrate 200 is provided, where the substrate 200 includes a first region I and a second region II, the first region I is located between the adjacent second regions II, the first region I has a plurality of fin structures 201 thereon, and the plurality of fin structures 201 are arranged along a first direction X parallel to a surface of the substrate 200.
The substrate 200 further has a first isolation layer (not shown) on the sidewall surface of the fin structure 201, and a top surface of the first isolation layer is lower than a top surface of the fin structure 201.
In this embodiment, the material of the substrate 200 is monocrystalline silicon; the material of the fin structure 201 comprises monocrystalline silicon.
In other embodiments, the substrate may also be a semiconductor material such as polysilicon, germanium, silicon germanium, gallium arsenide, silicon-on-insulator, or germanium-on-insulator; the fin structure may also be a semiconductor material such as polysilicon, germanium, silicon germanium, gallium arsenide, silicon on insulator, or germanium on insulator.
The material of the first isolation layer comprises a dielectric material comprising a combination of one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, and silicon carbide nitride. In this embodiment, the material of the first isolation layer includes silicon oxide.
Referring to fig. 5 and fig. 6, fig. 5 is a top view of fig. 6 with the isolation structure and the first isolation layer omitted, fig. 6 is a schematic cross-sectional view of fig. 5 along a section line BB' direction, a gate structure 203 is formed on a first region I, the gate structure 203 crosses over a plurality of fin structures 201, a first dummy gate structure 204 is formed on a second region II, the first dummy gate structure 204 is parallel to the gate structure 203, a second dummy gate structure 205 is formed on the first region I, the second dummy gate structure 205 is located at two sides of the gate structure 203, the second dummy gate structure 205 crosses over a plurality of fin structures 201, and the second dummy gate structure 205 is parallel to the gate structure 203.
In this embodiment, the method further includes: and forming a source-drain doped region 206 in the fin structure 201 on two sides of the gate structure 203, wherein the source-drain doped region 206 is positioned between the gate structure 203 and the second dummy gate structure 205.
Doped ions are arranged in the source-drain doped region 206, the type of the doped ions is N type or P type, the N type ions include phosphorus ions or arsenic ions, and the P type ions include boron ions or boron-fluorine ions.
In this embodiment, the gate structure 203, the first dummy gate structure 204 and the second dummy gate structure 205 are formed simultaneously.
The gate structure 203 includes a gate dielectric layer (not shown) and a gate layer (not shown) on the gate dielectric layer.
The first dummy gate structure 204 includes a first dummy gate dielectric layer (not shown) and a first dummy gate layer (not shown) on the first dummy gate dielectric layer.
The second dummy gate structure 205 includes a second dummy gate dielectric layer (not shown) and a second dummy gate layer (not shown) on the second dummy gate dielectric layer.
The dielectric constant of the material of the gate dielectric layer is greater than 3.7, and the material of the gate dielectric layer comprises hafnium oxide or aluminum oxide; the material of the gate layer comprises a metal comprising tungsten. The dielectric constant of the material of the first pseudo gate dielectric layer is greater than 3.7, and the material of the first pseudo gate dielectric layer comprises hafnium oxide or aluminum oxide; the material of the first dummy gate layer comprises a metal, and the metal comprises tungsten. The dielectric constant of the material of the second pseudo gate dielectric layer is greater than 3.7, and the material of the second pseudo gate dielectric layer comprises hafnium oxide or aluminum oxide; the material of the second dummy gate layer comprises a metal, and the metal comprises tungsten.
The forming method of the gate structure 203, the first dummy gate structure 204, the second dummy gate structure 205 and the source-drain doped region 206 comprises the following steps: forming a first initial gate structure (not shown) and third initial gate structures (not shown) on two sides of the first initial gate structure on the first region I of the substrate, wherein the first initial gate structure and the third initial gate structures cross over the fin structure 201, and forming a second initial gate structure (not shown) on the second region II; forming a source-drain doped region 206 in the fin structures 201 on two sides of the first initial gate structure, wherein the source-drain doped region 206 is located between the first initial gate structure and the third initial gate structure; forming a second isolation layer 207 on the substrate, the side wall of the first initial gate structure, the side wall of the second initial gate structure and the side wall of the third initial gate structure, wherein the second isolation layer 207 exposes the top surface of the initial gate structure; removing the first preliminary gate structure, forming a first gate opening (not shown) in the second isolation layer 207; removing the second initial gate structure, and forming a second gate opening (not shown) on the second region II; removing the third initial gate structure, and forming a third gate opening (not shown) on the first region I; a gate structure 203 is formed in the first gate opening, a first dummy gate structure 204 is formed in the second gate opening, and a second dummy gate structure 205 is formed in the third gate opening.
The material of the second isolation layer 207 comprises a dielectric material comprising one or a combination of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, and silicon carbide nitride. In this embodiment, the material of the second isolation layer 207 includes silicon oxide.
With continued reference to fig. 5 and 6, a third isolation layer 208 is formed on the second isolation layer 207, and isolation structures are formed on the substrate 200, the isolation structures being located on the top surface and sidewall surface of the gate structure 203, the top surface and sidewall surface of the first dummy gate structure 204, and the top surface and sidewall surface of the second dummy gate structure 205.
The isolation structure includes a second isolation layer 207 and a third isolation layer 208 on the second isolation layer 207.
The material of the third isolation layer 208 comprises a dielectric material comprising one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, and silicon oxycarbonitride. The process of forming the third isolation layer 208 includes a chemical vapor deposition process, an atomic layer deposition process, or a thermal treatment process.
In the present embodiment, the material of the third isolation layer 208 includes silicon oxide; the process of forming the third isolation layer 208 includes a chemical vapor deposition process.
Referring to fig. 7 and 8, fig. 7 is a top view of fig. 8 with the isolation structure, the first isolation layer and the first dielectric layer 212 omitted, fig. 8 is a schematic cross-sectional structure along the direction of the section line CC' of fig. 7, and a first plug (not shown) is formed in the isolation structure, the first plug is located in the isolation structure on the surface of the source-drain doped region 206, and the first plug is electrically connected to the source-drain doped region 206; forming a second plug 210 in the isolation structure, wherein the second plug 210 is located in the isolation structure on the top surface of the first dummy gate structure 204, and the second plug 210 is electrically connected to the first dummy gate structure 204; and forming a fourth plug 211 in the isolation structure, wherein the fourth plug 211 is located in the isolation structure on the top surface of the gate structure 203, and the fourth plug 211 is electrically connected with the top of the gate structure 203.
The material of the first plug comprises a metal comprising: combinations of one or more of copper, aluminum, tungsten, cobalt, and titanium nitride; the material of the second plug 210 comprises a metal comprising: combinations of one or more of copper, aluminum, tungsten, cobalt, and titanium nitride; the material of the fourth plug 211 includes a metal including: one or more combinations of copper, aluminum, tungsten, cobalt, and titanium nitride.
Forming a second plug 210 electrically connected with the first dummy gate structure 204 in the isolation structure, so that the first dummy gate structure 204 can be electrically connected subsequently, and no conductive plug electrically connected with the second dummy gate structure 205 is formed, so that the second dummy gate structure 205 becomes a floating gate, thereby avoiding the situation that a large coupling capacitance is generated between the first dummy gate structure 204 and the gate structure 203 when the first dummy gate structure 204 and the second dummy gate structure 205 simultaneously become floating gates; meanwhile, the situation that the first dummy gate structure 204 and the gate structure 203 generate large parasitic capacitance when the first dummy gate structure 204 and the second dummy gate structure 205 are connected with electric potential at the same time is also avoided.
With continued reference to fig. 7 and 8, after forming the first plug, the second plug 210 and the fourth plug 211, a first dielectric layer 212 is formed on the isolation structure; forming a second conductive layer 213 in the first dielectric layer 212, wherein the second conductive layer 213 is electrically connected to the first plug; forming a third conductive layer 214 in the first dielectric layer 212, wherein the third conductive layer 214 is electrically connected to the second plug 210; and forming a fourth conductive layer 215 in the first dielectric layer 212, wherein the fourth conductive layer 215 is located in the first dielectric layer 212 on the top surface of the fourth plug 211, and the fourth conductive layer 215 is electrically connected with the fourth plug 211.
In this embodiment, the method further includes, while forming the third conductive layer 214 and the fourth conductive layer 215: a second dummy conductive layer 216 is formed within the first dielectric layer 212, the second dummy conductive layer 216 being located within the first dielectric layer 212 on top of the second dummy gate structure 205.
The second dummy conductive layer 216 is not used for actual electrical connection, and the second dummy conductive layer 216 is formed to make the pattern density of the third conductive layer 214 and the fourth conductive layer 215 more uniform, so that the process integration level is higher, which is beneficial to improving the performance stability of the device.
In this embodiment, a first dummy conductive layer (not shown) is formed in the first dielectric layer 212 between the first dummy gate structure 204 and the second dummy gate structure 205 at the same time as the second conductive layer 213, and the first dummy conductive layer is parallel to the second conductive layer 213.
The first dummy conductive layer is not used for actual electrical connection, and is formed to make the pattern density of the second conductive layer 213 uniform, so that the process integration is high, which is beneficial to improving the performance stability of the device.
The material of the second conductive layer 213 includes a metal including: combinations of one or more of copper, aluminum, tungsten, cobalt, and titanium nitride; the material of the third conductive layer 214 includes a metal including: combinations of one or more of copper, aluminum, tungsten, cobalt, and titanium nitride; the material of the fourth conductive layer 215 includes a metal including: one or more combinations of copper, aluminum, tungsten, cobalt, and titanium nitride.
The material of the first dielectric layer 212 includes a dielectric material including one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, and silicon oxycarbonitride. The process for forming the first dielectric layer 212 includes a chemical vapor deposition process, an atomic layer deposition process, or a thermal treatment process.
In the present embodiment, the material of the first dielectric layer 212 includes silicon oxide; the process of forming the first dielectric layer 212 includes a chemical vapor deposition process.
Referring to fig. 9 and 10, fig. 9 is a top view of fig. 10 with the isolation structure, the first isolation layer, the first dielectric layer 212 and the second dielectric layer 217 omitted, and fig. 10 is a cross-sectional view of fig. 9 along the section line DD', wherein the second dielectric layer 217 is formed on the first dielectric layer 212; a plurality of third plugs 218 are formed in the second dielectric layer 217, wherein the plurality of third plugs 218 are electrically connected to the second conductive layer 213, and the plurality of third plugs 218 are electrically connected to the third conductive layer 214.
The material of the third plug 218 includes a metal including: one or more combinations of copper, aluminum, tungsten, cobalt, and titanium nitride.
The material of the second dielectric layer 217 comprises a dielectric material comprising one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride and silicon oxycarbonitride. The process for forming the second dielectric layer 217 includes a chemical vapor deposition process, an atomic layer deposition process, or a thermal treatment process.
In this embodiment, the material of the second dielectric layer 217 includes silicon oxide; the process of forming the second dielectric layer 217 includes a chemical vapor deposition process.
Referring to fig. 11 and 12, fig. 11 is a top view of fig. 12 without the isolation structure, the first isolation layer, the first dielectric layer 212 and the second dielectric layer 217, fig. 12 is a schematic cross-sectional view taken along the section line EE' of fig. 11, a first conductive layer 219 is formed on the second dielectric layer 217, and the first conductive layer 219 is electrically connected to the third plug 218.
The first conductive layer 219 is electrically connected to the third plug 218, that is, the first conductive layer 219 is electrically connected to the first plug, and the first conductive layer 219 is electrically connected to the second plug 210, that is, the first dummy gate structure 204 is electrically connected to the source/drain doped region 206, so that the second dummy gate structure 205 crossing the fin structure 201 becomes a floating gate.
The second dummy gate structure 205 is a floating gate, on one hand, the first dummy gate structure 204 is electrically connected with the source-drain doped region 206, and the distance between the first dummy gate structure 204 and the gate structure 203 is increased, so that the parasitic capacitance of the variable capacitor structure is reduced, and the situation that the first dummy gate structure 204 and the gate structure 203 generate large parasitic capacitance when the first dummy gate structure 204 and the second dummy gate structure 205 are simultaneously electrically connected with the source-drain doped region 206 is avoided; on the other hand, only the second dummy gate structure 205 becomes a floating gate, so that the coupling capacitance of the variable capacitor structure is reduced, and the situation that large coupling capacitance is generated between the first dummy gate structure 204 and the gate structure 203 and between the second dummy gate structure 205 and the gate structure 204 when the first dummy gate structure 204 and the second dummy gate structure 205 become floating gates at the same time is avoided. Parasitic capacitance and coupling capacitance in the variable capacitor structure reach a balanced state, so that the whole capacitance of the variable capacitor is controllable, and the effective working state of the variable capacitor circuit is improved. In conclusion, the performance of the variable capacitor is improved.
Accordingly, an embodiment of the present invention further provides a variable capacitor, please continue to refer to fig. 11 and 12, including:
the substrate 200 comprises a first area I and a second area II, the first area I is located between the adjacent second areas II, the first area I is provided with a plurality of fin structures 201, and the fin structures 201 are arranged along a first direction X parallel to the surface of the substrate 200;
a gate structure 203 located on the first region I, the gate structure 203 crossing over the plurality of fin structures 201;
a first dummy gate structure 204 located on the second region II, wherein the first dummy gate structure 204 is parallel to the gate structure 203;
a second dummy gate structure 205 located on the first region I, wherein the second dummy gate structure 205 is located on two sides of the gate structure 203, the second dummy gate structure 205 crosses over the plurality of fin structures 201, and the second dummy gate structure 205 is parallel to the gate structure 203;
the source-drain doped regions are positioned in the fin structures 201 on two sides of the gate structure 203, and the source-drain doped regions 206 are positioned between the gate structure 203 and the second dummy gate structure 205;
isolation structures on the substrate 200, the isolation structures located on the top surface and sidewall surface of the gate structure 203, the top surface and sidewall surface of the first dummy gate structure 204, and the top surface and sidewall surface of the second dummy gate structure 205;
a first plug and a second plug 210 located in the isolation structure, wherein the first plug is electrically connected to the source-drain doped region 206, and the second plug 210 is electrically connected to the first dummy gate structure 204;
a first conductive layer 219 on the isolation structure, the first conductive layer 219 being electrically connected to the first plug, and the first conductive layer 219 being electrically connected to the second plug 210.
In this embodiment, the method further includes: a first dielectric layer 212 between the isolation structure and the first conductive layer 219; a second conductive layer 213 disposed in the first dielectric layer 212, wherein the second conductive layer 213 is electrically connected to the first plug; a third conductive layer 214 located within the first dielectric layer 212, the third conductive layer 214 being electrically connected to the second plug 210.
In this embodiment, the method further includes: a second dielectric layer 217 between the first dielectric layer 212 and the first conductive layer 219; a plurality of third plugs 218 located in the second dielectric layer 217, wherein a plurality of the third plugs 218 are electrically connected to the second conductive layer 213, and a plurality of the third plugs 218 are electrically connected to the third conductive layer 214; the first conductive layer 219 is electrically connected to the third plug 218.
In this embodiment, the method further includes: and a fourth plug 211 positioned in the isolation structure, wherein the fourth plug 211 is positioned in the isolation structure on the top surface of the gate structure 203, and the fourth plug 211 is electrically connected with the top of the gate structure 203.
In this embodiment, the method further includes: and a fourth conductive layer 215 positioned in the first dielectric layer 212, wherein the fourth conductive layer 215 is positioned in the first dielectric layer 212 on the top surface of the fourth plug 211, and the fourth conductive layer 215 is electrically connected with the fourth plug 211.
In this embodiment, the method further includes: a first dummy conductive layer (not labeled) in the first dielectric layer 212 between the first dummy gate structure 204 and the second dummy gate structure 205, the first dummy conductive layer being parallel to the second conductive layer 213.
In this embodiment, the method further includes: and a second dummy conductive layer 216 within the first dielectric layer 212 at the top surface of the second dummy gate structure 205.
In this embodiment, the material of the first plug includes a metal, and the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, and titanium nitride; the material of the second plug 210 comprises a metal comprising: one or more combinations of copper, aluminum, tungsten, cobalt, and titanium nitride.
In this embodiment, the material of the first conductive layer 219 includes metal, and the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, and titanium nitride; the material of the second conductive layer 213 includes a metal including: combinations of one or more of copper, aluminum, tungsten, cobalt, and titanium nitride; the material of the third conductive layer 214 includes a metal including: one or more combinations of copper, aluminum, tungsten, cobalt, and titanium nitride.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (20)
1. A variable capacitor, comprising:
the substrate comprises a first area and a second area, wherein the first area is positioned between the adjacent second areas, the first area is provided with a plurality of fin structures, and the fin structures are arranged along a first direction parallel to the surface of the substrate;
the grid electrode structure is positioned on the first area and spans the fin part structures;
a first dummy gate structure located on the second region, the first dummy gate structure being parallel to the gate structure;
the second dummy gate structure is positioned on the first region, positioned on two sides of the gate structure and crossed over the fin structures, and parallel to the gate structure;
the source-drain doped regions are positioned in the fin part structures on the two sides of the grid structure and are positioned between the grid structure and the second pseudo grid structure;
the first plug is positioned on the source drain doping region and electrically connected with the source drain doping region;
a second plug located on the first dummy gate structure, the second plug being electrically connected to the first dummy gate structure;
a first conductive layer on the first plug and on the second plug, the first conductive layer electrically connected to the first plug, and the first conductive layer electrically connected to the second plug.
2. The variable capacitor of claim 1, further comprising: an isolation structure on the substrate, the isolation structure located on the gate structure top surface and sidewall surface, the first dummy gate structure top surface and sidewall surface, and the second dummy gate structure top surface and sidewall surface; the isolation structure covers the first plug and the second plug; the first conductive layer is also located on the isolation structure.
3. The variable capacitor of claim 2, further comprising: a first dielectric layer located between the isolation structure and the first conductive layer; a second conductive layer within the first dielectric layer, the second conductive layer electrically connected to the first plug; and the third conducting layer is positioned in the first dielectric layer and is electrically connected with the second plug.
4. The variable capacitor of claim 3, further comprising: a second dielectric layer located between the first dielectric layer and the first conductive layer; the plurality of third plugs are positioned in the second dielectric layer, the plurality of third plugs are respectively and electrically connected with the second conducting layer, and the plurality of third plugs are respectively and electrically connected with the third conducting layer; the first conductive layer is electrically connected to the third plug.
5. The variable capacitor of claim 3, further comprising: and the fourth plug is positioned in the isolation structure on the surface of the top of the grid structure and is electrically connected with the top of the grid structure.
6. The variable capacitor of claim 5, further comprising: and the fourth conducting layer is positioned in the first dielectric layer on the top surface of the fourth plug and is electrically connected with the fourth plug.
7. The variable capacitor of claim 3, further comprising: and the first dummy conductive layer is positioned in the first dielectric layer between the first dummy gate structure and the second dummy gate structure and is parallel to the second conductive layer.
8. The variable capacitor of claim 3, further comprising: and the second dummy conductive layer is positioned in the first dielectric layer on the top surface of the second dummy gate structure.
9. The variable capacitor of claim 1, wherein the material of the first plug comprises a metal comprising: combinations of one or more of copper, aluminum, tungsten, cobalt, and titanium nitride; the material of the second plug comprises a metal comprising: one or more combinations of copper, aluminum, tungsten, cobalt, and titanium nitride.
10. The variable capacitor of claim 3, wherein the material of the first conductive layer comprises a metal comprising: combinations of one or more of copper, aluminum, tungsten, cobalt, and titanium nitride; the material of the second conductive layer comprises a metal comprising: combinations of one or more of copper, aluminum, tungsten, cobalt, and titanium nitride; the material of the third conductive layer comprises a metal comprising: one or more combinations of copper, aluminum, tungsten, cobalt, and titanium nitride.
11. A method of forming a variable capacitor, comprising:
providing a substrate, wherein the substrate comprises a first area and a second area, the first area is positioned between the adjacent second areas, the first area is provided with a plurality of fin structures, and the fin structures are arranged along a first direction parallel to the surface of the substrate;
forming a gate structure on the first region, wherein the gate structure spans the fin structures;
forming a first dummy gate structure on the second region, the first dummy gate structure being parallel to the gate structure;
forming a second dummy gate structure on the first region, wherein the second dummy gate structure is positioned on two sides of the gate structure, the second dummy gate structure crosses over the fin structures, and the second dummy gate structure is parallel to the gate structure;
forming source and drain doped regions in the fin part structures on two sides of the grid structure, wherein the source and drain doped regions are positioned between the grid structure and the second pseudo grid structure;
forming a first plug on the source drain doping region, wherein the first plug is electrically connected with the source drain doping region;
forming a second plug on the first dummy gate structure, wherein the second plug is electrically connected with the first dummy gate structure;
and forming a first conductive layer on the first plug and the second plug, wherein the first conductive layer is electrically connected with the first plug, and the first conductive layer is electrically connected with the second plug.
12. The method for forming a variable capacitor as claimed in claim 11, wherein after forming the source-drain doped regions and before forming the first plug and the second plug, the method further comprises: and forming an isolation structure on the substrate, wherein the isolation structure is positioned on the side wall surface of the grid structure, the side wall surface of the first dummy grid structure and the side wall surface of the second dummy grid structure.
13. The method of forming a variable capacitor of claim 12, wherein said first and second plugs are located within said isolation structure; the first conductive layer is also located on the isolation structure.
14. The method of forming a variable capacitor according to claim 13, further comprising, before forming the first conductive layer: forming a first dielectric layer on the isolation structure; forming a second conductive layer in the first dielectric layer, wherein the second conductive layer is electrically connected with the first plug; and forming a third conductive layer in the first dielectric layer, wherein the third conductive layer is electrically connected with the second plug.
15. The method of forming a variable capacitor according to claim 14, further comprising, before forming the first conductive layer: forming a second dielectric layer on the first dielectric layer; forming a plurality of third plugs in the second dielectric layer, wherein the plurality of third plugs are respectively electrically connected with the second conductive layer, and the plurality of third plugs are respectively electrically connected with the third conductive layer; the first conductive layer is electrically connected to the third plug.
16. The method of forming a variable capacitor according to claim 14, further comprising, before forming the first conductive layer: and forming a fourth plug in the isolation structure, wherein the fourth plug is positioned in the isolation structure on the surface of the top of the gate structure and is electrically connected with the top of the gate structure.
17. The method of forming a variable capacitor according to claim 16, further comprising: and forming a fourth conducting layer in the first dielectric layer, wherein the fourth conducting layer is positioned in the first dielectric layer on the top surface of the fourth plug, and the fourth conducting layer is electrically connected with the fourth plug.
18. The variable capacitor of claim 14, further comprising: and forming a first pseudo conductive layer in the first dielectric layer between the first pseudo gate structure and the second pseudo gate structure, wherein the first pseudo conductive layer is parallel to the second conductive layer.
19. The method of forming a variable capacitor according to claim 11, wherein a material of the first plug includes a metal including: combinations of one or more of copper, aluminum, tungsten, cobalt, and titanium nitride; the material of the second plug comprises a metal comprising: one or more combinations of copper, aluminum, tungsten, cobalt, and titanium nitride.
20. The method of forming a variable capacitor according to claim 14, wherein a material of the first conductive layer includes a metal including: combinations of one or more of copper, aluminum, tungsten, cobalt, and titanium nitride; the material of the second conductive layer comprises a metal comprising: combinations of one or more of copper, aluminum, tungsten, cobalt, and titanium nitride; the material of the third conductive layer comprises a metal comprising: one or more combinations of copper, aluminum, tungsten, cobalt, and titanium nitride.
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| US20050145913A1 (en) * | 2004-01-06 | 2005-07-07 | Kabushiki Kaisha Toshiba | Semiconductor memory device with cap structure and method of manufacturing the same |
| US20120286337A1 (en) * | 2011-05-06 | 2012-11-15 | Qingqing Liang | Fin field-effect transistor and method for manufacturing the same |
| TW201539664A (en) * | 2014-01-28 | 2015-10-16 | Taiwan Semiconductor Mfg Co Ltd | FinFET varactor circuit and the froming mehtod thereof |
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