CN102623339A - Method for improving thickness uniformity of intermediate oxide layer of double-layer grid MOS structure - Google Patents
Method for improving thickness uniformity of intermediate oxide layer of double-layer grid MOS structure Download PDFInfo
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- CN102623339A CN102623339A CN2011100279143A CN201110027914A CN102623339A CN 102623339 A CN102623339 A CN 102623339A CN 2011100279143 A CN2011100279143 A CN 2011100279143A CN 201110027914 A CN201110027914 A CN 201110027914A CN 102623339 A CN102623339 A CN 102623339A
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Abstract
The invention discloses a method for improving thickness uniformity of an intermediate oxide layer of a double-layer grid MOS structure. The method comprises following steps: depositing a dielectric layer on a substrate, wherein the dielectric layer comprises a lower silicon oxide layer, a silicon nitride layer and an upper silicon oxide layer from bottom to top; defining positions of grooves by utilizing photoetching, then forming the grooves by etching the substrate, and growing a silicon oxide layer on the groove inner wall; filling the grooves by depositing a first layer of polysilicon, and then forming a first layer of polysilicon grid by carrying out back-etching on the first layer of polysilicon; filling the grooves by depositing an HDP silicon oxide layer employing an HDP technology; grinding the HDP silicon oxide layer by employing a CMP technology, stopping grinding at the silicon nitride layer, and then removing the silicon nitride layer; carrying out back-etching on the HDP silicon oxide layer and forming the intermediate oxide layer between the double layers of grid. The method of the invention facilitates the formation of the intermediate oxide layer with uniform thickness.
Description
Technical field
The present invention relates to a kind of preparation method of double-deck grid MOS structure.
Background technology
Double-deck grid MOS structure is a kind of power MOS (Metal Oxide Semiconductor) device commonly used.The technological process that has general double-deck grid MOS structure now is:
The hard mask layer of growth etching groove on substrate is generally one deck or two-layer silicon oxide layer earlier;
Then the position of lithographic definition groove is followed etching and is formed groove;
Afterwards in trench wall growth oxide layer;
Then deposit ground floor polysilicon filling groove carries out the etching first time to the ground floor polysilicon afterwards, removes to be positioned at the ground floor polysilicon on the groove;
Photoetching then protection part ground floor polysilicon (promptly be used for connect as the ground floor polysilicon part) carries out the second step etching of ground floor polysilicon, the desired depth to the groove;
Adopt high-density plasma (HDP) technology deposition oxidation film (also claiming the HDP oxide-film), filling groove;
Adopt cmp (CMP) technology to grind the HDP oxide-film, to the thick HDP oxide-film of residue 3000 dusts on substrate;
Wet etching makes the HDP oxide-film of residue 2500 dusts on the ground floor polysilicon in the groove, forms the intermediate oxide layer of double-deck grid;
Then be the growth of grid oxic horizon, the deposit of second layer polysilicon and etching, the preparation of whole double-deck grid MOS is accomplished in the formation of tagma and source region formation and contact hole, metal and passivation layer etc.
In the above-mentioned preparation flow, because CMP technology is to control through the time when grinding the HDP oxide layer, so the fluctuation of the HDP remaining thickness of CMP after handling very big (see Fig. 1, wherein Poly1 is the ground floor polysilicon).In addition, because the grinding rate of CMP technology there are differences between diverse location and silicon chip in the silicon chip face, this has also caused the homogeneity of the HDP oxide-film residual thickness after the CMP technology very poor.
Summary of the invention
The technical problem that the present invention will solve provides the method for the intermediate oxidation layer thickness homogeneity that improves double-deck grid MOS structure, and it can control the thickness evenness of intermediate oxide layer preferably.
For solving the problems of the technologies described above, the method for the intermediate oxidation layer thickness homogeneity of the double-deck grid MOS of improvement of the present invention structure comprises the steps:
Step 1, dielectric layer deposited on substrate, said dielectric layer is followed successively by lower floor's silicon oxide layer, silicon nitride layer and upper strata silicon oxide layer from top to bottom;
Step 2 utilizes lithographic definition to go out the position of groove, and the said substrate-like of etching becomes groove afterwards, and at trench wall growing silicon oxide layer;
Step 3, said groove is filled in the deposit of ground floor polysilicon, returns afterwards and carves said ground floor polysilicon formation ground floor polysilicon gate;
Step 4 adopts HDP technology deposit HDP silicon oxide layer with filling groove;
Step 5 adopts CMP technology to grind said HDP silicon oxide layer, stops on the said silicon nitride layer, then removes said silicon nitride layer;
Step 6, the HDP silicon oxide layer returns quarter, forms the intermediate oxide layer between the double-deck grid.
In the method for the invention, therefore the etching stop layer when adopting silicon nitride layer to grind as HDP silicon oxide layer CMP has greatly improved the thickness evenness that remains the HDP silicon oxide layer.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:
Fig. 1 is existing double-deck grid MOS structural section sketch map;
Fig. 2 is a method flow sketch map of the present invention;
Fig. 3 is for adopting the structural representation behind the etching formation part groove in the method for the present invention;
Fig. 4 is for adopting the structural representation behind the trench wall formation silicon nitride layer in the method for the present invention;
Fig. 5 is for adopting the structural representation behind the formation silicon nitride side wall in the method for the present invention;
Fig. 6 is for adopting the structural representation after in the completion groove, generating silica in the method for the present invention;
Fig. 7 is for adopting the structural representation after the removal of silicon nitride side wall in the method for the present invention;
Fig. 8 is the structural representation after the ground floor polysilicon gate forms in the employing method of the present invention;
Fig. 9 is for adopting the structural representation after the HDP silicon oxide layer CMP grinding in the method for the present invention;
Figure 10 is for adopting the structural representation behind the formation intermediate oxide layer in the method for the present invention;
Figure 11 is the structural representation after second layer polysilicon gate forms in the employing method of the present invention.
Embodiment
The method of the intermediate oxidation layer thickness homogeneity of the double-deck grid MOS of improvement of the present invention structure, the flow chart referring to Fig. 2 is elaborated below.
Elder generation's dielectric layer deposited on substrate.Substrate is generally silicon chip.Dielectric layer is followed successively by lower floor's silicon oxide layer, silicon nitride layer and upper strata silicon oxide layer from top to bottom.Its at the middle and upper levels silicon oxide layer do not removed and the etching barrier layer that silicon nitride layer grinds as CMP for the protection silicon nitride layer.Lower floor's silicon oxide layer can adopt hot oxygen oxidation technology to generate.Silicon nitride layer can adopt conventional technology to generate.The upper silicon nitride layer can adopt CVD method.The thickness range of upper strata silicon oxide layer: 1000～10000 dusts, thickness range 1000～2000 dusts of silicon nitride layer, thickness range 200～1000 dusts of lower floor's silicon oxide layer.
In an instantiation, the thickness of upper strata silicon oxide layer is 250 dusts, and the thickness of silicon nitride layer is 1500 dusts, and the thickness of lower floor's silicon oxide layer is 10000 dusts.
Then etching forms groove, and at trench wall growing silicon oxide layer.The etching of groove can once form, and also can carry out at twice.The silicon oxide layer of trench wall adopts hot oxygen method usually, makes silicon oxidation generate silica.
The deposit of ground floor polysilicon, filling groove returns afterwards and carves ground floor polysilicon formation ground floor polysilicon gate (see figure 8).The formation of ground floor polysilicon gate can be through two step etchings, and first step etching is for removing the unnecessary polysilicon in groove top, and polysilicon to the desired depth of following back in the ditch groove forms polysilicon gate.The deposit of ground floor polysilicon is identical with existing technology with etching.
Adopt HDP (high density plasma oxide deposit) technology deposit HDP silicon oxide layer, filling groove.
Adopt CMP (cmp) technology to grind the HDP silicon oxide layer afterwards, stop at (see figure 9) on the silicon nitride layer, then remove silicon nitride layer.Because this step CMP technology has higher selection ratio to silicon nitride, so grinding can stop at silicon nitride surface.Simultaneously because CMP can stop at silicon nitride surface, so the residual thickness of the HDP silicon oxide layer after CMP grinds is comparatively even.
The HDP silicon oxide layer is returned quarter, form the intermediate oxide layer (see figure 10) between the double-deck grid.The Hui Keke of HDP silicon oxide layer adopts wet corrosion technique.The oxide layer of residue predetermined thickness on the ground floor polysilicon gate is as the oxide layer in the middle of the double-deck grid.In one instance, the thickness of intermediate oxide layer is that 2500 Izods are right.
And then all be conventional processing step, like the growth of grid oxygen, the deposit of second layer polysilicon and etching (seeing Figure 11), the preparation of whole double-deck grate MOS device is accomplished in the formation of the formation in tagma and source region and contact hole, metal, passivation layer etc.
In the etching of above-mentioned groove, adopt the flow process of twice etching can be:
1) etching for the first time, desired depth under etched substrate to the substrate plane forms part groove (see figure 3).Before etching, need to adopt photoetching process to define the position of groove, identical with original technology.This time etching technics is also identical with original technology, adopts dry etch process usually, but the degree of depth of etching is merely the part of design gash depth, and this degree of depth can be arranged in the degree of depth of substrate consistent with intermediate oxide layer.
2) in part trench wall growing silicon oxide layer successively and silicon nitride layer (see figure 4).Silicon oxide layer adopts hot oxygen oxidizing process to generate usually.The thickness range of silicon oxide layer is 200～1000 dusts, and the thickness range of silicon nitride layer is 1000～2500 dusts, and the thickness of silicon oxide layer is 250 dusts, and the thickness of silicon nitride layer is 1800 dusts.
3) etching upper strata silicon oxide layer and silicon nitride layer are removed the silicon nitride layer that is positioned at upper strata silicon oxide layer and part channel bottom, and form silicon nitride side wall (see figure 5) at the part trenched side-wall.
4) the said substrate of etching in the part groove, the etching (see figure 6) of completion groove.Because the existence of silicon nitride side wall, the lower channel that this time etching forms is slightly narrower than upper groove.Groove pattern wide at the top and narrow at the bottom, the ground floor polysilicon that helps being filled in the groove forms fine and close structure.
5), remove the silicon nitride side wall (see figure 7) that is positioned at the part trenched side-wall afterwards at trench wall growing silicon oxide layer.
Claims (9)
1. a method of improving the intermediate oxidation layer thickness homogeneity of double-deck grid MOS structure is characterized in that, comprises the steps:
Step 1, dielectric layer deposited on substrate, said dielectric layer is followed successively by lower floor's silicon oxide layer, silicon nitride layer and upper strata silicon oxide layer from top to bottom;
Step 2 utilizes lithographic definition to go out the position of groove, and the said substrate-like of etching becomes groove afterwards, and at trench wall growing silicon oxide layer;
Step 3, said groove is filled in the deposit of ground floor polysilicon, returns afterwards and carves said ground floor polysilicon formation ground floor polysilicon gate;
Step 4 adopts HDP technology deposit HDP silicon oxide layer with filling groove;
Step 5 adopts CMP technology to grind said HDP silicon oxide layer, stops on the said silicon nitride layer, then removes said silicon nitride layer;
Step 6 is returned and is carved the HDP silicon oxide layer, forms the intermediate oxide layer between the double-deck grid.
2. the method for claim 1 is characterized in that, said step 2 is specially:
1) desired depth under the said substrate of etching to the substrate plane forms the part groove;
2) at said part trench wall growing silicon oxide layer and silicon nitride layer successively;
3) etching upper strata silicon oxide layer and silicon nitride layer are removed the silicon nitride layer that is positioned at said upper strata silicon oxide layer and said part channel bottom, and form the silicon nitride side wall at said part trenched side-wall;
4) the said substrate of etching in said part groove, the etching of completion groove;
5) at said trench wall growing silicon oxide layer, remove said silicon nitride side wall afterwards.
3. method as claimed in claim 2 is characterized in that: said part groove is consistent in the degree of depth of said substrate with intermediate oxide layer in the degree of depth of substrate.
4. like the described method of claim 1 to 3, it is characterized in that: hot oxide growth method is adopted in the growth of silicon oxide layer in the said step 2.
5. like the described method of claim 1 to 3, it is characterized in that: in the said step 1, the thickness range of upper strata silicon oxide layer: 1000～10000 dusts, thickness range 1000～2000 dusts of silicon nitride layer, thickness range 200～1000 dusts of lower floor's silicon oxide layer.
6. method as claimed in claim 5 is characterized in that: the thickness of lower floor's silicon oxide layer is 250 dusts in the said step 1, and the thickness of silicon nitride layer is 1500 dusts, and the thickness of upper strata silicon oxide layer is 10000 dusts.
7. like the described method of claim 1 to 3, it is characterized in that: in the said step 3, the thickness range of silicon oxide layer is 200～1000 dusts, and the thickness range of silicon nitride layer is 1000～2500 dusts.
8. method as claimed in claim 7 is characterized in that: the thickness of silicon oxide layer is 250 dusts in the said step 3, and the thickness of silicon nitride layer is 1800 dusts.
9. like the described method of claim 1 to 3, it is characterized in that: in the said step 6, the employing wet corrosion technique is carved in returning of HDP silicon oxide layer.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103523742A (en) * | 2013-10-24 | 2014-01-22 | 北京大学 | Radiation dosage detector of MOS structure and preparation method thereof |
| CN108172517A (en) * | 2017-12-29 | 2018-06-15 | 中航（重庆）微电子有限公司 | A kind of shield grid groove MOSFET manufacturing method |
| CN108417487A (en) * | 2018-02-07 | 2018-08-17 | 上海华虹宏力半导体制造有限公司 | The process of groove-shaped shield grid power device |
| CN113654600A (en) * | 2021-07-23 | 2021-11-16 | 无锡莱斯能特科技有限公司 | Manufacturing method of flow sensor |
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| US6265315B1 (en) * | 1998-06-24 | 2001-07-24 | Taiwan Semiconductor Manufacturing Company | Method for improving chemical/mechanical polish uniformity over rough topography for semiconductor integrated circuits |
| CN1641878A (en) * | 2004-01-12 | 2005-07-20 | 三星电子株式会社 | Semiconductor integrated circuit with laminated node contacting structure and mfg. method |
| CN101459135A (en) * | 2007-12-14 | 2009-06-17 | 上海华虹Nec电子有限公司 | Implementing method for slot type dual layer grid power MOS device construction |
| CN101536163A (en) * | 2005-06-10 | 2009-09-16 | 飞兆半导体公司 | Charge balance field effect transistor |
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2011
- 2011-01-26 CN CN2011100279143A patent/CN102623339A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US6265315B1 (en) * | 1998-06-24 | 2001-07-24 | Taiwan Semiconductor Manufacturing Company | Method for improving chemical/mechanical polish uniformity over rough topography for semiconductor integrated circuits |
| CN1641878A (en) * | 2004-01-12 | 2005-07-20 | 三星电子株式会社 | Semiconductor integrated circuit with laminated node contacting structure and mfg. method |
| CN101536163A (en) * | 2005-06-10 | 2009-09-16 | 飞兆半导体公司 | Charge balance field effect transistor |
| CN101459135A (en) * | 2007-12-14 | 2009-06-17 | 上海华虹Nec电子有限公司 | Implementing method for slot type dual layer grid power MOS device construction |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103523742A (en) * | 2013-10-24 | 2014-01-22 | 北京大学 | Radiation dosage detector of MOS structure and preparation method thereof |
| CN103523742B (en) * | 2013-10-24 | 2016-01-13 | 北京大学 | Radiation dose detector of a kind of MOS structure and preparation method thereof |
| CN108172517A (en) * | 2017-12-29 | 2018-06-15 | 中航（重庆）微电子有限公司 | A kind of shield grid groove MOSFET manufacturing method |
| CN108417487A (en) * | 2018-02-07 | 2018-08-17 | 上海华虹宏力半导体制造有限公司 | The process of groove-shaped shield grid power device |
| CN113654600A (en) * | 2021-07-23 | 2021-11-16 | 无锡莱斯能特科技有限公司 | Manufacturing method of flow sensor |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140108 |
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Effective date of registration: 20140108 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Applicant before: Shanghai Huahong NEC Electronics Co., Ltd. |
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Application publication date: 20120801 |