JP2818202B2 - Nonvolatile semiconductor memory device - Google Patents

Description

The present invention relates to a rewritable nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device in which a plurality of memory cells are connected in series to form a NAND cell. The present invention relates to a nonvolatile semiconductor memory device.

(Prior art) As an electrically rewritable non-volatile semiconductor memory device (EEPROM) capable of high integration, the applicant has previously proposed a type in which memory cells are connected in series to form a NAND cell. ing.

FIG. 4 is a plan view showing one NAND cell block of such an EEPROM, and FIGS. 5 (a) and 5 (b) are AA 'lines thereof.
And BB 'sectional drawing. In one region of the silicon substrate 21 surrounded by the element isolation insulating film 22, 8
Memory cells M1 to M8 and two select transistors S1 and S2
Are formed. Each memory cell is thinner over the first gate insulating film 23 made of an oxide film consisting of a first layer polysilicon film floating gate 24 (24 _{1-24 8)} is formed on a substrate 21, a further oxide film A control gate 26 (26 ₁ -2) made of a second-layer polycrystalline silicon film via a second gate insulating film 25
6 ₈ ) is formed. The gate insulating film of the select transistors S1, S2 are formed at the same time as the second gate insulating film, the select gate 26 _9, 26 ₁₀ are formed simultaneously with the control gate 26 by a second layer polycrystalline silicon film. An n ⁺ diffusion layer 27 serving as a source and a drain is formed between the memory cells by diffusion and connected in series so that the adjacent memory cells share the source and the drain, thereby forming a NAND cell. The writing and erasing operations of the NAND cell type EEPROM are performed by transfer of charges by a tunnel current between the substrate 21 and the floating gate 24. For example, in the batch erasing method, a high voltage is applied to the control gate and select gate of all the memory cells, and the drain and the source are grounded. As a result, electrons are injected from the substrate to the floating gate in all memory cells,
The state changes to the “1” state in which the threshold value has moved in the positive direction. Writing is performed in order from the memory cell M8 on the source side. First grounded control gate 26 ₈ and the source and the select gate 6 ₁₀ of the memory cell M8, a high voltage is applied to the remaining control gate and the drain. As a result, in the memory cell M8, electrons of the floating gate are emitted to the substrate, the threshold value moves in the negative direction, and "0" writing is performed. Hereinafter, data writing is performed in the order of the memory cells M7, M6,. Data reading is performed by grounding the control gate and source of the selected memory cell, applying a power supply potential to the remaining control gates and selection gates, and detecting the presence or absence of a current.

This NAND cell type EEPROM has the advantage that the number of contacts is significantly reduced as compared with the conventional NOR type EEPROM, and high integration is possible. However, more highly integrated EE
There is still a problem when trying to get a PROM. Although forming a NAND cell, the floating gate must be independently patterned for each memory cell. Therefore, a space is always required between the memory cells, and a diffusion layer serving as a source and a drain commonly used between adjacent cells must be formed in this portion. This causes a hindrance to high integration.

(Problems to be Solved by the Invention) As described above, a memory cell having a two-layer gate structure is used.
In the NAND cell type EEPROM, it is necessary to make a floating gate, which is a charge storage layer, independent for each memory cell, and this has a problem that further high integration is hindered.

The present invention has been made in view of the above points, and provides a NAND cell type nonvolatile semiconductor memory device that does not require patterning of a charge storage layer for each memory cell, and thus enables higher integration. The purpose is to:

[Structure of the Invention] (Means for Solving the Problems) In the present invention, a structure in which an insulating layer having an interface trap level therein is used as a charge storage layer and a control gate is stacked thereon is used as a memory cell. A NAND cell is constituted by the memory cell. In this case, an insulating layer as a charge storage layer is commonly provided for a plurality of memory cells constituting a NAND cell. As for a plurality of control gates in the NAND cell, a first-layer polycrystalline silicon gate is provided for every other cell in the NAND cell, and the remaining control gates are interpolated between the first-layer polycrystalline silicon gates. The gate is constituted by a second-layer polysilicon gate separated from the first-layer polysilicon gate by an interlayer insulating film.

(Operation) The memory cell structure itself according to the present invention is, for example, the same as that conventionally known as an MNOS memory. In this memory cell structure, unlike the case where a floating gate formed of a conductive film is used as a charge storage layer, charges trapped at an interface trap level in an insulating layer cannot move in a plane.
In forming a NAND cell, it is not necessary to separate the insulating layer for each memory cell. Therefore, by arranging the insulating layer as the charge storage layer in common for a plurality of memory cells in the NAND cell, patterning of the charge storage layer in the NAND cell becomes unnecessary. And, by using a two-layer polycrystalline silicon film for the control gate, each channel region was formed continuously without substantially requiring a space between a plurality of memory cells constituting the NAND cell. State. Therefore, the density can be almost doubled as compared with the case where the two-layer gate structure is used.

(Example) Hereinafter, an example of the present invention will be described.

FIG. 1 shows one NAND cell type EEPROM of one embodiment.
FIGS. 2A and 2B are plan views of the cell portion, and FIGS.
It is A 'and BB' sectional drawing. In this embodiment, 8
One NAND cell is constituted by the memory cells M1 to M8 and the select MOS transistors S1 and S2 provided at both ends thereof. The charge storage layers of the memory cells M1 to M8 are composed of a thin silicon oxide film 9 and a silicon nitride film 10 laminated thereon.
Are formed in common. That is, the trap level formed at the interface of the two-layer insulating film becomes the charge storage portion.
The control gates 6 ₂ , 6 ₄ , 6 ₆ , 68 of the memory cells M 2, M 4, M 6, M ₈ are formed of a first-layer polycrystalline silicon film, and the memory cells M 1, M 3 are interpolated therebetween. , M5, M7 control gate 6 ₁ ,
6 _3, 6 _5, 6 ₇ are formed by a second layer polycrystalline silicon film.

More specifically, the process will be described with reference to manufacturing process cross-sectional views shown in FIGS. 3 (a) to 3 (d). After a p-type well 8 is formed in a memory cell region of an n-type silicon substrate 1, a field insulating film 2 is formed in an element isolation region. Next, after a thin silicon oxide film 9 of, for example, about 20 ° is formed in the element region, a silicon nitride film 10 of about 300 ° is deposited on the entire surface by CVD (FIG. 3A). Then depositing a first layer polycrystalline silicon film, and patterning the control gate 6 ₂ of the first layer, 6 _4, 6 _6, 6 ₈ formed (FIG. 3 (b)). Then, after performing thermal oxidation to form a silicon oxide film 12 serving as an interlayer insulating film on the control gate to a thickness of about 500 °, a second-layer polycrystalline silicon film is deposited and patterned to form a first layer between the control gates. the control gate 6 ₁ of the second layer so as to fill a 6 _3, 6 _5, 6 ₇ to form. After the control gates of the eight memory cells are formed in an array without any space therebetween, the underlying silicon nitride film 10 is etched away using these control gates as a mask. A silicon oxide film 11 serving as an interlayer insulating film is also formed on the control gate surface of the second layer by thermal oxidation (FIG. 3C). Further depositing a third layer polycrystalline silicon film, it is patterned to form a selection gate 6 ₉ and 6 ₁₀ so as to partially overlap each control gate 6 ₁ and 6 _8. The control gate ₆₁ through ₈ and the select gate 6 _9, 6 _10, phosphorus or arsenic is ion-implanted as a mask, NAND cell both ends sources, to form an n ⁺ -type diffusion layer 7 to the drain region (3 Figure (d). Thereafter, although not shown, the entire surface is covered with a CVD oxide film, a contact hole is opened, and a metal wiring such as a bit line connected to the drain is formed.

The operation of the EEPROM of this embodiment will now be described. In the collective erasing, a positive high voltage is applied to the n-type substrate 1 and the p-type layer 8, and electrons trapped at the interface trap level between the oxide film 9 and the nitride film 10 are emitted to the substrate side. As a result, the threshold values of all the memory cells move in the negative direction and “0” data is stored.

Next, write “1” data to the source side memory cell
Perform in order from M8. First, the memory cell M8 has a positive high voltage is applied to its control gate 6 _8, giving an intermediate potential now to the control gate ₆₁ through ₇ and the select gate 6 ₉ on the drain side of the memory cell M1~M7 selection gate 6 ₁₀ and the drain and source diffusion layer 7 on the source side is grounded. As a result,
In the selected memory cell M8, electrons are injected and trapped from the substrate into the gate insulating film, and the “1” state in which the threshold value moves in the positive direction is written. This electron injection is performed by inverting the channel regions of the memory cells M1 to M7 and transmitting the ground potential of the drain to immediately below the memory cell M8.
Caused by a high electrolyte it can take between M8 of the channel region and the control gate 6 _8. Then the case of writing "1" data in the memory cell M7, addition to providing already intermediate potential to the control gate 6 ₈ has been written to the same manner as in the previous example. When the data to be written is "0", an intermediate potential may be applied to the drain to prevent electron injection.

Data read is performed by the NAND cell type EEPROM described in the conventional example.
Is the same as

As described above, according to this embodiment, a plurality of memory cells constituting a NAND cell are arranged without gaps, and compared with the case where a conventional two-layer gate structure of a floating gate and a control gate is used. The density can be greatly increased.

The present invention is not limited to the above embodiment. For example, in the embodiments, a so-called MNOS type was used as the memory cell structure. However, a silicon-rich silicon oxide containing excess silicon is used as a charge storage layer that holds the trapped charges in a state in which the trapped charges cannot move in a plane. It is also possible to use a triple layer in which silicon oxide films are provided above and below with a film interposed therebetween. In the embodiment, the select gate is formed of the third-layer polycrystalline silicon film. However, it may be formed of the second-layer polycrystalline silicon film. However, in this case, the control gate ₆₁ adjacent thereto and the selection gate 6 ₉ of at least the drain side
Is required to be separated, and an n ⁺ -type diffusion layer is formed at the separation portion.

Further, in the embodiment, the EEPROM for electrically rewriting has been described. However, the EEPROM may be configured as an ultraviolet-erasable EPROM for performing batch erasing with ultraviolet rays.

[Effects of the Invention] As described above, according to the present invention, a highly integrated nonvolatile semiconductor memory device can be provided by laying down without gaps between a plurality of memory cells constituting a NAND cell.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view showing one NAND cell part of an EEPROM according to an embodiment of the present invention, and FIGS. 2 (a) and (b) are AA 'and B of FIG. -B '
FIGS. 3 (a) to 3 (d) are cross-sectional views showing a manufacturing process thereof, FIG. 4 is a plan view showing a configuration of one NAND cell portion of a conventional EEPROM, FIGS. 5 (a) (b) ) Are AA 'and BB' in FIG.
It is sectional drawing. 1 ...... n-type silicon substrate, 8 ...... p-type layer, 2 ...... field insulating film, 9 ...... silicon oxide film, 10 ...... silicon nitride film, 11, 12 ...... interlayer insulating film, 6 _2, 6 ₄ , 6 ₆ , 6 ₈ ... Control gate (first layer polycrystalline silicon film), 6 ₁ , 6 ₃ , 6 ₅ , 6 ₇ ... Control gate (second layer polycrystalline silicon film), 6 ₉ , 6 ₁₀ ... Select gates, M1 to M8... Memory cells, S1, S2... Select MOS transistors.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 29/792 (72) Inventor Fujio Masukaoka 1st location, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Toshiba Research Institute, Inc. (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 29/788-29/792 H01L 21/8247 H01L 27/112-27/115 G11C 17/00 307

Claims (7)

(57) [Claims] A charge storage layer and a control gate are stacked on a semiconductor substrate, and a plurality of memory cells for writing and erasing data by transferring charges between the substrate and the charge storage layer are connected in series to form a NAND cell. In the nonvolatile semiconductor memory device, the charge storage layers of the plurality of memory cells constituting the NAND cell have a trap level for trapping the charge injected from the substrate without in-plane movement. A control gate of a plurality of memory cells constituting the NAND cell is constituted by an insulating layer provided in common with the memory cells, and a first layer polycrystalline silicon gate separated and formed alternately by an interlayer insulating film is provided. And a second-layer polycrystalline silicon gate. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said insulating layer constituting said charge storage layer comprises a thin silicon oxide film formed on a substrate and a silicon nitride film laminated thereon. . 3. The non-volatile semiconductor memory device according to claim 1, wherein said insulating layer constituting said charge storage layer comprises a triple layer of a silicon oxide film sandwiching a silicon-rich silicon oxide film. 4. A charge storage layer and a control gate are stacked on a semiconductor substrate, and a plurality of memory cells for writing and erasing data by transferring charges between the substrate and the charge storage layer constitute one cell unit. In a nonvolatile semiconductor memory device in which the cell units are arranged in an array, source / drain diffusion layers are arranged only at both ends of the cell unit, and the source / drain is formed of the same conductive region. A non-volatile semiconductor storage device. 5. The nonvolatile semiconductor memory device according to claim 4, wherein adjacent control gate electrodes of said cell unit are provided so as to overlap each other. 6. The non-volatile semiconductor memory device according to claim 4, wherein said charge storage layer comprises a stacked film of a silicon nitride film and a silicon oxide film. 7. The nonvolatile semiconductor memory device according to claim 4, wherein said cell unit comprises a plurality of memory cells connected in series to constitute a NAND cell.