JPH11204762A - Semiconductor nonvolatile storage device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor nonvolatile storage device in which reliability is ensured by simplifying manufacturing processes, and its manufacturing method. SOLUTION: This semiconductor nonvolatile storage device is provided with a memory transistor MT (first transistor) having a first conducting layer 30 turning to a floating gate and second conducting layers 31, 32 turning to a control gate on a substrate 10, a high voltage driving type transistor HT (second transistor) having a second gate electrode 33 in which the first conducting layer 30 and the second conducting layers 31, 32 are laminated, and a low voltage driving type transistors NLT, PTL (third transistors) having third gate electrode 35 in which the first conducting layer 30 and the second conducting layers 31, 32 are laminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor nonvolatile memory device and a method of manufacturing the same, and more particularly, to a memory transistor having a floating gate for storing electric charge between a gate electrode of a transistor and a channel forming region, and a method of manufacturing the same. The present invention relates to a semiconductor nonvolatile memory device having a high-voltage driving transistor and a low-voltage driving transistor for driving, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Instead of a magnetic storage device such as a floppy disk, an electrically rewritable semiconductor nonvolatile storage device (EEPROM: Electrically Erasable and Prog
rammable ROM) has begun to be used. As an EEPROM, a floating gate type, MNOS type or M
Structures having various features such as an ONOS type and a TEXTURED POLY type have been developed.

FIG. 10 shows a conventional example of a floating gate type semiconductor nonvolatile memory device which is one of EEPROMs. For example, as disclosed in JP-A-6-163926, a memory transistor MT having a floating gate 30 for storing charges between a gate electrode of the transistor and a channel forming region, and a memory transistor MT for driving the memory transistor For example, it has a high-voltage drive transistor HT for applying a high voltage of about Vpp and a low-voltage drive transistor (NLT, PLT) for applying a low voltage of about Vcc, for example. Each of the above transistors is an n-well 1 formed in a p-type semiconductor substrate 10.
It is formed on one or p-type well 12 or on bulk silicon of p-type semiconductor substrate 10.

The above-mentioned memory transistor has, for example, a gate insulating film 22, a floating gate 30, an intermediate insulating film 24 and a control gate 34 laminated on a channel formation region of a semiconductor substrate. Are insulated by the intermediate insulating film 24. The semiconductor substrate on both sides of the gate has source / drain diffusion layers 13 formed to be connected to the channel formation region.

In the memory transistor having the above-described structure, the floating gate has a function of retaining charges in the film, and the gate insulating film and the intermediate insulating film have a role of confining charges in the floating gate. When an appropriate voltage is applied to the control gate, the semiconductor substrate, or the source / drain diffusion layers, a Fowler-Nordheim type tunnel current is generated, and charges are injected from the semiconductor substrate to the floating gate through the gate insulating film, or the semiconductor substrate flows from the floating gate to the semiconductor substrate. Charge is released. Therefore, the gate insulating film is formed as a thin film having a thickness of several nm to several tens nm so that a tunnel current can be passed.

In the above-described memory transistor, when electric charges are accumulated in the floating gate, an electric field is generated by the accumulated electric charges, so that the threshold voltage of the transistor changes. This change allows data to be stored. For example, data can be erased by accumulating electrons in the floating gate, and data can be written by discharging electrons accumulated in the floating gate.

On the other hand, the high-voltage drive type transistor HT and the low-voltage drive type transistors (NLT, PLT) include, for example, a gate insulating film (21, 23) laminated on a channel formation region of the semiconductor substrate 10 and a gate electrode (33). , 3
And source / drain diffusion layers (13, 14) formed in the semiconductor substrate on both sides of the gate so as to be connected to the channel formation region. The gate insulating film 21 of the high voltage drive type transistor is designed to have a thickness of, for example, about several tens nm so as to withstand the applied high voltage.

In the conventional method of manufacturing a semiconductor nonvolatile memory device as described above, the formation of the gate insulating films of the memory transistor, the high-voltage driving transistor, and the low-voltage driving transistor is performed in independent steps. Further, in a conventional method, a first conductive layer is deposited and processed to form a floating gate of a memory transistor, and a second conductive layer is deposited and processed to form a control gate of a memory transistor and a high voltage drive type transistor. And a gate electrode of the low-voltage drive transistor.

[0009]

However, in the above-mentioned conventional method of manufacturing a semiconductor nonvolatile memory device,
Mask formation step and etching step for removing the first conductive layer in the formation region of the high voltage drive type transistor and the low voltage drive type transistor, gate electrode (floating gate and control gate) of memory cell transistor and high voltage drive type transistor And etching steps for patterning gate electrodes of low-voltage and low-voltage transistors, and mask formation for separately forming gate insulating films of high-voltage and low-voltage transistors Since a process, an etching process, an oxidation process, and the like are required, a large number of masks are used, and the process is complicated.

Further, according to the above-mentioned conventional method for manufacturing a semiconductor nonvolatile memory device, after a first conductive layer serving as a floating gate of a memory transistor is deposited and patterned, a high-voltage drive transistor and a low-voltage drive transistor are formed. Since the formation of the gate insulating film and the etching process are performed, the characteristics of the memory transistor may be deteriorated due to processes such as high-temperature heat treatment and plasma etching, which may cause a problem in reliability.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and accordingly, the present invention provides a memory transistor having a floating gate, a high-voltage drive transistor for driving the memory transistor, and a low-voltage drive transistor. And a method of manufacturing the same, which is capable of simplifying the manufacturing process to reduce the manufacturing cost and ensuring reliability and a method of manufacturing the same. The purpose is to do.

[0012]

To achieve the above object, a semiconductor nonvolatile memory device according to the present invention comprises a first transistor, a second transistor for driving the first transistor, and a second transistor on a semiconductor substrate. A semiconductor nonvolatile memory device having a third transistor, wherein the first transistor is formed on a first gate insulating film formed on a first channel formation region for a first transistor of the semiconductor substrate; A first conductive layer formed on the gate insulating film and serving as a floating gate; an intermediate insulating film formed on the first conductive layer; and a first conductive layer formed on the intermediate insulating film and serving as a control gate. Two conductive layers,
A memory transistor having a first source / drain region connected to the first channel formation region, wherein the second transistor is formed above a second channel formation region for a second transistor on the semiconductor substrate; First
A second gate insulating film having a thickness greater than that of the gate insulating film; and a second conductive film formed on the second gate insulating film and connected to the first conductive layer and the first conductive layer. And a second source / drain region connected to the second channel formation region, wherein the third transistor is a third transistor of the semiconductor substrate. A third gate insulating film formed in a layer above the third channel forming region and having a smaller thickness than the second gate insulating film; a third gate insulating film formed in a layer above the third gate insulating film; A third layer having the second conductive layer formed in connection with the first conductive layer;
A low-voltage drive transistor including a gate electrode and a third source / drain region connected to the third channel formation region.

In the above-mentioned semiconductor nonvolatile memory device of the present invention, in the memory transistor (first transistor), a field-effect transistor having a floating gate is provided between the control gate and a channel formation region in the semiconductor substrate. When an appropriate voltage is applied to the control gate, the semiconductor substrate, the source / drain regions, etc., a Fowler-Nordheim tunnel current is generated, and charges are injected into the floating gate or discharged from the floating gate to the semiconductor substrate. When charges are accumulated in the floating gate in this manner, an electric field is generated by the accumulated charges, so that the threshold voltage of the transistor changes. This change allows data to be stored.

The above-mentioned nonvolatile semiconductor memory device further includes a high-voltage driving transistor (second transistor) and a low-voltage driving transistor (third transistor) for driving the memory transistor. The gate insulating film (second gate insulating film) of the high-voltage driven transistor is larger than the gate insulating film (first gate insulating film) of the memory transistor and the gate insulating film (third gate insulating film) of the low-voltage driven transistor. It is formed in a thick film and has a structure that can withstand the applied high voltage.

Further, in the above-mentioned semiconductor nonvolatile memory device, the gate electrodes (the second gate electrode and the third gate electrode) of the high voltage drive type transistor and the low voltage drive type transistor are provided.
The gate electrode is formed by connecting a first conductive layer serving as a floating gate and a second conductive layer serving as a control gate in each memory transistor. For the connection between the first conductive layer and the second conductive layer, a connection portion such as a contact may be provided, or the first conductive layer and the second conductive layer may be stacked and connected. Therefore, a mask forming step and an etching step for removing the first conductive layer in the formation region of the high voltage drive type transistor and the low voltage drive type transistor, the gate electrode (floating gate and control gate) of the memory cell transistor and the high voltage drive It has a structure that can be manufactured by simplifying the process, such as an independent mask forming process and an etching process for patterning the gate electrodes of the type transistor and the low voltage drive type transistor.
Manufacturing costs can be reduced. In order to manufacture a semiconductor nonvolatile memory device having the above structure, a gate insulating film of a high-voltage driving transistor and a low-voltage driving transistor are formed and an etching process is performed after forming a floating gate of a memory transistor. Therefore, it is not necessary to perform a high-temperature heat treatment or a plasma etching process, so that deterioration of the characteristics of the memory transistor due to each of the above processes can be avoided, and reliability can be ensured.

In the semiconductor nonvolatile memory device according to the present invention, preferably, the first gate electrode is provided at the second gate electrode.
A conductive layer and the second conductive layer are formed by lamination, and the third gate electrode includes the first conductive layer and the second conductive layer.
The conductive layers are formed by lamination. Thereby, the gate electrodes (the second gate electrode and the third gate electrode) of the high voltage drive type transistor and the low voltage drive type transistor
Can connect the first conductive layer and the second conductive layer, respectively.

In the above-described semiconductor nonvolatile memory device of the present invention, preferably, the first gate insulating film and the third gate insulating film have the same thickness. This makes it possible to simultaneously form the first gate insulating film and the third gate insulating film, thereby making it possible to further simplify the manufacturing process and manufacture the semiconductor device.

The semiconductor nonvolatile memory device of the present invention preferably has an n-channel transistor and a p-channel transistor as the third transistor. In a complementary MOS (CMOS) integrated circuit having n-channel and p-channel MOS transistors, power consumption in a stationary state can be reduced to a negligible level.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor non-volatile memory device, comprising the steps of: forming a first transistor as a memory transistor on a semiconductor substrate; A method for manufacturing a semiconductor nonvolatile memory device having a second transistor which is a voltage-driven transistor and a third transistor which is a low-voltage transistor, wherein a first channel formation region is formed in a first transistor formation region of the semiconductor substrate. Forming a second channel forming region in the second transistor forming region, forming a third channel forming region in the third transistor forming region, and forming a first gate insulating film on the first channel forming region. A second gate insulating film having a thickness greater than that of the first gate insulating film formed on the second channel forming region. Formed, and forming the third thin film thickness than the upper layer of the channel formation region a second gate insulating film third gate insulating film, the first gate insulating film,
Forming a first conductive layer above the second gate insulating film and the third gate insulating film, and forming an intermediate insulating film above the first conductive layer in the first transistor formation region; Forming a second conductive layer on the intermediate insulating film in the first transistor formation region and on the second conductive layer in the second transistor formation region and the third transistor formation region; The second conductive layer, the intermediate insulating film, and the first conductive layer are patterned into a floating gate and a control gate pattern in a formation region, and the second conductive layer and the first conductive layer are formed in the second transistor formation region. Patterning into a second gate electrode pattern, and forming the second conductive layer in the third transistor formation region; Patterning the first conductive layer into a third gate electrode pattern, a first source / drain region connected to the first channel formation region, and a second source / drain connected to the second channel formation region Forming a region and a third source / drain region connected to the third channel formation region.

In the method of manufacturing a semiconductor nonvolatile memory device according to the present invention, a first channel formation region is formed in a first transistor formation region of a semiconductor substrate, and a second channel formation region is formed in a second transistor formation region. Forming a third channel formation region in the third transistor formation region. next,
Forming a first gate insulating film above the first channel forming region, forming a second gate insulating film thicker than the first gate insulating film above the second channel forming region, and forming a third channel forming region A third gate insulating film thinner than the second gate insulating film is formed as an upper layer. Next, a first conductive layer is formed over the first gate insulating film, the second gate insulating film, and the third gate insulating film. Next, an intermediate insulating film is formed over the first conductive layer in the first transistor formation region.
Next, a second conductive layer is formed on the intermediate insulating film in the first transistor formation region and on the first conductive layer in the second transistor formation region and the third transistor formation region. Next, the second transistor is formed in the first transistor formation region.
Patterning the conductive layer, the intermediate insulating film, and the first conductive layer into a floating gate and a control gate pattern; patterning the second conductive layer and the first conductive layer into a second gate electrode pattern in a second transistor formation region; In the three transistor formation region, the second conductive layer and the first conductive layer are patterned into a third gate electrode pattern. Next, a first source / drain region connected to the first channel formation region, a second source / drain region connected to the second channel formation region, and a third source / drain region connected to the third channel formation region To form

According to the method of manufacturing a semiconductor nonvolatile memory device, a floating gate (first conductive layer) is provided between the control gate (second conductive layer) and the channel forming region in the semiconductor substrate in the first transistor forming region. A first transistor (memory transistor) having a layer is formed. In the second transistor formation region, a second transistor (high-voltage driven transistor) having a stacked body of the second conductive layer and the first conductive layer as a second gate electrode is formed.
In the third transistor formation region, a third transistor (a low-voltage drive transistor) having a stacked body of the second conductive layer and the first conductive layer as a third gate electrode is formed.

According to the method of manufacturing a semiconductor nonvolatile memory device described above, a mask for removing the first conductive layer in a region where a high-voltage driving transistor and a low-voltage driving transistor are formed, which is required by a conventional method, is formed. Process and etching process, independent mask formation process and etching process for patterning the gate electrodes (floating gate and control gate) of the memory cell transistor and the gate electrodes of the high voltage driving transistor and the low voltage driving transistor Omitted,
Since it is possible to simplify the manufacturing process and manufacture,
Manufacturing costs can be reduced. In addition, before forming the floating gate of the memory transistor, a gate insulating film of a high-voltage driving transistor and a low-voltage driving transistor is formed, and plasma etching is performed in processing a gate electrode pattern of the high-voltage and low-voltage driving transistors. Since the number of processes can be reduced, it is possible to avoid the deterioration of the gate insulating film (tunnel insulating film) of the memory transistor due to the occurrence of stress due to the high-temperature heat treatment and the diffusion of impurities in these processes, and to ensure the reliability of the semiconductor nonvolatile memory. A storage device can be manufactured.

In the method of manufacturing a semiconductor nonvolatile memory device according to the present invention, preferably, the step of forming the intermediate insulating film includes the step of forming the first transistor forming region and the second transistor forming region.
In the transistor forming region and the third transistor forming region, an intermediate insulating film is formed over the entire surface of the first conductive layer, and the second transistor forming region and the second transistor forming region are left except for the intermediate insulating film in the first transistor forming region. The intermediate insulating film formed in the third transistor formation region is removed. Thus, the first conductive layer and the second conductive layer can be stacked and formed in the second transistor formation region and the third transistor formation region.

In the method of manufacturing a semiconductor nonvolatile memory device according to the present invention, preferably, the first gate insulating film and the third gate insulating film are formed simultaneously. This makes it possible to further simplify the manufacturing process and manufacture.

In the method of manufacturing a semiconductor nonvolatile memory device according to the present invention, preferably, the step of forming the first gate insulating film, the second gate insulating film, and the third gate insulating film is performed by the first gate insulating film. Forming an insulating film to be a part of a second gate insulating film in the channel forming region, the second channel forming region, and the third channel forming region; and forming the insulating film in the first channel forming region and the third channel forming region. A step of removing the insulating film that becomes a part of the second gate insulating film; and a step of forming a second gate insulating film by thickening the insulating film that becomes a part of the second gate insulating film. This makes it possible to form the second gate insulating film thicker than the first gate insulating film and the third gate insulating film, and to increase the thickness of the insulating film that becomes a part of the second gate insulating film. At the same time, the first gate insulating film and the third gate insulating film can be formed at the same time.

In the method of manufacturing a semiconductor nonvolatile memory device according to the present invention, preferably, in the step of increasing the thickness of an insulating film that becomes a part of the second gate insulating film, the first and second gate insulating films are simultaneously formed.
Forming a gate insulating film and the third gate insulating film;
This makes it possible to further simplify the manufacturing process and manufacture.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a semiconductor nonvolatile memory device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of a floating gate type semiconductor nonvolatile memory device according to this embodiment. For example, L
A memory transistor (MT) and a memory transistor (M) are formed on an active region of the semiconductor substrate 10 separated by an element isolation insulating film (not shown) formed by the OCOS method or the like.
A high-voltage driving MOS transistor (HT), an n-channel low-voltage driving MOS transistor (NLT), and a p-channel low-voltage driving MOS transistor (PLT) for driving T) are formed, respectively.

The above-mentioned memory transistor MT is, for example, a p-type semiconductor in an n-type well 11 formed in a p-type semiconductor substrate 10.
The mold well 12 has a channel formation region. A first gate insulating film (tunnel insulating film) 22 having a thickness of, for example, about 10 nm is formed above the channel formation region.
A first conductive layer 30 made of, for example, polysilicon and serving as a floating gate is formed thereon. An intermediate insulating film 24 that is, for example, an ONO film (a stacked body of an oxide film, a nitride film, and an oxide film) is formed thereon. On the lower layer, a lower second conductive layer 31 made of, for example, polysilicon
Second conductive layer 32 made of tungsten and tungsten silicide
A control gate 34 having a polycide structure, which is a laminate of the above, is formed. Sidewall insulating films 25 are formed on both sides of these gate electrodes, and an n-type source / drain containing an n-type conductive impurity is formed in p-type well 12.
A drain diffusion layer 13 is formed. As described above, the memory transistor MT is configured.

The above-mentioned high voltage drive type transistor HT is
For example, a high voltage of about Vpp is applied and used. For example, a p-type semiconductor substrate 10 has a channel formation region directly. A second gate insulating film 21 having a thickness of, for example, about 40 nm is formed on an upper layer of the channel forming region, and a first conductive layer 30 of, for example, polysilicon, for example, a lower second conductive layer of, for example, polysilicon is formed thereon. A first conductive layer 30 and a lower second conductive layer 31 are formed by laminating a layer 31 and an upper second conductive layer 32 made of tungsten silicide.
A second gate electrode 33 is formed from the upper second conductive layer 32. Sidewall insulating films 25 are formed on both sides of these gate electrodes.
An n-type source / drain diffusion layer 13 containing an n-type conductive impurity is formed therein. As described above, the high voltage drive type transistor HT is configured.

The above-mentioned low-voltage driving transistor is an n-channel low-voltage driving transistor NLT.
In addition, a p-channel type low voltage driving transistor PLT is formed, and a low voltage of, for example, about Vcc is applied and used. The n-channel type low voltage drive type transistor NLT is, for example, a p-type semiconductor substrate 10 formed on a p-type semiconductor substrate 10.
The mold well 12 has a channel forming region. A third layer having a thickness of, for example, about 10 nm is formed on the upper layer of the channel formation region.
A gate insulating film 23 is formed, and a first conductive layer 30 made of, for example, polysilicon, a lower second conductive layer 31 made of, for example, polysilicon, and an upper second conductive layer 32 made of tungsten silicide are stacked thereon. The third gate electrode 35 is formed from the first conductive layer 30, the lower second conductive layer 31, and the upper second conductive layer 32. Sidewall insulating films 25 are formed on both sides of these gate electrodes, and n-type source / drain diffusion layers 13 containing n-type conductive impurities are formed in p-type well 12.
Are formed. As described above, the n-channel low-voltage drive transistor NLT is configured. On the other hand, the p-channel type low voltage drive transistor PLT has a channel formation region in an n-type well 11 formed in a p-type semiconductor substrate 10 and has a p-type source containing p-type conductive impurities. Except for having the drain diffusion layer 14, it is almost the same as the n-channel type low voltage drive transistor NLT.

In the memory transistor of the semiconductor nonvolatile memory device described above, the first conductive layer 30 has a function as a floating gate for retaining charges in the film, and the gate insulating film 22 and the intermediate insulating film 24 float charges. Has the role of confined in the gate. Control gate 34 or n-type source / drain diffusion layer 13
When an appropriate voltage is applied, a Fowler-Nordheim type tunnel current is generated, and charges are injected from the semiconductor substrate 10 to the floating gate through the first gate insulating film 22 or charges are released from the floating gate to the semiconductor substrate 10. . For example, charge is injected from the substrate to the floating gate by applying a high potential to the control gate 31 and applying a ground potential to the n-type source / drain diffusion layer 13.

When electric charges are accumulated in the floating gate as described above, an electric field is generated by the accumulated electric charges, so that the threshold voltage of the transistor changes. This change allows data to be stored. For example, data can be erased by accumulating electrons in the floating gate, and data can be written by discharging electrons accumulated in the floating gate.

The gate insulating film (second gate insulating film) 21 of the high voltage drive type MOS transistor (HT) is
The gate insulating film (first gate insulating film) 22 of the memory transistor (MT) and the gate insulating film (third gate insulating film) 23 of the low voltage drive type MOS transistor are formed to be thicker than the gate insulating film and the applied high voltage. Designed to withstand voltage.

The semiconductor nonvolatile memory device having such a structure is as follows.
The gate electrodes (the second gate electrode 33 and the third gate electrode 35) of the high voltage drive type transistor (HT) and the low voltage drive type transistors (NLT, PLT) are each a first conductive layer 30 which becomes a floating gate in the memory transistor. And a second conductive layer (31, 32) serving as a control gate. Therefore,
The structure can be manufactured by simplifying the process as compared with the related art, and the manufacturing cost can be reduced. Further, in order to manufacture the semiconductor nonvolatile memory device having the above structure, after forming the floating gate (first conductive layer) 30 of the memory transistor, the gate insulating film of the high-voltage driving transistor and the low-voltage driving transistor is formed. Since it is not necessary to perform high-temperature heat treatment or plasma etching treatment for forming and etching steps, deterioration of characteristics of the memory transistor due to each of the above treatments can be avoided and reliability can be secured. .

A method for manufacturing the semiconductor nonvolatile memory device according to this embodiment will be described. First, as shown in FIG. 2, an element isolation insulating film (not shown) is formed on, for example, a p-type semiconductor substrate 10 by, for example, a LOCOS method or the like.
0, a memory transistor (hereinafter abbreviated as MT) formation region,
A high voltage drive type transistor (hereinafter abbreviated as HT) formation region,
An n-channel type low voltage drive type transistor (hereinafter abbreviated as NLT) formation region and a p-channel type low voltage drive type transistor (hereinafter abbreviated as PLT) formation region are formed. Next, M
A resist film having an opening in the T formation region and the PLT formation region is patterned and formed, and an n-type conductive impurity such as phosphorus is ion-implanted to form an n-type well 11 in the MT formation region and the PLT formation region. Next, a resist film having an opening in the MT formation region and the NLT formation region is patterned and formed, and a p-type conductive impurity such as boron is ion-implanted, and the p-type impurity is implanted in the n-type well 11 in the MT formation region and in the NLT formation region. A well 12 is formed. Next, an oxide film 20 having a thickness of, for example, 30 nm is formed by, for example, a thermal oxidation method.

Next, as shown in FIG. 3, a resist film R for protecting the HT formation region by a photolithography process
1 is patterned and etched by, for example, RIE (reactive ion etching) to form an MT formation region,
The oxide film 20 in the NLT formation region and the PLT formation region is removed.

Next, as shown in FIG. 4, the thickness of the oxide film 20 is increased by 10 nm by, for example, a thermal oxidation method.
An HT gate insulating film (second gate insulating film) 21 having a thickness of nm is formed. At this time, the MT formation region, the NLT formation region, and the PLT formation region also
An oxide film having a thickness of 0 nm is grown, and a first gate insulating film (tunnel insulating film) 22 is formed in the MT formation region.
The third gate insulating film 23 is formed in the LT formation region and the PLT formation region. Since the first gate insulating film 22 and the third gate insulating film 23 are designed to have the same thickness, they can be formed simultaneously. In the case where the first gate insulating film 22 and the third gate insulating film 23 are formed with different film thicknesses, the above steps (the step of forming the resist film, the etching removal of the gate insulating film in a region not protected by the resist film) are performed. By repeating the process and the thermal oxidation process on the entire surface, gate insulating films having different thicknesses can be formed.

Next, as shown in FIG.
Polysilicon is deposited in a thickness of about 100 nm on the entire surface of the HT formation region, the NLT formation region and the PLT formation region by, for example, a CVD method (Chemical Vapor Deposition).
The first conductive layer 30 is formed by performing patterning for dividing a control gate to be formed later in the wiring direction.
Next, O is formed on the first conductive layer 30 by, for example, a CVD method.
An NO film (a stacked body of an oxide film, a nitride film, and an oxide film) is deposited, and an intermediate insulating film 24 is formed.

Next, as shown in FIG. 6, a resist film R for protecting the MT formation region by a photolithography process.
2 is patterned and etched, for example, by RIE, to form an HT formation region, an NLT formation region, and a PLT.
The intermediate insulating film 24 in the formation region is removed.

Next, as shown in FIG. 7, in the MT formation region, the HT formation region, NL
In the T formation region and the PLT formation region, polysilicon is deposited on the entire surface of the first conductive layer 30 by, for example, a CVD method to form a lower second conductive layer 31. next,
Tungsten silicide is deposited on the lower second conductive layer 31 by, for example, a CVD method to form the upper second conductive layer 32. HT forming region, NLT forming region and PLT
In the formation region, the first conductive layer 30 and the second conductive layer are stacked and connected.

Next, as shown in FIG. 8, a resist film R3 having a control gate wiring pattern of MT and wiring patterns of gate electrodes of HT, NLT and PLT is formed by a photolithography process, and etching such as plasma etching is performed. Then, the first conductive layer 30, the intermediate insulating film 24, the lower second conductive layer 31, and the upper second conductive layer 32 are patterned. Thus, in the MT formation region, the first conductive layer 30 can be used as a floating gate, and the second conductive layers (31, 32) can be used as the control gate. In the HT formation region, a second gate electrode 33 formed by stacking the first conductive layer 30 and the second conductive layers (31, 32) can be used. In the NLT formation region and the PLT formation region, the first conductive layer 30 and the second conductive layer (31, 32)
Can be used as the third gate electrode 35 formed by laminating them.

Next, in the MT formation region, using the control gate 34 as a mask, an n-type conductive impurity such as phosphorus is ion-implanted to form an n-type source / drain diffusion layer 13 to form the memory transistor MT. Finalize. In the HT formation region, an n-type conductive impurity such as phosphorus is ion-implanted using the second gate electrode 33 as a mask to form an n-type source / drain diffusion layer 13 to complete the high voltage drive transistor HT. . NLT
In the formation region, an n-type conductive impurity such as phosphorus is ion-implanted using the third gate electrode 33 as a mask, and an n-type source / drain diffusion layer 13 is formed to form an n-channel low-voltage drive transistor NLT. Finalize.
In the PLT formation region, p-type conductive impurities such as boron are ion-implanted using the third gate electrode 33 as a mask, and a p-type source / drain diffusion layer 14 is formed to form a p-channel low-voltage drive transistor PLT. To complete. Next, silicon oxide is deposited by, for example, a CVD method, and the entire surface is etched back by RIE or the like to form sidewall insulating films 25 on both sides of the gate electrode. In the formation of each of the source / drain diffusion layers described above, ions may be implanted before and after the formation of the sidewall insulating film to form a source / drain diffusion layer having an LDD (Lightly Doped Drain) structure. As described above, FIG.
Can be obtained.

According to the method of manufacturing a semiconductor nonvolatile memory device of the present embodiment, the first conductive layer in the formation region of the high-voltage drive transistor and the low-voltage drive transistor, which is required by the conventional method, is removed. Mask forming step and etching step, and independent mask forming step for patterning the gate electrodes (floating gate and control gate) of the memory cell transistor and the gate electrodes of the high voltage driving transistor and the low voltage driving transistor. Since an etching process and the like can be omitted and the manufacturing process can be simplified, the manufacturing cost can be reduced. In addition, before forming the floating gate of the memory transistor, a gate insulating film of a high-voltage driving transistor and a low-voltage driving transistor is formed, and plasma etching is performed in processing a gate electrode pattern of the high-voltage and low-voltage driving transistors. Since the number of processes can be reduced, it is possible to avoid deterioration of the gate insulating film (tunnel insulating film) of the memory transistor due to generation of stress due to high-temperature heat treatment and diffusion of impurities in these processes, and to ensure reliability of the semiconductor nonvolatile memory. A storage device can be manufactured.

Further, according to the method of manufacturing a semiconductor nonvolatile memory device of the present embodiment, the steps of the base steps of the memory transistor, the high-voltage drive type transistor and the low-voltage drive type transistor, and the respective gate electrodes are formed by patterning. Since the thickness of the film to be etched at the time is almost equal, a reduction in photolithography process margin due to a large step and a difference in etching conditions due to a difference in film thickness are eliminated, and a memory transistor, a high voltage drive transistor and a low voltage drive are used. It is possible to simultaneously pattern and form each gate electrode of the type transistor.

In the method of manufacturing the semiconductor nonvolatile memory device according to the present embodiment, when the intermediate insulating film 24 is formed, as shown in FIG.
A stacked body of a conductive layer (third conductive layer) 36 of about nm can be formed. In this case, when removing the intermediate insulating film 24 in the HT formation region, the NLT formation region and the PLT formation region, the third conductive layer 36 in the same region is also removed, and the third conductive layer 36 remaining in the MT formation region is controlled. Gate 3
Part 4 When this third conductive layer 36 is formed, H
Since the intermediate insulating film 24 in the MT formation region is covered with the third conductive layer 36 when the intermediate insulating film 24 is removed in the T formation region, the NLT formation region, and the PLT formation region, the HT formation region is used as a mask. , The native oxide film formed on the upper surface of the first conductive layer 30 in the NLT formation region and the PLT formation region can be removed by etching, and the first conductive layer 30 in the HT formation region, the NLT formation region and the PLT formation region can be removed. Second conductive layer (31, 32)
Electrical connection can be stabilized.

The semiconductor nonvolatile memory device of the present invention is not limited to the above embodiment. For example, the floating gate has a single-layer structure of polysilicon, but may have a multi-layer structure. The source / drain diffusion layer is L
Various structures such as a DD structure can be adopted. The semiconductor memory device can be a NAND type, an AND type, or a DINOR type.
The injection of charges into the charge storage layer may be performed in any case of writing or erasing data. In addition, various changes can be made without departing from the gist of the present invention.

[0048]

According to the semiconductor non-volatile memory device of the present invention, the structure can be manufactured by simplifying the process as compared with the conventional one, and the manufacturing cost can be reduced.
In addition, deterioration of characteristics of the memory transistor due to high-temperature heat treatment or plasma etching can be avoided, and reliability can be ensured.

Further, according to the method of manufacturing a semiconductor nonvolatile memory device of the present invention, the above-described semiconductor nonvolatile memory device of the present invention can be manufactured, and the manufacturing process can be simplified. Therefore, the manufacturing cost can be reduced, and the deterioration of the gate insulating film (tunnel insulating film) of the memory transistor due to the high-temperature heat treatment or the plasma etching treatment can be avoided. Can be manufactured.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor nonvolatile memory device according to an embodiment.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of the method for manufacturing the semiconductor nonvolatile memory device according to the embodiment, up to the step of forming an oxide film.

FIG. 3 shows a step that follows the step shown in FIG. 2 up to the step of removing the oxide film in the region excluding the high-voltage drive transistor formation region.

FIG. 4 shows a step subsequent to that of FIG. 3, and includes steps up to a step of thickening an oxide film in a high-voltage drive transistor formation region and forming an oxide film in a region excluding the high-voltage drive transistor formation region. Show.

FIG. 5 shows a step that follows the step shown in FIG. 4 up to the step of forming an intermediate insulating film.

FIG. 6 shows a step subsequent to that of FIG. 5, and shows a step until a step of removing an intermediate insulating film in a region excluding a memory transistor formation region.

FIG. 7 shows a step that follows the step shown in FIG. 6 up to the step of forming a second conductive layer.

FIG. 8 shows a step that follows the step shown in FIG. 7 up to the step of patterning the gate electrode of each transistor.

FIG. 9 is a sectional view of a modified example of the semiconductor nonvolatile memory device according to the embodiment;

FIG. 10 is a cross-sectional view of a conventional semiconductor nonvolatile memory device.

[Explanation of symbols]

10 ... p-type semiconductor substrate, 11 ... n-type well, 12 ... p-type well, 13 ... n-type source / drain diffusion layer, 14 ... p
Type source / drain diffusion layers, 20 ... oxide film, 21 ... second
Gate insulating film, 22 first gate insulating film, 23 third gate insulating film, 24 intermediate insulating film, 25 sidewall insulating film, 30 first conductive layer, 31 lower second conductive layer, 3
2: Upper second conductive layer, 33: second gate electrode, 34: control gate, 35: third gate electrode, 36: third
Conductive layers, R1 to R3: resist film, MT: memory transistor, HT: high-voltage drive transistor, NLT: n
Channel type low voltage drive type transistor, PLT ... p channel type low voltage drive type transistor.

Claims (9)

[Claims] 1. A non-volatile semiconductor memory device comprising a first transistor, a second transistor for driving the first transistor, and a third transistor on a semiconductor substrate, wherein the first transistor is a semiconductor memory. A first gate insulating film formed on a first channel formation region for a first transistor of the substrate, a first conductive layer formed on the first gate insulating film and serving as a floating gate, An intermediate insulating film formed on the conductive layer, a second conductive layer formed on the intermediate insulating film and serving as a control gate, and a first conductive layer connected to the first channel formation region.
A memory transistor having a source / drain region, wherein the second transistor is formed in an upper layer of a second channel formation region for a second transistor on the semiconductor substrate, and is thicker than the first gate insulating film. A second gate insulating film formed on the second gate insulating film;
A second conductive layer connected to the first conductive layer;
A high-voltage driving transistor having a second gate electrode having a conductive layer and a second source / drain region connected to the second channel formation region, wherein the third transistor is a third transistor of the semiconductor substrate. A third gate insulating film, which is formed in a layer above the third channel forming region for use and is thinner than the second gate insulating film, and which is formed in an upper layer of the third gate insulating film,
A second conductive layer connected to the first conductive layer;
A semiconductor non-volatile memory device which is a low-voltage drive transistor having a third gate electrode having a conductive layer and a third source / drain region connected to the third channel formation region. 2. The second gate electrode is formed by laminating the first conductive layer and the second conductive layer, and the third gate electrode is formed by laminating the first conductive layer and the second conductive layer. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said semiconductor nonvolatile memory device is formed by laminating. 3. The nonvolatile semiconductor memory device according to claim 1, wherein said first gate insulating film and said third gate insulating film have the same thickness. 4. The semiconductor nonvolatile memory device according to claim 1, wherein said third transistor includes an n-channel transistor and a p-channel transistor. 5. A semiconductor device comprising a first transistor as a memory transistor, a second transistor as a high-voltage driving transistor for driving the first transistor, and a third transistor as a low-voltage driving transistor for driving the first transistor. A method for manufacturing a semiconductor nonvolatile memory device, comprising: forming a first channel formation region in a first transistor formation region of a semiconductor substrate; forming a second channel formation region in a second transistor formation region; Forming a third channel formation region in the formation region; forming a first gate insulating film on the first channel formation region; forming a third gate formation film on the second channel formation region; A second gate insulating film having a large thickness is formed, and a second gate insulating film having a thickness greater than that of the second gate insulating film is formed on the third channel formation region. Forming a third gate insulating film; forming a first conductive layer on the first gate insulating film, the second gate insulating film, and the third gate insulating film; and forming the first transistor Forming an intermediate insulating film on the first conductive layer in the region; forming an intermediate layer on the intermediate insulating film in the first transistor forming region; the second transistor forming region;
Forming a second conductive layer on the first conductive layer in the transistor formation region; and controlling the second conductive layer, the intermediate insulating film and the first conductive layer in the first transistor formation region by a floating gate and a control. Pattern processing into a gate pattern, patterning the second conductive layer and the first conductive layer into a second gate electrode pattern in the second transistor formation region, and processing the second conductive layer and the Patterning a first conductive layer into a third gate electrode pattern; a first source / drain region connected to the first channel formation region; and a second source connected to the second channel formation region.
A method for manufacturing a semiconductor non-volatile memory device, comprising: forming a source / drain region and a third source / drain region connected to the third channel formation region. 6. The step of forming the intermediate insulating film, wherein in the first transistor forming region, the second transistor forming region, and the third transistor forming region, an intermediate insulating film is formed over the entire surface of the first conductive layer. 6. The non-volatile semiconductor device according to claim 5, wherein a film is formed, and the intermediate insulating film formed in the second transistor forming region and the third transistor forming region is removed while leaving the intermediate insulating film in the first transistor forming region. A method for manufacturing a storage device. 7. The method according to claim 5, wherein said first gate insulating film and said third gate insulating film are simultaneously formed. 8. The step of forming the first gate insulating film, the second gate insulating film, and the third gate insulating film includes the steps of: forming the first channel forming region, the second channel forming region, and the third channel forming region. Forming an insulating film that becomes a part of the second gate insulating film, and removing the insulating film that becomes a part of the second gate insulating film in the first channel forming region and the third channel forming region. 6. A step of forming a second gate insulating film by thickening an insulating film that becomes a part of the second gate insulating film.
The manufacturing method of the semiconductor nonvolatile memory device described in the above. 9. The non-volatile semiconductor device according to claim 8, wherein said first gate insulating film and said third gate insulating film are formed simultaneously in the step of increasing the thickness of the insulating film which becomes a part of said second gate insulating film. A method for manufacturing a storage device.