JPH11214639A - Dielectric memory and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a dielectric memory and manufacture thereof whereby a self-aligning process can be applied for forming contacts, even in memory cell regions and dummy regions to thereby simplify the manufacturing process. SOLUTION: At a memory cell region 3, patterns of word lines WL1-WLn are formed with the same spacings as a pitch F between bit lines BL1, BL2. In a dummy cell region 4, the spacing between dummy word lines WL1, WL2 is made wide in accordance with the difference in the capacitor size from the memory region 3. At the dummy cell region 4, electrically inoperative mechanical word lines MWL1, MWU2 are provided, and the pitch between the word lines is set to the same value as that of the memory cell region 3. Hence in the dummy region 4, a self-aligning process is applied also, similar to the memory cell region 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dielectric memory provided with a dielectric capacitor using a ferroelectric film or a high dielectric film and a method for manufacturing the same, and more particularly to a method for generating a reference potential (reference potential). The present invention relates to a dielectric memory provided with a dummy cell region having a dielectric capacitor having a large storage capacitance and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, with the progress of film forming technology, nonvolatile dielectric memories using a ferroelectric thin film or a high dielectric thin film have been actively developed. The dielectric memory is a ferroelectric random access memory (Ferroelectric Random Access Memories; FeRA) that can be rewritten at a high speed by using a high-speed polarization reversal of a dielectric thin film and its dielectric polarization.
M), which is advantageous in that the written contents are not erased, unlike a volatile memory in which the written information is erased when the power is turned off.

[0003] This dielectric memory uses a conventional DRAM (Dy).
(Namic Random Access Memory). In the DRAM fabrication process, when the 1G bit class is reached, the bit contacts and node contacts are self-aligned (self-aligned).
Is formed. Therefore, when a dielectric memory is highly integrated, self-alignment is indispensable when forming each contact.

By the way, in a DRAM, "0", "1"
(1/2) Vcc (Vcc;
Power supply potential). On the other hand, in the case of the dielectric memory, when the reference potential is generated in the same manner as in the DRAM, the signal amount as the reference potential decreases, and in the case of Vcc writing, the potential drops to V _ss due to junction leak. Since a refresh is required like a DRAM, a dummy cell (reference cell) having a transistor and a dielectric capacitor as in the memory cell area
It is considered that a method in which a region is formed and a reference potential is generated using the dummy cell region becomes mainstream.

[0005]

However, a dielectric memory of the type in which such a dummy cell region is provided to generate a reference potential has the following problems. That is,
For example, in a so-called 1T / 1C type dielectric memory including one transistor and one dielectric capacitor, the gate electrode of the transistor also serves as a word line, but has two impurity regions ( The source / drain) is electrically connected to a bit line via a bit contact (contact plug layer) and to one electrode of a dielectric capacitor via a node contact (contact plug layer). For high integration, it is a problem how to reduce the area required for the node contact and the bit contact. For that purpose, it is essential to apply the self-alignment process as described above.

However, the capacitor in the dummy cell region is used every time reading or writing is performed in the memory cell region and used more frequently than the capacitor in the memory cell region that is selectively used. It is necessary to set a large value (for example, about 3 to 5 times the capacitance of the capacitor on the memory cell region side). For this reason, in the dummy cell region, the pitch of the word lines becomes wider than the memory cell region in accordance with the size of the capacitor, and there is a problem that the self-alignment process cannot be applied when forming the node contacts and the bit contacts.

The present invention has been made in view of such a problem, and an object thereof is to apply a self-alignment process to contact formation even in a memory cell region and a dummy region, thereby simplifying a manufacturing process. An object of the present invention is to provide a dielectric memory and a method of manufacturing the same.

[0008]

SUMMARY OF THE INVENTION A dielectric memory according to the present invention is provided with a memory cell region having a dielectric capacitor and juxtaposedly with the memory cell region, and is provided with a dielectric capacitor higher than the dielectric capacitor on the memory cell region side. And a plurality of first conductive lines provided at a predetermined pitch in the memory cell region and different from the first conductive lines in the dummy cell region. A plurality of second conductive lines provided at a pitch;
The dummy cell region includes a third conductive line that is not electrically operated and that is provided adjacent to the second conductive line such that a distance between the dummy cell regions is equal to a pitch between the first conductive lines.

In another dielectric memory according to the present invention, a memory cell region having a dielectric capacitor and a dummy cell region having a dielectric capacitor having a larger storage capacity than the dielectric capacitor on the memory cell region side are formed on a semiconductor substrate. A dielectric memory comprising: a plurality of impurity regions selectively provided in a semiconductor substrate in a memory cell region and a dummy cell region; and a plurality of impurity regions provided at a predetermined pitch on a surface of the semiconductor substrate in the memory cell region via an insulating film. A plurality of first conductive lines, a plurality of second conductive lines provided at a different pitch from the first conductive lines via an insulating film on the surface of the semiconductor substrate in the dummy cell region, and a semiconductor in the dummy cell region. Provided adjacent to the second conductive line on the surface of the substrate via an insulating film so that the interval between the two is the same as the pitch between the first conductive lines A third conductive line that does not electrically operate, a sidewall film provided on the side surface of each of the first conductive line, the second conductive line, and the third conductive line, and a contact formed by the sidewall film A contact plug layer having a size determined and electrically connected to the impurity region;

A method for manufacturing a dielectric memory according to the present invention comprises:
A method of manufacturing a dielectric memory including a memory cell region having a dielectric capacitor on a semiconductor substrate and a dummy cell region having a dielectric capacitor having a larger storage capacitance than the dielectric capacitor on the memory cell region side, comprising: Forming a plurality of conductive lines at the same pitch on a semiconductor substrate in a memory cell region and a dummy cell region through an insulating film; and forming a plurality of impurities in the semiconductor substrate in the memory cell region and the dummy cell region in correspondence with the plurality of conductive lines. Selectively forming regions, forming sidewall films on the side surfaces of the plurality of conductive lines, forming an interlayer insulating film on the semiconductor substrate after forming the sidewall films, An opening reaching the impurity region is formed in the interlayer insulating film by a self-alignment process using the side wall film of the line. And a step of forming a contact plug layer by embedding a conductive material.

In the dielectric memory according to the present invention, the second conductive line and the third conductive line in the dummy cell region are provided at the same pitch as the first conductive line in the memory cell region. In each of the memory cell region and the dummy cell region, a contact plug layer (bit contact and node contact) can be formed in a self-aligned manner.

In another dielectric memory according to the present invention, the second conductive line and the third conductive line are provided in the dummy cell region at the same pitch as the first conductive line in the memory cell region, and are provided for each conductive line. Since the sidewall film is formed, the contact plug layer (bit contact and node contact) is formed in each of the memory cell region and the dummy cell region in a self-alignment manner by using the sidewall film in the manufacturing process. Becomes possible.

In the method of manufacturing a dielectric memory according to the present invention, a plurality of conductive lines are formed at the same pitch in each of the memory cell region and the dummy cell region.
Sidewall films are formed on the side surfaces of the respective conductive lines, and a contact plug layer is formed by a self-alignment process using the sidewall films.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a circuit configuration of a dielectric memory 1 according to one embodiment of the present invention. This dielectric memory 1
Has a memory cell region 3 electrically connected to the sense amplifier 2 via two bit lines BL1 and BL2, and a reference potential generating circuit is provided between the memory cell region 3 and the sense amplifier 2. Dummy cell region 4 is provided.
The memory cell region 3 is configured by alternately arranging cells connected to the bit line BL1 and cells connected to the bit line BL2. Each cell includes one transistor 3a and one dielectric capacitor 3b. It is composed of
Each transistor 3a has its gate electrode connected to the word line WL.
1 to WLn (n is an even number), and one of the two impurity regions (source / drain) is
It is electrically connected to one of L1 and BL2. The other impurity region of each transistor 3a is electrically connected to one electrode (lower electrode) of dielectric capacitor 3b, and the other electrode (upper electrode) of dielectric capacitor 3b is electrically connected to plate lines PL1 to PLn, respectively. Connected. Note that the word lines WL1 to WLn correspond to the first conductive lines of the present invention.

Each cell of the dummy cell area 4 (here, 2
Similarly, each of them includes one transistor (dummy transistor) 4a and one dielectric capacitor (dummy capacitor) 4b. Dielectric capacitor 4
Since b has a larger number of uses than the dielectric capacitor 3b on the memory cell region 3 side, as shown in a sectional configuration described later, the storage capacity of b is larger than that of the dielectric capacitor 3b, that is, the area is larger ( For example, three times the dielectric capacitor 3b). In each transistor 4a, its gate electrode forms a part of dummy word lines DWL1 and DWL2, and one of two impurity regions (source / drain) is electrically connected to one of bit lines BL1 and BL2. ing. The other impurity region of each transistor 4a is connected to one electrode (lower electrode) of the dielectric capacitor 4b.
, And the other electrode (upper electrode) of the dielectric capacitor 4b is connected to the dummy plate lines DPL1 and DPL2.
Are electrically connected to each other. Note that the dummy word lines DWL1 and DWL2 correspond to the second conductive lines of the present invention.

In the dielectric memory 1, in the memory cell region 3, odd-numbered word lines WL
1, WL3 to WLn-1 are selected, the transistor 3a in the cell on the left side in the figure is turned on, and the potential stored in the dielectric capacitor 3b is changed to one bit line BL1.
Is sent to the sense amplifier 2 via the amplifier and amplified. At this time, in dummy cell region 4, one dummy word line DWL2 is selected, transistor 4a on the right side in the figure is turned on, and the potential stored in large-capacity dielectric capacitor 4b is set as a reference potential via bit line BL2. And sent to the sense amplifier 2. Based on this reference potential, determination of “1” or “0” of the potential generated in the memory cell region 3 is performed.

Similarly, even-numbered word lines WL2, WL
When 4 to WLn are selected, the transistor 3a in the right cell in the figure is turned on, and the dielectric capacitor 3b is turned on.
Is sent to the sense amplifier 2 via the other bit line BL2. In the dummy cell region 4, the other dummy word line DWL2 is selected, the transistor 4a on the left side in the figure is turned on, and the potential stored in the dielectric capacitor 4b is used as a reference potential for the bit line BWL.
The signal is sent to the sense amplifier 2 via L2, and the same determination as above is performed.

FIG. 2 shows a memory cell area 3 of the dielectric memory 1.
3 shows a pattern configuration of a word line and a bit line of the dummy cell region 4. In the memory cell region 3, each pattern of the word lines WL1 to WLn is formed at the same interval as the pitch (F) between the bit lines BL1 and BL2. On the other hand, in the dummy cell region 4, the distance between the dummy word line WL1 and the dummy word line WL2 is 3
It is F. This is because the area of the dielectric capacitor 4b is set to be larger than that of the dielectric capacitor 3b as described above.

In the memory cell region 3, the word lines WL1 to WL1
Since WLn are arranged at the same pitch, word line WL1
By forming a sidewall film on each side surface of WLn, the bit contact 5 and the node contact 6 can be formed by a self-alignment process. On the other hand, in the dummy cell region 4, the pitch between the dummy word line WL1 and the dummy word line WL2 is different from that in the memory cell region 3, and in this state, as described above, Unable to apply alignment process.

Therefore, in the present embodiment, the mechanical word lines MWL1 and MW for self-alignment are
By adding L2, the pitch between the patterns is set to the same size as that of the memory cell region 3, and the self-alignment process can be applied to the dummy cell region 4. These mechanical word lines MWL1, MW
Unlike other word lines, L2 is meaningful in the process of forming the bit contact and node contact regions, and does not operate electrically. Note that these mechanical word lines MWL1, MWL
WL2 corresponds to the third conductive line of the present invention.

FIG. 3 shows a specific configuration of the dielectric memory 1. This drawing shows a cross-sectional configuration in the direction of arrow AA in the pattern configuration diagram of FIG. In this dielectric memory 1, an impurity region 13 having an LDD (Lightly Doped Drain) structure serving as a source / drain is provided in a region surrounded by a field insulating film 12 in a substrate such as a silicon substrate 11.
A, 13B and 13C are formed respectively. A word line (also serving as a gate electrode) is formed on the silicon substrate 11 between these impurity regions 13A to 13C via a gate insulating film 14.
15A and a dummy word line 15B are formed respectively. The word line 15A corresponds to the word line WLn shown in FIGS. 1 and 2, and the dummy word line 15B corresponds to the dummy word line DWL1 shown in FIGS. Cell transistor 3a and impurity region 1 shown in FIG. 1 are formed by impurity regions 13A and 13B and word line 15A.
The dummy transistors 4a shown in FIG. 1 are respectively constituted by 3B, 13C and the dummy word line 15B.

Also on the field insulating film 12, the word line 15C on the memory cell region 3 side, the mechanical word line 15D and the dummy word line 1 on the dummy cell region 4 side.
5E and a mechanical word line 15F are formed respectively. The word line 15C is the word line WLn-1 shown in FIGS. 1 and 2, the mechanical word line 15D is the mechanical word line MWL1, the dummy word line 1 shown in FIG.
5E is the dummy word line DWL shown in FIGS.
2. The mechanical word line 15F corresponds to the mechanical word line MWL2 shown in FIG. The word lines 15A and 15C and the dummy word lines 15B and 15E
Each of the mechanical word lines 15D and 15F is formed of a so-called polycide film having a structure in which a silicide film (for example, WSi ₂ ) is laminated on a low-resistance polycrystalline silicon film, for example.
An offset insulating film 16 made of iO ₂ (silicon dioxide) is formed, and each line width is, for example, 0.25.
μm.

The word lines 15A, 15C, the dummy word lines 15B, 15E, and the mechanical word lines 15D, 15
On each side surface of F, a self-aligning sidewall film 17 made of, for example, SiO ₂ is formed. Each sidewall film 17 and offset insulating film 1
The periphery of 6 is covered with an insulating protective film 18 made of, for example, SiN (silicon nitride).

A contact plug layer 19 (the bit contact shown in FIG. 2) electrically connected to the impurity layer 13B through an opening provided in the insulating protection film 18 between the word line 15A and the dummy word line 15B. 5). The contact plug layer 19 is formed of, for example, low-resistance polycrystalline silicon.
(Boro-Phospho-Silicate Glass) and the like. The contact plug layer 19 is electrically connected to the bit line 21 via the connection 19A. The bit line 21 is, for example, W
(Word line 1)
It is arranged in a direction crossing 5A or the like. This bit line 21 corresponds to bit line BL1 shown in FIGS. On the bit line 21, an interlayer insulating film 20B made of, for example, BPSG is formed.

Between the word line 15C and the word line 15A,
And the dummy word line 15B and the mechanical word line 15
The contact plug layers 22 and 23 (corresponding to the node contacts 6 in FIG. 2) electrically connected to the impurity layers 13A and 13C through openings formed in the insulating protection film 18 are provided between the contact plug layers D and D. Have been.

The surfaces of the contact plug layers 22 and 23 and the interlayer insulating film 20B are flattened. For example, dielectric capacitors 3b and 4b having a trench structure are provided in the interlayer insulating film 24 formed on the flat surface. Have been.

Dielectric capacitor 3 on memory cell region 3 side
“b” is composed of, for example, a lower electrode 31, a dielectric film 32 and an upper electrode 33 stacked in the groove 25 having a rectangular cross section. The dielectric capacitor 4b on the dummy cell 4 side
Similarly, the lower electrode 41, the dielectric film 42, and the upper electrode 43 are stacked in the groove 26 having a rectangular cross section, for example. Although the depths of the grooves 25 and 26 are the same, the area thereof is large in the groove 26, and the dielectric capacitor 4b has a large capacity as described above. The lower electrodes 31 and 41 and the upper electrodes 33 and 43 are, for example, Pt (platinum),
It is made of a metal material such as Ir (iridium), Ru (ruthenium), Rh (rhodium) and Pd (palladium). The dielectric films 32 and 42 are formed of a ferroelectric material or a high dielectric material. SBT (Bi ₂ SrTa ₂ O ₉ ), SBNT as a ferroelectric material
(Bi _2-X SrNb _X O ₉ ), PZT (Pb (Zr, T
a)), PLZT ((Pb, La) (Zr, Ti)
O ₃ ) and the like, and Ta ₂ O ₅ , B
ST ((Ba, Sr) TiO ₃ ), STO (SrTiO
₃ ) and the like.

The upper end of the contact plug layer 22 is electrically connected to the lower electrode 31 of the dielectric capacitor 3b. The upper end of the contact plug layer 23 is electrically connected to the lower electrode 41 of the dielectric capacitor 4b.

The surface of the interlayer insulating film 24 is flattened together with the surfaces of the dielectric capacitors 3b and 4b. In the dielectric capacitor 3b, both ends of the lower electrode 31 and the dielectric film 32 are along with the upper surface of the upper electrode 33. In the dielectric capacitor 4b, both ends of the lower electrode 41 and the dielectric film 42 are in the upper surface of the upper electrode 43. , Respectively, and are exposed on a flat surface.

On the dielectric capacitors 3b and 4b, wiring layers 28 and 2 made of, for example, Al (aluminum) are formed via an insulating film 27 made of, for example, BPSG.
9 are provided. The wiring layer 28 is electrically connected to the upper electrode 33 of the dielectric capacitor 3b via a connection hole 27a provided in the insulating film 27. This wiring layer 28 corresponds to plate line PLn shown in FIG. Similarly, the wiring layer 29 has a connection hole 27 b provided in the insulating film 27.
Is electrically connected to the upper electrode 43 of the dielectric capacitor 4b via the. This wiring layer 29 corresponds to dummy plate line DPL1 shown in FIG.

In this dielectric memory 1, the transistor 3
When a predetermined voltage is applied to the gate electrode a (word line 15A), the transistor 3a is turned on, and the source-drain (between the impurity regions 13A and 13B) becomes conductive. As a result, a voltage is applied between the upper electrode 33 and the lower electrode 31 of the dielectric capacitor 3a via the contact plug layer 33, and as a result, polarization occurs in the ferroelectric film 32. Since this voltage-polarization characteristic has hysteresis, writing or reading of "1" or "0" data is performed using this hysteresis. On the other hand, in the dummy cell region 4, when the transistor 4a is turned on, the storage potential of the dielectric capacitor 4b is generated as a reference potential.

In the dielectric memory 1 of the present embodiment, mechanically inactive mechanical word lines MWL1 (word lines 15D) and MWL2 (word lines 15F) are provided in the dummy cell region 4, and the pitch between each word line is provided. Is set to the same size as the pitch between the word lines in the memory cell region 3, so that the self-alignment process is performed in the dummy cell region 4 in the same manner as in the memory cell region 3 as specifically described in a manufacturing process described later. Can be applied.

Next, a specific method of manufacturing the dielectric memory 1 will be described with reference to FIGS. 4A to 4C to 10 and FIGS. 1 to 3.

First, as shown in FIG. 4A, a field insulating film 12 for element isolation is formed on a p-type silicon substrate 11 in the same manner as in a known DRAM process. A channel stopper region and the like are formed by ion implantation. Subsequently, a gate insulating film (SiO ₂ ) 14 is formed on the surface of the silicon substrate 11 by thermal oxidation. Next, a polycide film composed of a low-resistance polycrystalline silicon film and a silicide film (for example, WSi ₂ ) is formed on the gate insulating film 14 and the field insulating film 12, and then, for example, SiO ₂ (silicon dioxide) is formed on the polycide film. ) Is continuously formed. Next, for example, RIE (Reactive Ion E
tching: reactive ion etching), and the word lines 15A and 15C, the dummy word lines 15B and 15E, and the mechanical word line 15 are formed at the same pitch.
D and 15F are respectively formed. Then, the word line 15
An n-type impurity such as P (phosphorus) is introduced into the silicon substrate 11 by ion implantation using the offset insulating films 16 on the dummy word lines A and 15C, the dummy word lines 15B and 15E, and the mechanical word lines 15D and 15F as a mask. LDD
A region 13 is formed.

Next, as shown in FIG. 4B, for example, CVD (Chemical Vapor Deposition).
Word lines 15A and 15C and dummy word lines 15
After forming an insulating film made of, for example, SiO _{2 on} the entire surface of the silicon substrate 11 including the B, 15E and the mechanical word lines 15D, 15F, the word lines 15A, 1 are etched (etched back) by, eg, RIE.
5C, a side wall film 17 for self-alignment is formed on each side surface of the dummy word lines 15B and 15E and the mechanical word lines 15D and 15F. Subsequently, an n-type impurity, for example, P (phosphorus) is introduced into the silicon substrate 11 by an ion implantation method using the offset insulating film 16 and the side wall film 17 as a mask, and an impurity region (source / drain) 13A deeper than the LDD region 13 is formed. To 13C.

Next, as shown in FIG. 4C, the surface of the silicon substrate 11 is coated with Si ₃ N by, eg, CVD.
_{4 An} insulating protective film 18 made of (silicon nitride) is formed,
An opening 18a of a bit contact pattern is formed in the insulating protective film 18 by photolithography.

Next, as shown in FIG. 5A, a region corresponding to the opening 18a of the gate insulating film 14 is selectively removed by, for example, wet etching using diluted hydrofluoric acid.
The impurity region 13B is exposed.

Next, as shown in FIG. 5B, a low-resistance polycrystalline silicon film containing impurities, for example, phosphorus (P) is formed on the surface of the silicon substrate 11 by, for example, a CVD method, and then patterned. A contact plug layer (bit contact) 19 reaching the impurity region 13B is formed. At this time, since the sidewall film 17 is formed between the word line 15A and the dummy word line 15B, the contact plug layer 19 having a width smaller than the pitch between the word line 15A and the dummy word line 15B is formed by itself. Formed consistently.

Next, as shown in FIG. 5C, after an interlayer insulating film 20A made of BPSG is formed on the surface of the silicon substrate 11 by, for example, a CVD method, reflow or CMP (Chemical and Mechanical) is performed. Polishin
g: Chemical mechanical polishing) to smooth or flatten the surface. Subsequently, after a connection hole is formed in the interlayer insulating film 20A, W (tungsten) is deposited by, for example, a sputtering method to form the bit line 21 and to form a connection portion 19A to form the bit line 21 and the contact plug layer 19. Is electrically connected. Then, as shown in FIG. 10, contact plug layers (node contacts) 22, 23 are formed on the side surfaces of the bit lines 21 as described later.
For self-aligned of (a direction perpendicular to the paper surface in FIG. 5) the longitudinal direction of the word line in forming, for example, Si ₃ N
_{From 4} , a sidewall film 30 is formed. Note that FIG.
Corresponds to the cross section in the direction of arrow BB in FIG.

Next, as shown in FIG. 6A, after an interlayer insulating film 20B made of BPSG is formed on the surface of the silicon substrate 11 by, for example, a CVD method, the surface is reflowed or CMP-processed. Smoothing or flattening. Subsequently, the interlayer insulating films 20B and 20B are formed by RIE under the condition that the selectivity of the insulating protective film (Si ₃ N ₄ ) 18 is large.
Openings (contact holes) 22a and 23a are provided in 0A.

Here, in the step of FIG. 5C, the side wall film 30 (FIG. 10) is formed on the bit line 21. Therefore, regardless of the displacement of the resist pattern for node contact, the bit lines 21 in the openings 22a and 23a
The size W ₁ (node contact size) (see FIG. 9) in the longitudinal direction of the word line (that is, in the longitudinal direction of the word line (in FIG. 6A, the direction perpendicular to the paper surface)) is determined in a self-aligned manner. On the other hand, since the sidewall films 17 are also formed between the word lines 15A and 15C and between the dummy word lines 15B and the mechanical word lines 15D, the openings 22 are formed.
The size W ₂ (node contact size) between the word lines a and 23a (see FIG. 6A) is also determined in a self-aligned manner. The insulating film protection film 18 on the side wall film 17 also serves as an end point (end point) when the openings 22a and 23a are formed in the interlayer insulating films 20B and 20A by RIE. That is, when the insulating protection film 18 is exposed, the RIE of the interlayer insulating film 20A is stopped.
As shown in (B), the insulating protective film 18 exposed by dry etching such as RIE is selectively removed. Further, the gate insulating film 14 is selectively removed by wet etching using diluted hydrofluoric acid (HF) to remove the impurity region 13.
A, Expose the surface of 13C. Then, for example, CVD
After depositing low-resistance polycrystalline silicon containing impurities such as phosphorus (P) on the surface of the silicon substrate 11 by the method
The surface is flattened by, for example, CMP to form contact plug layers (node contacts) 22 and 23.

Next, as shown in FIG.
0B and the contact plug layers 22 and 23
After forming an interlayer insulating film 24 made of PSG, a photoresist film (not shown) having a pattern of a cell capacitor and a dummy capacitor is formed, and grooves 25 and 26 are formed by RIE using the photoresist film as a mask. . If the coverage of the lower electrodes 31, 41, the dielectric films 32, 42 and the upper electrodes 33, 43 formed in a later process is not good, the edges of the grooves 25, 26 are smoothed. It is preferable to perform reflow by heat treatment.

Next, as shown in FIG.
The lower electrode layer 34 made of, for example, platinum (Pt) having a thickness of 100 nm, for example, a 100 nm-thick dielectric film layer 35 made of SBT and, for example, platinum (Pt) are formed on the interlayer insulating film 24 containing Film thickness 0.5μ
m lower electrode layers 36 are continuously formed. At this time, if the coefficient of thermal expansion between the interlayer insulating film 24 and the lower electrode layer 34 is greatly different, and if the film is easily separated, Ta (tantalum) is used.
It is desirable to provide a buffer layer such as or its oxide.

Next, as shown in FIG.
The lower electrode layer 3 was formed by a CMP method using 4 as an end point detection layer.
4, the groove 25 of the dielectric film layer 35 and the upper electrode layer 36,
The portions other than 26 are selectively removed, and the silicon substrate 11 is removed.
The surface of is flattened. Thereby, in the groove 25,
A dielectric capacitor 3b composed of a lower electrode 31, a dielectric film 32 and an upper electrode 33 is formed, and a dielectric capacitor 4b composed of a lower electrode 41, a dielectric film 42 and an upper electrode 43 is formed in the groove 26.

Next, as shown in FIG. 3 described above, a 0.3 μm-thick interlayer insulating film 27 made of PSG is formed on the dielectric capacitors 3 b and 4 b and the interlayer insulating film 24 by, eg, CVD. . Subsequently, the interlayer insulating film 27
After forming the connection holes 27a and 27b in the interlayer insulating film 2
Wiring layers 28 and 29 are formed by depositing, for example, Al (aluminum) on the layer 7 and selectively etching it. The connection holes 23a and 23b may be filled with W (tungsten) or the like as necessary. Thereafter, the dielectric memory 1 according to the present embodiment goes through a normal metal wiring process.
Is completed.

As described above, in the method of manufacturing the dielectric memory 1 according to the present embodiment, the mechanical word lines 15D and 15F for self-alignment are provided in the dummy cell region 4, and the pitch of each pattern is made the same as that of the memory cell region 3. The size is set and the side wall film 17 is provided on the side surface of each word line including the mechanical word lines 15D and 15F, and the side wall film 30 is provided on the side surface of the bit line 21. Can also apply a self-aligned process. Therefore, fine node contacts and bit contacts can be formed with high accuracy, the degree of integration is improved, and the manufacturing process is simplified.

In the present embodiment, the interlayer insulating film 24
By appropriately adjusting the size of the groove 26 on the side of the dummy cell 4 to be formed, the size of the groove 26 can be made larger than that of the groove 25 on the side of the memory cell region 3. A simple dummy capacitor can be easily manufactured.

As described above, the present invention has been described with reference to the embodiments. However, the present invention is not limited to the above embodiments and can be variously modified. For example, in the above-described embodiment, the dielectric capacitor 3a, 4a having a trench (groove structure) structure has been described. However, the present invention is applicable to a dielectric capacitor having another structure, for example, a stacked (stacked) structure. can do.

[0050]

As described above, the dielectric memory according to any one of claims 1 to 6, or the seventh aspect of the present invention.
According to the method of manufacturing a dielectric memory according to any one of claims 9 to 9, a plurality of conductive lines are formed at the same pitch over the memory cell region and the dummy cell region, including the conductive lines that do not electrically operate. Since it is provided, the self-alignment process can be applied when forming the contact plug layer even in the dummy cell region having a large capacitance of the capacitor, so that the integration degree is improved and the manufacturing process can be simplified. This has the effect.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a dielectric memory according to an embodiment of the present invention.

FIG. 2 is a pattern configuration diagram of a capacitor portion of the dielectric memory shown in FIG.

FIG. 3 is a sectional view illustrating a configuration of the dielectric memory illustrated in FIG.

FIG. 4 is a cross-sectional view for each step illustrating a method for manufacturing the dielectric memory shown in FIG.

FIG. 5 is a cross-sectional view of each step following the step of FIG. 4;

FIG. 6 is a sectional view of each step following the step of FIG. 5;

FIG. 7 is a sectional view of each step following the step of FIG. 6;

8 is a cross-sectional view of each step following the step of FIG. 7;

FIG. 9 is a sectional view of each step following the step of FIG. 8;

FIG. 10 is a sectional view taken in the direction of arrows BB in FIG. 2;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Dielectric memory, 2 ... Sense amplifier, 3 ... Memory cell area, 3a ... Transistor (cell transistor), 3b
... dielectric capacitor (cell capacitor), 4 ... dummy cell area, 4a ... transistor (dummy transistor),
4b: dielectric capacitor (dummy capacitor), 5: bit contact, 6: node contact, 11: silicon substrate, 12: field insulating film, 13A to 13C: impurity region (source / drain), 14: gate insulating film,
15A, 15C: word line, 15B, 15E: dummy word line, 15D, 15F: mechanical word line, 16:
Offset insulating film, 17: sidewall film, 18: insulating protective film, 19: contact plug layer (bit contact), 20A, 20B: interlayer insulating film, 21: bit line,
22, 23 contact plug layer (node contact), 25, 26 groove, 27 interlayer insulating film, 28, 2
9: wiring layer, 31, 41: upper electrode, 32, 42: dielectric film, 33, 43: upper electrode

Claims (9)

[Claims] 1. A memory cell region having a dielectric capacitor, and a dummy cell region provided in parallel with the memory cell region and having a dielectric capacitor having a larger storage capacitance than the dielectric capacitor on the memory cell region side. And a plurality of first memories provided at a predetermined pitch in a memory cell region.
And a plurality of second conductive lines provided at a different pitch from the first conductive line in the dummy cell region, and a mutual interval in the dummy cell region is equal to a pitch between the first conductive lines. And a third electrically inactive line provided adjacent to the second electrically conductive line as described above. 2. A dielectric memory comprising, on a semiconductor substrate, a memory cell region having a dielectric capacitor and a dummy cell region having a dielectric capacitor having a larger storage capacitance than the dielectric capacitor on the memory cell region side, A plurality of impurity regions selectively provided in the semiconductor substrate in the memory cell region and the dummy cell region; and a plurality of first conductive regions provided at a predetermined pitch on the surface of the semiconductor substrate in the memory cell region via an insulating film. A plurality of second conductive lines provided at a different pitch from the first conductive lines on the surface of the semiconductor substrate in the dummy cell region via an insulating film; and a plurality of second conductive lines on the surface of the semiconductor substrate in the dummy cell region via the insulating film. Electrically actuated provided adjacent to the second conductive line such that the distance between the conductive lines is equal to the pitch between the first conductive lines. A third conductive line, a sidewall film provided on a side surface of each of the first conductive line, the second conductive line, and the third conductive line; and a contact size is determined by the sidewall film. A dielectric memory, comprising: a contact plug layer electrically connected to the impurity region. 3. The semiconductor device according to claim 1, wherein each of the first conductive line, the second conductive line, and the third conductive line is a word line having a laminated structure of a low-resistance polycrystalline silicon film and an offset insulating film. 3. The dielectric memory according to claim 2, wherein 4. In a direction crossing the word line,
A bit line having a sidewall film formed on a side surface is provided, and the contact plug layer constitutes a bit contact electrically connected to the bit line in each of a memory cell region and a dummy cell region. 4. The dielectric memory according to claim 3, wherein 5. The dielectric according to claim 3, wherein each of the dielectric capacitors in the memory cell region and the dummy cell region is buried in a groove provided in an interlayer insulating film on the contact plug layer. Body memory. 6. The dielectric according to claim 5, wherein the contact plug layer forms a node contact electrically connected to one electrode of each dielectric capacitor in the memory cell region and the dummy cell region. memory. 7. A method of manufacturing a dielectric memory including a memory cell region having a dielectric capacitor and a dummy cell region having a dielectric capacitor having a larger storage capacity than the dielectric capacitor on the memory cell region side on a semiconductor substrate. Forming a plurality of conductive lines at the same pitch on a semiconductor substrate in the memory cell region and the dummy cell region via an insulating film; and forming a plurality of conductive lines in the semiconductor substrate in the memory cell region and the dummy cell region between the plurality of conductive lines. A step of selectively forming a plurality of impurity regions correspondingly; a step of forming a sidewall film on each of the side surfaces of the plurality of conductive lines; and forming an interlayer insulating film on the semiconductor substrate after forming the sidewall film. Forming a film, and the interlayer insulating film by a self-alignment process using a sidewall film of each conductive line. Said reach the impurity region to form an opening, a manufacturing method of the ferroelectric memory characterized by comprising a step of forming a contact plug layer by burying a conductive material in the opening. 8. A word line in which the plurality of conductive lines are formed by a laminated structure of a low-resistance polycrystalline silicon film and an offset insulating film, and a bit contact is formed by using a sidewall film formed on the word line. 8. The method according to claim 7, wherein a contact plug layer is formed as a node contact. 9. In a direction crossing the word line,
9. The dielectric memory according to claim 8, wherein a bit line having a sidewall film formed on a side surface is formed, and a contact plug layer as a bit contact is formed using the sidewall film of the bit line. Manufacturing method.