JP2011171420A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To definitely prevent a short circuit of source extraction electrodes and gate extraction electrodes, to reduce the size the DMOS transistor, and to prevent an inter source-drain breakdown voltage VDS from being deteriorated in a trench power DMOS transistor. <P>SOLUTION: A P+type contact layer 14 formed in a P type base layer 9 directly under the bottom face of a N+type source layer 13 is exposed to a recess 16 that penetrates the N+type source layer 13 that is exposed to at least a part of the bottom face of the contact opening 25 in the contact opening 25. Then, the N+type source layer 13 that is exposed to the bottom face of the contact opening 25 and the N+type source layer 13 that is exposed to the recess section 16, and a source extraction electrode 17a that is connected to the P+type contact layer 14 by laying the electrode under the ground inside the contact opening 25 by its upper end and is extended are formed. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device related to a trench power DMOS transistor having a trench gate structure and a method for manufacturing the same, and more particularly to a configuration of a lead electrode connected to a source layer or the like on the bottom of a trench and extending to the surface of a semiconductor substrate. The present invention relates to the structure of the source layer on the bottom surface and the manufacturing method thereof.

  Power MOS transistors are widely used in switching power supplies such as DC-DC converters and motor inverter circuits because they have superior switching characteristics and are stable and easy to use compared to bipolar power transistors. Since power MOS transistors have a long history of products and are easy to make, horizontal power MOS transistors in which a source region, a drain region, and a gate region are formed on the surface of a semiconductor substrate were mainly used.

  However, demands for high breakdown voltage, large current, and low saturation voltage are increasing, and a semiconductor substrate is etched to form a trench, a gate insulating film is formed on the trench sidewall, a gate electrode is formed thereon, and the gate electrode and the gate insulating film are formed. Inverting a semiconductor layer opposed to each other via a so-called channel layer, a vertical current is passed between the substrate front side and the substrate back side between the upper end of the trench and the source or drain formed on the back side of the semiconductor substrate. A trench power DMOS transistor was developed.

  In addition, with the rapid development of portable devices and the spread of communication devices, products in which power MOS transistors and control circuits are integrated on a single chip are widely spread due to the demand for miniaturization and weight reduction. When the control circuit and the power MOS transistor are made into one chip, the lateral power MOS transistor is formed on the same chip as the conventional small MOS transistor because the source layer, drain layer and gate electrode are formed on the surface of the semiconductor substrate. It was relatively easy.

  However, in the case of a trench power DMOS transistor in which a trench is formed in a semiconductor substrate and a large current flows between the front surface of the semiconductor substrate and the back surface of the semiconductor substrate, it extends from the active layer on the back surface side of the semiconductor substrate to the front surface side of the semiconductor substrate. An extraction electrode serving as a current path is required, and integration with a control circuit or the like becomes difficult as compared with a lateral power MOS. Also, the back side active layer is formed on the semiconductor layer exposed at the bottom of the trench, but when the back side active layer is the source layer, it is formed in parallel with the source layer for the reason described later, and the base layer below it. It is also necessary to form a contact layer that extends to

  FIG. 12 schematically shows a part of a plan view of a lateral N-channel power MOS transistor formed on the surface of a semiconductor substrate. A source region 59 in which an N + type source layer is formed, a gate region 60 in which a gate electrode is formed on a semiconductor layer via a gate insulating film, and several or more drain regions 61 in which an N + type drain layer is formed are formed in parallel. Is done. In the source region 59, a P + type contact region 62 made of a P + type contact layer is formed in parallel with the source region 59 and extending through the source region 59 to the P type base layer therebelow.

  12A is a plan view of the power MOS transistor when the P + contact region 62 does not exist in the source region 59, and FIG. 12B shows a P + having a predetermined size with a predetermined interval from the source region 59. FIG. FIG. 12C is a plan view of the power MOS transistor when the type contact region 62 is formed, and FIG. 12C shows the power MOS transistor when the P + type contact region 62 having a constant width is formed in the entire source region 59. The top view of is shown. Reference numerals 63, 64, and 65 denote contact openings formed in an interlayer insulating film formed thereon.

  The reason why the P + type contact layer extending in parallel to the N + type source layer to the P type base layer therebelow is formed is to make the potential of the P type base layer equal to the potential of the N + type source layer. By making the potentials of both layers the same potential, an NPN parasitic transistor having an N + type source layer as an emitter, a P type base layer as a base, and an N + type drain layer as a collector is turned on in a lateral N channel power MOS transistor. Can be prevented. The on-current of the NPN parasitic transistor becomes a leakage current of the lateral N-channel power MOS transistor and causes a reduction in the source-drain breakdown voltage VDS.

  In FIG. 13, the horizontal axis indicates the area of the P + type contact region 62 occupying the source region 59 corresponding to FIGS. 12A, 12B, and 12C as A, B, and C, and the vertical axis. 4 is a graph showing a source-drain breakdown voltage VDS of a power MOS transistor. It is shown that the value of the source-drain breakdown voltage VDS of the power MOS transistor is improved as the area of the P + type contact region 62 increases. This indicates that the effect of preventing the NPN parasitic transistor from being turned on increases as the area of the P + type contact region 62 increases.

  Regarding a single trench power DMOS transistor, a number of documents including the following Patent Document 1 are disclosed.

Japanese Patent Application Laid-Open No. 07-122745

  There are various methods for forming the extraction electrode. However, the surface area of the semiconductor substrate used for forming the extraction electrode is made as small as possible, and the extraction electrode from the source layer formed on the bottom of the trench and the gate electrode are used. The problem is to establish a configuration of the extraction electrode that does not cause a problem such as a short circuit of the extraction electrode and a manufacturing method thereof.

  The semiconductor device of the present invention is a semiconductor device having a trench in which a wide region and a narrow region are integrally formed, the gate electrode formed on the side wall of the trench via a gate insulating film, An active layer extraction electrode connected to the first semiconductor layer of the first conductivity type exposed on the bottom surface of the trench and extending to the upper end of the trench through the gate electrode and the first insulating film; A wide first trench, a gate electrode embedded in the trench through the gate insulating film, and a gate lead electrode connected to the gate electrode and extending through the trench to the upper end thereof A first trench comprising: a second trench having a wide width; a gate electrode embedded in the trench with the gate insulating film interposed therebetween; and a second insulating film embedded in the trench. And a narrow third trench connecting the second trench, wherein the gate electrode of the first trench and the gate electrode of the second trench are the gate of the third trench. The active layer lead electrode of the first trench and the gate lead electrode of the second trench are separated by the third trench.

  Further, in the semiconductor device of the present invention, in the first trench, a recess portion that penetrates the first semiconductor layer, and a portion of the surface of the recess portion is directly below the first semiconductor layer. A second semiconductor layer of the second conductivity type formed exposed, and at least a part of the active layer lead electrode exposed in the recess and the second semiconductor layer. It is connected to a semiconductor layer.

  In the semiconductor device of the present invention, in the first trench, all of the active layer lead electrodes are connected to the first semiconductor layer and the second semiconductor layer exposed in the recess. Features.

  In the semiconductor device of the present invention, a polysilicon lead electrode formed on the inner wall of the first trench with the gate electrode and an insulating film interposed between the polysilicon lead electrode and the polysilicon lead electrode in the first trench. A recess extending through the first semiconductor layer exposed at the bottom of the trench to a semiconductor layer immediately below the first semiconductor layer, and a recess directly below the first semiconductor layer. A second semiconductor layer of a second conductivity type formed by exposing a part of the surface of the first semiconductor, wherein at least a part of the active layer lead electrode is exposed in the recess. A layer is connected to the second semiconductor layer and buried between the polysilicon lead electrodes.

  The semiconductor device according to the present invention is characterized in that the semiconductor device is a trench power DMOS transistor having a trench gate structure, and the first semiconductor layer is a source layer.

  The semiconductor device according to the present invention is characterized in that the semiconductor device is a trench power DMOS transistor having a trench gate structure, and the first semiconductor layer is a source layer.

  The semiconductor device manufacturing method of the present invention is a method for manufacturing a semiconductor device having a trench in which a wide region and a narrow region are integrally formed, and a gate is formed on a side wall of the trench via a gate insulating film. Forming an electrode; and connecting to the first semiconductor layer of the first conductivity type exposed at the bottom of the trench, and extending in the trench to the upper end through the gate electrode and the first insulating film Forming a wide first trench including a step of forming an active layer lead electrode; forming a gate electrode embedded in the trench through the gate insulating film; and Forming a gate lead electrode connected to and extending to the upper end of the trench, and forming a second wide trench including the gate insulating film through the gate insulating film. Forming a gate electrode to be buried; and forming a second insulating film to be buried in the trench; and forming a third trench having a narrow width connecting the first trench and the second trench. And forming the active region of the first trench by connecting the gate electrode of the first trench and the gate electrode of the second trench by the gate electrode of the third trench. The layer lead electrode and the gate lead electrode of the second trench are divided by the third trench.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the step of forming a recess portion that penetrates the first semiconductor layer in the first trench, and the recess portion immediately below the first semiconductor layer. Forming a second semiconductor layer of a second conductivity type in which a part of the surface is exposed, wherein at least a part of the active layer lead electrode is exposed in the recess. The semiconductor device is connected to the semiconductor layer and the second semiconductor layer.

  In the semiconductor device manufacturing method according to the present invention, in the first trench, all of the active layer lead electrodes are connected to the first semiconductor layer and the second semiconductor layer exposed in the recess. It is characterized by that.

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming a polysilicon lead electrode on the inner wall of the first trench through the gate electrode and an insulating film in the first trench, and the polysilicon. Forming a recess that penetrates the first semiconductor layer exposed between the extraction electrodes and extends to a semiconductor layer immediately below the first semiconductor layer; and immediately below the first semiconductor layer, Forming a second semiconductor layer of a second conductivity type in which a part of the surface of the recess is exposed, wherein at least a part of the active layer lead electrode is exposed in the recess. It is connected to one semiconductor layer and the second semiconductor layer, and is buried between the polysilicon lead electrodes.

  According to the semiconductor device and the manufacturing method thereof of the present invention, it is possible to reliably prevent a short circuit between the extraction electrode from the N + type source layer and the extraction electrode from the gate electrode. Further, since there is no P + type contact layer in parallel with the N + type source layer on the surface of the P type base layer, the width of the N + type source layer can be reduced. Therefore, the size of the trench power DMOS transistor can be reduced.

It is a top view which shows the semiconductor device in the 1st, 2nd and 3rd embodiment of this invention. It is sectional drawing which shows formation regions, such as a source extraction electrode of the semiconductor device in the 1st Embodiment of this invention. It is sectional drawing which shows the formation area of a gate extraction electrode etc. of a semiconductor device and the narrow trench formation area in the 1st and 2nd embodiment of the present invention. It is sectional drawing which shows the formation area of a source extraction electrode etc. and the formation area of a gate extraction electrode, etc. in the case of using a two-layer metal wiring in the first and second embodiments of the present invention. FIG. 3 is a cross-sectional view showing the method for manufacturing the semiconductor device in the first embodiment of the present invention. FIG. 3 is a cross-sectional view showing the method for manufacturing the semiconductor device in the first embodiment of the present invention. FIG. 3 is a cross-sectional view showing the method for manufacturing the semiconductor device in the first embodiment of the present invention. FIG. 3 is a cross-sectional view showing the method for manufacturing the semiconductor device in the first embodiment of the present invention. FIG. 3 is a cross-sectional view showing the method for manufacturing the semiconductor device in the first embodiment of the present invention. It is sectional drawing which shows formation regions, such as a source extraction electrode of the semiconductor device in the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device in the 2nd Embodiment of this invention. It is a top view of a horizontal type N channel power MOS transistor. It is a graph which shows the relationship between the area of the P + type contact region which occupies for the source region of a horizontal N channel power MOS transistor, and the source-drain breakdown voltage VDS.

[First Embodiment]
A first embodiment of the present invention will be described below with reference to FIGS. 1 is a plan view of a trench power DMOS transistor according to the present embodiment, FIG. 2 is a cross-sectional view taken along the line AA in FIG. 1, FIG. 3A is a cross-sectional view taken along the line BB in FIG. It is CC sectional drawing of. 4 is a cross-sectional view when a multilayer wiring structure made of aluminum (Al) or the like is employed. FIG. 4A is a cross-sectional view taken along the line AA in FIG. 1, and FIG. It is -B sectional drawing. In the present embodiment, the trench power DMOS transistor is assumed to be an N channel trench power DMOS transistor, and the N + type source layer 13 is formed on the bottom of the trench.

  As shown in FIG. 1, a narrow trench 5 is formed between wide trenches 4. In the wide trench 4 above and below the narrow trench 5 shown in the same figure, a source lead region 1 connected to the N + type source layer 13 etc. shown in FIG. . The left and right sides of the source lead region 1 are the gate region 2 in which the gate electrode 12a and the like shown in FIG. 2 are formed.

  A gate lead region 6a and a gate region 2 are formed in the wide trench 4 sandwiched between two narrow trenches 5 continuous with the upper and lower trenches 4 in which the source lead region 1 is formed. In the gate lead-out region 6a, as shown in FIG. 3A, a gate lead-out electrode 17b that is connected to the gate electrode 12b formed therebelow and extends to the upper end of the trench is formed. Further, the gate connection electrode 17c and the like shown in FIG. 3A are formed in the gate connection electrode region 6 indicated by a dotted line orthogonal to the gate lead region 6a. The gate connection electrode 17c and the like are formed of a gate electrode material or a multilayer wiring electrode material.

  As shown in FIG. 3B, the gate electrode 12 c is buried below the trench 5 in the narrow trench 5, and the insulating film 11 a is buried above the trench 5 while covering the gate electrode 12 c. Accordingly, in the trench 5, unlike the wide trench 4, there is no opening in which an electrode lead region such as the source lead region 1 and the gate lead region 6a is formed. As a result, the source lead electrode 17a formed in the source lead region 1 as shown in FIGS. 2A and 2B and the gate lead electrode shown in FIG. 3A formed in the gate lead region 6a. 17b is divided by the narrow trench 5 portion. The first feature of the present embodiment is that the source lead electrode 17a and the gate lead electrode 17b are completely divided by the narrow trench 5.

  The present embodiment will be described in detail below with reference to FIGS. 2 to 4 showing cross-sectional views of the source lead region 1 portion, the gate lead region 6a portion, and the narrow trench 5 region portion of FIG. 2 is a cross-sectional view taken along the line AA of FIG. 1 as described above, and is a cross-sectional view crossing the source extraction region 1 and the gate region 2 and reaching the drain region 3. FIG. 3 is also a cross-sectional view taken along the line BB in FIG. 1 as described above, and is a cross-sectional view including the gate lead-out region 6a and the gate connection electrode region 6 crossing the gate region 2.

  The difference between FIG. 2A and FIG. 2B is that in FIG. 2A, a contact opening 25 is formed in a recess 16 formed by etching the N + type source layer 13 and the P + type contact layer 14. In contrast to reaching the exposed P + -type contact layer 14, in FIG. 2B, the contact opening 25 reaches only the surface of the N + -type source layer 13 exposed therein.

  In the case of a lateral N-channel power MOS transistor formed on the semiconductor surface, the P + type contact region 62 shown in FIGS. 12B and 12C is in parallel with the source region 59 on the surface of the semiconductor layer and the source region. It extends through 59 and extends into the underlying semiconductor layer. As described above, the effect of preventing the NPN parasitic transistor from turning on increases as the area of the P + type contact region 62 occupying the source region 59 increases.

  Therefore, when forming a plurality of isolated P + type contact regions 62 as shown in FIG. 12B, the P type contact regions 62 are formed larger than the contact hole openings 64 in order to make the area as large as possible. In this case, only the P + type contact region 62 is exposed in the contact opening 64, and a source electrode (not shown) formed on the contact opening 64 is unlikely to be a flow path for an electron current as a current carrier. A source electrode on a contact opening 64 (not shown) directly formed in the source region 59 serves as an electron current flow path.

  Further, when the area of the P + type contact region 62 is further increased, the P + type contact region 62 is formed in the entire region of the source region 59 as shown in FIG. In this case, in order to connect the source electrode serving as the flow path of the electron current to the source region 59, the contact opening 65 must be larger than the width of the P + type contact region 62 in order to expose the source region 59 as shown in FIG. Don't be.

  In the case of FIG. 12B, if the P + type contact region 62 is excessively increased, the flow path of the electron current is narrowed by the area, and the resistance to the electron current is increased. In the case of FIG. 12C, the source region 59 must be exposed in the contact opening 65 in order to secure the flow path of the electron current as described above, and the lateral width of the P + type contact region 62 is increased. Limited. The width and size of the P + type contact region 62 are determined in consideration of securing a flow path for the electron current.

The characteristic of this embodiment with respect to it is demonstrated in detail below based on FIG. 2 (A).
In the figure, an N + type drain layer 18 and an N − type drain layer 18 a are formed on the surface of the P type semiconductor substrate 7, and an N − type drain layer 18 a is formed from the N + type drain layer 18 on the surface of the P type semiconductor substrate 7. A trench 4 extending to the inside of the P-type semiconductor substrate 7 is formed. A P-type base layer 9 is formed on the P-type semiconductor substrate 7 extending from the bottom surface of the trench 4 to the side surface of the trench 4. A P + type contact layer 14 whose surface is exposed to the recess 16 is formed immediately below the N + type source layer 13.

  A gate electrode 12a is formed on the side wall in the trench 4 across the N + type source layer 13 and the N− type drain layer 18a via the gate insulating film 10. A portion of the P-type base layer 9 and the P-type semiconductor substrate 7 sandwiched between the N + type source layer 13 adjacent to the bottom surface of the trench 4 and the N− type drain layer 18a adjacent to the outer wall of the trench 4 are connected to the gate electrode 12a. When a voltage is applied, the channel portion is reversed to the N-type layer and becomes a flow path for electron current.

  Inside the trench 4 is a gate electrode 12a through a gate insulating film 10 and a first spacer 11 made of an insulating film, and inside the first spacer 11 is a second spacer 15 made of an insulating film. 4 is formed on the side wall. The side wall of the spacer 15 serves as an end face of the contact opening 25, and a recess 16 extending through the N + type source layer 13 to the inside of the P + type contact layer 14 is formed in the extension line of the contact opening 25.

  In the contact opening 25, the source is connected to the surface of the P + type contact layer 13 exposed at the recess 16, buried in the divided left and right N + type source layers 13, and extended to the upper end of the contact opening 25. A lead electrode 17a is formed. As shown in FIG. 2A, the source lead electrode 17a needs to be connected to both the N + type source layer 13 and the P + type contact layer 14, and therefore, instead of the commonly used N + type doped polysilicon. A metal material such as tungsten (W) is formed through a barrier metal such as titanium nitride (TiN). A drain electrode 20 connected to the N + type drain layer 18 and a source electrode 21 connected to the source lead electrode 17a are formed through a contact opening 32 formed in the interlayer insulating film 19 covering the entire surface of the P type semiconductor substrate 7. The

  The second feature of the present embodiment is that an N + type source layer 13 is formed in the entire region of the source region 1 in FIG. 1 as shown in FIG. The point where the P + type contact layer 14 is formed, and the N + type source layer 13 exposed in the depression 16 in the depression 16 formed by dividing the N + type source layer 13 up to the inside of the P + type contact layer 14 and The source lead electrode 17a is buried so as to be connected to both of the P + type contact layers.

  Unlike the case of the lateral power MOS transistor shown in FIGS. 12B and 12C, the P + type contact layer 14 is not formed in parallel with the N + type source layer 13 on the surface of the P type base layer 9. The surface of the base layer 9 is not occupied because the P + type contact layer 14 is formed. Accordingly, the source region 1 in FIG. 1 can be made narrower, and the size of the N-channel trench power DMOS transistor can be reduced.

  As described above, the source lead electrode 17a is connected to the N + type source layer 13 and the P + type contact layer 14 exposed in the recessed portion 16, is buried in the contact opening 25, and its upper end is deposited on its upper surface. The source electrode 21 is connected through a contact opening 32 such as the interlayer insulating film 19. That is, the P + type contact layer 14 and the source electrode 21 are connected via the source lead electrode 17a, and a source potential is applied to the P + type contact layer 14. Accordingly, the potential of the N + type source layer 14 and the potential of the P type base layer 9 connected to the P + type contact layer 14 can be made the same potential.

  Further, in the example of the lateral N-channel power MOS transistor, by increasing the occupied area of the P + type contact region 62 in the source region 59, the ON current of the NPN parasitic transistor is decreased, and the breakdown voltage VDS between the source and drain is decreased. This can be prevented as described above with reference to FIG. However, for the various reasons described above, in the conventional lateral N-channel power MOS transistor, the expansion of the area of the P + type contact region 62 formed in parallel with the source region 59 is limited.

  In contrast, in this embodiment, the P + type contact layer 14 is formed directly under the N + type source layer 13 with the same width as the N + type source layer 13 over the entire length of the N + type source layer 13. The area of the P + type contact layer 14 is realized. Therefore, the source-drain breakdown voltage VDS of the N-channel trench power DMOS transistor can be brought close to the original value without the on-state current of the NPN parasitic transistor.

  Further, the source lead electrode 17a is embedded in the space between the N + type source layer 13 divided to the left and right with a conductive material constituting the source lead electrode 17a. It functions in the same way as the single N + type source layer 13 by being integrated with the conductive material embedded in the. Therefore, as shown in FIG. 2B, compared with the case where the source lead electrode 17a is directly connected to the N + type source layer 13, the resistance component with respect to the electron current which is the current carrier of the N channel trench power DMOS transistor is approximately the same. It is.

  That is, the source extraction electrode 17a in FIG. 2A exhibits the effect of the large contact opening 65 or more shown in FIG. 12C showing the conventional example, despite the small contact opening 25. From this point, the width of the source lead region 1 in FIG. 1 can be reduced, and the size of the N-channel trench power DMOS transistor can be reduced.

  Further, the contact opening 25 formed in the source lead region 1 of FIG. 1 is formed as far as the P + type contact layer 14 by the recess 16 as shown in FIG. 2A, and FIG. As described above, two layers may be formed at a predetermined interval from those formed up to the surface of the N + type source layer 13. In this case, after exposing the N + type source layer 13 on the bottom surface of the contact opening 25 having the side surface of the second spacer 15 as an end surface, the contact opening 25 region where the P + type contact layer 14 is not exposed is resisted. A recess 16 that penetrates a part of the N + type source layer 13 and reaches the P + type contact layer 14 may be formed.

  In FIG. 2A, the source lead electrode 17a is connected only to the narrow N + type source layer 13 etching cross section, but in FIG. 2B, it is widely connected to the surface of the N + type source layer 13. The connection area between the source lead electrode 17a and the N + type source layer 13 can be increased even if an N + type polysilicon layer is interposed as in a modification of the second embodiment described later.

  The P + type contact layer 14 may be formed at a predetermined interval instead of being formed directly below the N + type source layer 13 in the source lead region 1 of FIG. In this case, the cross-sectional view of the portion where the P + type contact layer is formed immediately below the N + type source layer 13 is the same as FIG. 2A, but the P + type contact layer 14 is formed immediately below the N + type source layer 13. The cross-sectional shape of the part that is not formed has a configuration in which the P + type contact layer is deleted from the cross-sectional view of FIG.

  When this embodiment is compared with FIG. 12B which shows a lateral power MOS transistor in which the P + type contact region 62 is formed with a predetermined interval and a part of the source electrode is formed thereon, as described above. In addition to being able to narrow the source lead region 1, in this embodiment, the N + type source layer 13 and the P + type contact layer 14 are integrally formed, which is advantageous in that a channel for electron current is secured.

  Next, a configuration centering on the gate lead-out region 6a and the narrow trench 5 shown in FIG. 1 will be described with reference to FIG. As described above, FIG. 3A is a cross-sectional view taken along the line BB in FIG. An N − type drain layer 18 a and a P type base layer 9 are formed from the bottom surface of the trench 4 in the P type semiconductor substrate 7. The N− type drain layer 18a may not be formed. A gate electrode 12 b is buried below the trench 4 via a gate insulating film 10, and a first spacer 11 and a second spacer 15 are formed on the side wall of the trench 4 as an object.

  The gate electrode 12b is exposed on the bottom surface of the contact opening 31 where the second spacer 15 serves as an end face, and the gate lead electrode 17b connected to the exposed surface of the gate electrode 12b and extending to the upper end of the contact opening 31 is provided. It is formed. A gate connection electrode 17c extending on the insulating film 23 covering the top of the P-type semiconductor substrate 7 through the insulating film 23 continuously with the gate lead electrode 17b, and an interlayer insulating film 19 deposited thereon An external gate electrode 24 connected to the gate connection electrode 17c through the contact opening 33 is formed. The gate lead electrode 17b and the gate connection electrode 17c are formed simultaneously in the same process using tungsten of the same material as the source lead electrode 17a.

  3B is a cross-sectional view taken along the line C-C of the narrow trench 5 portion of FIG. 1 as described above. An N − type drain layer 18 a and a trench 4 are formed in the P type semiconductor substrate 7, and a P type base layer 9 is formed on the P type semiconductor substrate 7 below the bottom surface of the trench 4. The N− type drain layer 18a may not be formed. In the trench 4, a gate electrode 12 c is buried below with a gate insulating film 10, and an insulating film 11 a made of the same material as the first spacer 11 is buried at the same time when the first spacer 11 is formed on the upper side. . The uppermost surface is covered with an interlayer insulating film 19.

  Since the gate electrode 12 c and the insulating film 11 a are buried in the narrow trench 5, the source lead electrode 17 a and the gate lead electrode 17 b are not formed in the trench 5. Further, a first spacer 11 and a second spacer 15 are formed on a surface perpendicular to the trench 5 and the source region 1 shown in FIG. 1 and also on a surface orthogonal to the trench 5 and the gate lead-out region 6a. The gate electrode 12a is formed on the side wall of the trench 4 in the source lead region 1 and the gate electrode 12b formed below the trench 4 in the gate lead region 6a has a width. The connection is made through a gate electrode 12 c formed by being buried in the narrow trench 5.

  On the other hand, the trench 4 in the gate lead-out region 6a and the narrow trench 5 are insulated from the semiconductor layer such as the P-type semiconductor layer 9 by the gate insulating film 10, so that the N + type source layer 13 shown in FIG. The gate electrode 12b shown in FIG. 3 formed in the gate lead-out region 6a is separated. Further, the source lead electrode 17a connected to the N + type source layer 13 and the gate lead electrode 17b connected to the gate electrode 12a are completely divided by the narrow trench 5 region where the lead electrode is not formed because the upper surface is flat. The Therefore, by forming the narrow trench 5 between the wide trenches 4, the source lead electrode 17a and the gate electrode 21a can be reliably separated.

  FIG. 4 shows a configuration in which the external gate electrode 30, the source electrode 21, and the drain electrode 20 are separated by multilayer wiring using aluminum electrodes or the like. As shown in FIG. 4B, the gate lead electrode 17b is formed up to the upper end of the contact opening 31 similarly to the source lead electrode 17a. Thereafter, an interlayer insulating film 27 and the like are formed, a gate connection electrode 28 made of aluminum (Al) or the like is formed through the contact opening 33, an interlayer insulating film 29 is further formed thereon, and the contact opening 34 is interposed through the contact opening 34. Thus, the external gate electrode 30 is formed.

  As shown in FIG. 4A, the source lead electrode 17a and the N + type drain layer 18 are also connected to the source electrode 21 and the drain electrode 20 through the interlayer insulating film 28 formed in multiple layers and the contact opening 32 of the same 29, respectively. Is done. In the case of a semiconductor device adopting a multilayer wiring configuration, the configuration of FIG. 4B can be adopted instead of the configuration in which the gate lead electrode 17b and the gate connection electrode 17c are integrally formed as shown in FIG.

Next, a method for manufacturing the semiconductor device of this embodiment will be described below with reference to FIGS.
5A is a cross-sectional view taken along the line AA in FIG. 1, FIG. 5B is a cross-sectional view taken along the line BB, and FIG. 5C is a cross-sectional view taken along the line CC. The same display is used in FIG. First, as shown in FIG. 5A, a P-type semiconductor substrate 7 is prepared, and an N − -type drain layer 18a is formed from the surface of the P-type semiconductor layer 7 toward the inside. The impurity concentration and diffusion depth are determined by the breakdown voltage, saturation voltage, etc. of the trench power DMOS transistor. Although the N-drain layer 18a is also formed in FIGS. 5B and 5C, it may not be formed in these regions.

  Next, as shown in the figure, an etching mask is formed on the surface of the P-type semiconductor substrate 7 by an insulator 23 made of a silicon oxide film or a silicon nitride film. In the case of a silicon nitride film, a silicon oxide film is formed under the silicon nitride film as a buffer film for reducing distortion. Thereafter, trench 4 extending from N − type drain layer 18 a to P type semiconductor substrate 7 is formed by predetermined anisotropic etching using insulator 23 as a mask. The trench shown in FIG. 5C is a narrow trench 5 as described above. Note that an N + -type drain layer 18 (to be described later) shown in FIG. 2A may be formed before the mask made of the insulator 23 is formed.

  Next, boron (B) ions and the like are implanted from above the trenches 4 and 5 and heat-treated, thereby forming a P-type base layer 9 in the P-type semiconductor substrate 7 below the bottom of the trenches 4 and 5. The P-type base layer 9 has the role of adjusting the threshold value of the trench power DMOS and stabilizing the breakdown voltage VDS between the source and drain.

  Next, a sacrificial silicon oxide film (not shown) is formed on the inner walls of the trenches 4 and 5 by thermal oxidation, etching damage on the inner walls of the trenches 4 and 5 is removed, the sacrificial silicon oxide film is removed, and then the trench 4 is thermally oxidized. The gate insulating film 10 is formed again on the inner wall 5. After that, after depositing a polysilicon film filling the trenches 4 and 5 and covering the entire surface of the semiconductor substrate 7, the polysilicon film is etched back. The polysilicon film after the etch back is buried below the trenches 4 and 5 to form gate electrodes 12a, 12b, and 12c as shown in FIGS. 5A, 5B, and 5C. To do. The polysilicon film is an N + type polysilicon film through a predetermined process.

  Next, as shown in FIG. 6, an insulating film is formed on the entire surface of the semiconductor substrate 7 including the inner wall of the trench by CVD or the like, and a portion other than the trench 4 for forming the source lead electrode 17a in FIG. After that, the insulating film is etched back by predetermined anisotropic etching. After the etch back, first spacers 11 are formed on both side walls of the trench 4 as shown in FIG. 6A, and the gate electrode 12a is exposed on the bottom surface.

  Since the regions shown in FIGS. 6B and 6C are protected by a resist mask, the insulating film is not etched back. As shown in FIG. 6B, the insulating film 11a remains deposited on the surface of the gate insulating film 10 above the gate electrode 12b and on the sidewalls on both sides of the trench 4. As shown in FIG. 6C, the narrow trench 5 is filled with the gate electrode 12c below and the insulating film 11b above.

  Next, as shown in FIG. 7A, the exposed portion of the gate electrode 12a is removed by a predetermined anisotropic etching using the first spacer 11 as a mask, and the first spacer 11 is formed below the first spacer 11 with the first spacer 11 removed. A gate electrode 12a having the same side surface as that of the first spacer 11 is formed. In this case, since the regions shown in FIGS. 7B and 7C are covered with the insulating films 11a and 11b, the gate electrodes 12b and 12c therebelow remain without being etched.

  Next, arsenic (As) ions are ion-implanted at a low acceleration voltage into the P-type base layer 9 exposed through the gate insulating film 10 between the gate electrodes 12a formed on the sidewalls of the trench 4 to form P-type. An N + type source layer 13 is formed in a shallow position of the semiconductor layer 9. Thereafter, boron (B) ions are ion-implanted at a medium acceleration voltage, and the P + -type contact layer 14 is formed of boron whose average range is deeper than the bottom surface of the N + -type source layer 13. In this case, it goes without saying that B ion implantation may be performed first and As ion implantation may be performed later.

  As a result, the P + type contact layer 14 is formed in the P type base layer 9 immediately below the N + type source layer 13 in contact with or spaced apart from the bottom surface of the N + type source layer 13. When the N + type source layer 13 and the P + type contact layer 14 are in contact with each other, the area occupied by the P + type contact layer 14 with respect to the N + type source layer 13 can be increased. As a matter of course, the N + type source layer 13 is not formed on the bottom surfaces of the trenches 4 and 5 in the regions shown in FIGS. 7B and 7C.

The P + type contact layer 14 may be formed at a predetermined interval directly below the N + type source layer 13 using a resist mask. This is to cope with the formation of the source lead electrode 17a connected to the N + type source layer 13 in which the P + type contact layer 14 is not formed.
In FIG. 7A, the lateral width of the P + type contact layer 14 is shown to be narrower than the lateral width of the N + type source layer 13. It may be larger than the width of.

  Next, the insulating films 11a and 11b remaining on FIGS. 7B and 7C are etched back by predetermined anisotropic etching. As shown in FIG. 8B, a first spacer 11a is formed on the side wall of the trench 4 in the gate lead-out region 6a in FIG. 1, and the gate electrode 12b is exposed between the spacers. As shown in FIG. 8C, an insulating film 11b is buried in the narrow trench 5 so as to cover the gate electrode 12c.

  Next, the entire surface of the P-type semiconductor substrate 7 including the inside of the trench 4 is covered with a new insulating film formed by the CVD method. Thereafter, as shown in FIG. 8, the insulating film is etched back by predetermined anisotropic etching. In FIG. 8A, a first spacer 11 formed on the sidewall of the trench 4 after the etch back and a new second spacer 15 made of the insulating film covering the gate electrode 12a are formed. It is shown that the N + type source layer 13 is exposed on the bottom surface of the contact opening 25 having the side surface of the spacer 15 as an end surface.

  Thereafter, the N + source layer 13 is separated into left and right portions by a predetermined anisotropic etching using the second spacer 15 as a mask, penetrating the P + type contact layer 14 formed immediately below the N + type source layer 13. A recess 16 is formed which extends to the inside and has the same side as the side of the contact opening 25.

  In this case, as described in FIG. 2, the contact opening 25 extending to the recess 16 shown in FIG. 8A and the surface of the N + type source layer 13 as shown in FIG. The contact openings 25 may be formed at an appropriate ratio. Further, the contact opening 25 in which the P + type contact layer 14 is removed from the configuration shown in FIG. 2B and the contact opening 25 extending to the recess 16 shown in FIG. 8A are formed at an appropriate ratio. You may do it.

  FIG. 8B shows a state after the etch back of the insulating film in the vicinity of the gate lead-out region 6a. A second spacer 15a is formed on the side surface of the first spacer 11a formed on the side wall in the trench 4, and a contact opening 25a having the side surface of the second spacer 15a as an end surface is formed. A part of the surface of the gate electrode 12b is exposed at the bottom surface of the contact opening 25a. FIG. 8C shows a state after the etch back in the vicinity of the narrow trench 5. The newly deposited insulating film is removed by etch back, and the previous insulating film 11a and the like are still buried in the trench 5.

  Next, as shown in FIG. 9, a metal film such as a tungsten (W) film covering the entire surface of the semiconductor substrate 7 including the inside of the trench 4 is formed by a CVD method or the like. Normally, a polysilicon film is used. However, since an N + type polysilicon film is used to provide conductivity, it is in ohmic contact with the N + type source layer 13 but is exposed to the bottom surface of the trench 4. This is because it is difficult to establish an ohmic connection.

  Next, after patterning the gate connection electrode 17c with a resist mask in the gate connection electrode formation region 6, the tungsten film is etched away by a predetermined anisotropic etching or the like. FIG. 9A shows a source extraction electrode 17a made of a tungsten film which is connected to both the P + type contact layer 14 and the N + type source layer 13 in the contact opening 25 after etching and extends to the upper end thereof. .

  The source lead electrode 17 a that is in ohmic contact with the P + -type contact layer 14 and the N + -type source layer 13 is drawn to the upper end of the contact opening 25. In addition, the N + type source layer 13 divided into the left and right is filled with tungsten, which is a constituent material of the source extraction electrode 17a, in the middle space, and the N + type source layer 13 divided into the left and right and tungsten filling the space therebetween. Therefore, it functions as if it were a single N + type source layer 13 that is not divided.

  As a result, one source lead electrode 17a exhibits two functions and effects of leading the P + contact layer 14 and leading the N + source layer 13 without increasing the width of the contact opening 25. Become. Therefore, the width of the source region 1 shown in FIG. 1 can be reduced as a whole, and the size of the N-channel trench power DMOS transistor can be reduced. As described above, the ON prevention effect of the NPN parasitic transistor is also increased.

  FIG. 9B shows a state in the vicinity of the gate lead electrode 17b formation region after etching the tungsten film. As shown in the figure, since the gate connection electrode 17c formation region is covered with a resist mask, the gate connection electrode 17c is formed on the insulating film 23 so as to extend from the gate lead electrode 17b. When the double-layered aluminum wiring technique shown in FIG. 4 is used, the entire surface may be etched back without forming a resist mask in the gate connection electrode 17c formation region.

  FIG. 9C shows a state after etching of tungsten in the vicinity of the narrow trench 5 region. Since the trench 5 is filled with the insulating film 11b and the like, all the tungsten film deposited thereon is removed by etching. As a result, the source lead electrode 17a made of tungsten shown in FIG. 9A formed in the source lead region 1 of FIG. 1 and the tungsten shown in FIG. 9B formed in the gate lead region 6a of FIG. It is completely separated from the gate lead electrode 17b by the narrow trench 5 portion where there is no lead electrode made of tungsten shown in FIG.

  Next, as shown in FIG. 2, an N + type drain layer 18 is formed on the surface of the N− type drain layer 18a adjacent to the sidewall of the trench 4 by ion implantation through a predetermined process. Next, as shown in the figure, an interlayer insulating film 19 and the like are deposited on the entire surface of the semiconductor substrate 7, contact openings 32 and 33 are formed through a predetermined process, and the source electrode 21 connected to the source lead electrode 17a is formed. The drain electrode 20 connected to the N + drain layer 18 is formed, and the external gate electrode 24 connected to the gate connection electrode 17c is formed as shown in FIG. Finally, the N channel trench power DMOS transistor is completed by covering the whole with a passivation film.

[Second Embodiment]
Next, a second embodiment will be described with reference to FIG. The plan view of the second embodiment is the same as that of the first embodiment and is shown in FIG. FIG. 10A is a cross-sectional view taken along the line AA in FIG. 1 and is a cross-sectional view centering on a region where the source lead electrode 17a is formed according to the second embodiment. When FIG. 10A is compared with FIG. 2A, the difference is that the lateral width of the P + type contact layer 14 formed immediately below the N + type source layer 13 is only smaller in FIG. 10A. . The effect is also substantially the same.

  In FIG. 10B, a polysilicon lead electrode 22 is formed of N + type polysilicon on both side surfaces of the second spacer 15, and the N + type source layer 13 and the P + type contact layer 14 exposed in the recessed portion 16 between them are formed. A state in which a source extraction electrode 17a made of tungsten extending to the upper end of the contact opening 25 is formed is shown.

  The source lead electrode 17a and the polysilicon lead electrode 22 are ohmically connected over the entire surface in contact with each other. The polysilicon lead electrode 22 is in ohmic contact with the N + type source layer 13. Therefore, this structure has the effect of increasing the connection area between the N + type source layer 13 and the source lead electrode 17a as a result.

  Next, a method for manufacturing the semiconductor device of this embodiment will be described. Of the manufacturing method of the present embodiment, FIG. 10A will be described by omitting the drawing since only the formation process of the P + type contact layer 14 is different from that of the first embodiment. The same applies to FIGS. 5 and 6 showing the method of manufacturing the semiconductor device of the first embodiment. FIG. 7 is different. At this stage, the P + type contact layer 14 is not formed, and only the N + type source layer 13 is formed in the P type base layer 9 below the bottom of the trench.

  Next, the spacer 15 made of an insulator is formed in the step of FIG. 8, and the N + type source layer 13 is exposed on the bottom surface of the contact opening 25 having the side surface of the spacer 15 as an end surface. The recess 16 is formed so as to extend through the N + type source layer 13 to the P type base layer 9. Next, B ions are implanted into the P-type base layer 9 in the recessed portion 16 from the upper portion of the contact opening 25 and heat-treated to form the P + -type contact layer 14 in the P-type base layer 9. As a result, the P + -type contact layer 14 is formed in the P-type base layer 9 with a width smaller than that of the first embodiment, with the recessed portion 16 directly below the N + -type source layer 13 as the center. Thereafter, source lead electrodes 17a and the like are formed as shown in FIG. 9, and finally an N-channel trench power DMOS transistor is completed as shown in FIG.

  Next, the manufacturing method in the case of FIG. 10 (B) is demonstrated based on FIG. The process until the contact opening 25 is formed by the second spacer 15 is the same as in the case of FIG. Next, a polysilicon film is deposited on the entire surface of the semiconductor substrate 7 including the inside of the trench 4, and the polysilicon film is converted into an N + type polysilicon film through a predetermined process. Next, the entire polysilicon film is etched back by predetermined anisotropic etching to form a polysilicon lead electrode 22 on the side wall of the second spacer 15.

  Since the polysilicon lead electrode 22 is doped in N + type, it can make ohmic contact with the surface of the N + type source layer 13. Next, using the polysilicon lead electrode 22 as a mask, a recess 16 that penetrates the N + type source layer 13 and extends into the P type base layer 9 is formed. In this case, the upper portion of the polysilicon lead electrode 22 is also etched and becomes lower than the upper end of the contact opening 25, but there is no problem.

  Next, B ions are implanted into the P-type base layer 9 exposed in the recess 16 to form the P + -type contact layer 14. As described above, the polysilicon lead electrode 22 and the source lead electrode 17a are ohmically connected, and the polysilicon lead electrode 22 and the N + type source layer 13 are also ohmically connected. Therefore, according to the present embodiment, the source lead electrode 17a is substantially provided. And the connection area between the N + type source electrode 13 can be increased.

  FIG. 11B shows a cross-sectional view of a region where the gate lead electrode 17b is formed when the polysilicon lead electrode 22 is formed. The polysilicon lead electrode 22a is formed on both side surfaces of the first embodiment and the second spacer 15a. There is no other difference just by being done.

  In this embodiment as well, as in FIG. 2B of the first embodiment, the above-mentioned depression is obtained by forming the source lead electrode 17a in the contact opening 25 with the N + type source layer 13 exposed. The part 16 having the source extraction electrode 17a formed therein may be formed at a predetermined interval.

  Further, as shown as one example of the first embodiment, the source lead electrode 17a connected to the N + type source layer 13 in which the P + type contact layer 14 is not formed immediately below, and the source from the recessed portion 16 Needless to say, the lead electrode 17a may be formed at a predetermined interval.

[Third Embodiment]
A third embodiment of the present invention will be described below. In the first embodiment, etc., the place where the source layer and the drain layer are formed is changed, so that a new drawing is omitted and only the text is described. The main difference between the third embodiment, the first embodiment, and the second embodiment is that an N + type drain layer 18 is formed on the P-type semiconductor substrate 7 immediately below the bottom surface of the trench 4. The point formed adjacent to the upper end of the trench 4 is the P-type base layer 9, the PN + type source layer 13, and the P + type contact layer 14 having the same configuration as in the first and second embodiments.

  Accordingly, the plan view of the N-channel trench DMOS transistor according to the third embodiment is also the same as FIG. 1 according to the first embodiment. As a result, a drain lead electrode connected to the N + type drain layer 18 exposed on the bottom surface of the trench 4 and extending to the upper end of the trench is formed. The drain lead electrode and the gate lead electrode 17b are the same as those in the first embodiment. Similarly, it is reliably divided in the narrow trench 5 region.

  Further, since the P + type contact layer 14 is formed in the P type base layer 9 immediately below the N + type source layer 13 formed adjacent to the upper end of the trench, the N + type is used for the same reason as in the first embodiment. The width of the source layer 13 can be reduced, and the size of the N-channel power MOS transistor can be reduced. In addition, it is possible to prevent the source-drain breakdown voltage VDS from being lowered by preventing the NPN parasitic transistor from being turned on.

  In this embodiment, the source electrode is not drawn from the bottom surface of the trench 4, but the connection method with the N + type source layer and the P + type contact layer is the same as in the first embodiment and the second embodiment. Similarly, it goes without saying that various forms such as forming a recess can be realized.

  The next major difference is that the positions of the gate electrode 12a and the first spacer 11 shown in FIG. 2A are upside down because the N + type source layer 13 is formed on the surface side of the semiconductor substrate 7. is there. In this case, first, the insulating film covering the entire surface of the semiconductor substrate is etched back by predetermined anisotropic etching, and the trench 4 and the like are filled with the insulating film. Thereafter, the polysilicon film deposited thereon is etched back by anisotropic etching to form a gate electrode on the upper side wall of the trench 4. This is because it is necessary to form the channel portion adjacent to the N + type source layer.

  Another difference is that the P-type base layer 9 in the first embodiment is formed in the P-type semiconductor substrate 7 so as to extend from directly under the bottom surface of the trench 4 to the side wall of the trench 4. In the embodiment, it is an N − type drain layer 18a. Further, as described above, the P-type base layer 9 is different in that it is formed from the surface of the semiconductor substrate. The N− drain layer 18a can be formed from the surface of the P-type semiconductor substrate 7 as in the first embodiment and the like, but phosphorus (P) ions or the like are implanted into the P-type semiconductor substrate 7 from the sidewalls of the trench 4. This can be easily formed. The P-type base layer 9 can also be easily formed from the surface of the P-type semiconductor substrate 7.

  In each embodiment of the present invention, the case of the N-channel trench power DMOS has been described. However, it is needless to say that the present invention can be applied to a P-channel trench power DMOS transistor, and can be applied to other embodiments having the same technical idea.

DESCRIPTION OF SYMBOLS 1 Source region 2 Gate region 3 Drain region 4 Trench 5 Narrow trench 6 Gate connection electrode region 6a Gate extraction region 7 P-type semiconductor substrate 9 P-type base layer 10 Gate insulating film
11, 11a First spacer 12a, 12b, 12c Gate electrode
13 N + type source layer 14 P + type contact layer 15, 15a Second spacer 16 Recessed portion 17a Source extraction electrode 17b Gate extraction electrode
17c Gate connection electrode 18 N + drain layer 18a N- drain layer
19 Interlayer insulating film 20 Drain electrode 21 Source electrode
22, 22a Polysilicon lead electrode 23 Insulating film 24 External gate electrode 25 Opening for contact 27 Interlayer insulating film 28 Gate connection electrode
29 Interlayer insulating film 30 External gate electrodes 31 to 34, contact opening
59 Source region 60 Gate region 61 Drain region
62 P + type contact region 63, 64, 65 Opening for contact

Claims (10)

A semiconductor device having a trench in which a wide region and a narrow region are integrally formed,
A gate electrode formed on the inner wall of the trench via a gate insulating film;
A width having an active layer extraction electrode connected to the first semiconductor layer of the first conductivity type exposed on the bottom surface of the trench and extending in the trench to the upper end thereof via the insulating film. A wide first trench, and a gate electrode embedded in the inner wall of the trench via the gate insulating film,
A wide second trench having a gate lead electrode connected to the gate electrode and extending through the trench to its upper end;
A gate electrode embedded in the inner wall of the trench through the gate insulating film;
An insulating film embedded in the trench, and a narrow third trench connecting the first trench and the second trench, and the gate electrode of the first trench, The gate electrode of the second trench is connected to the gate electrode of the third trench, and the active layer extraction electrode of the first trench and the gate extraction electrode of the second trench are the third A semiconductor device which is divided by a trench. In the first trench, a recessed portion penetrating the first semiconductor layer, and a second conductive layer formed immediately below the first semiconductor layer with a portion of the surface exposed at the recessed portion. A second semiconductor layer of a type, wherein at least a part of the active layer lead electrode is connected to the first semiconductor layer and the second semiconductor layer exposed in the recess. The semiconductor device according to claim 1. 3. The device according to claim 2, wherein in the first trench, all of the active layer lead electrodes are connected to the first semiconductor layer and the second semiconductor layer exposed in the recess portion. Semiconductor device. In the first trench, a polysilicon lead electrode formed on the inner wall of the first trench via the gate electrode and an insulating film, and the bottom surface of the trench exposed between the polysilicon lead electrodes A recess that extends through the first semiconductor layer to the semiconductor layer immediately below the first semiconductor layer, and a portion of the surface of the recess is exposed immediately below the first semiconductor layer. A second semiconductor layer of the second conductivity type formed, wherein the first semiconductor layer and the second semiconductor layer have at least a part of the active layer lead electrode exposed in the recess. 2. The semiconductor device according to claim 1, wherein the semiconductor device is connected and buried between the polysilicon lead electrodes. 5. The semiconductor device according to claim 1, wherein the semiconductor device is a trench power DMOS transistor having a trench gate structure, and the first semiconductor layer is a source layer. 2. The semiconductor device according to claim 1, wherein the semiconductor device is a trench power DMOS transistor having a trench gate structure, and the first semiconductor layer is a drain layer. A method of manufacturing a semiconductor device having a trench in which a wide region and a narrow region are integrally formed,
Forming a gate electrode on the inner wall of the trench through a gate insulating film;
An active layer lead electrode is formed which is connected to the first semiconductor layer of the first conductivity type exposed at the bottom of the trench and extends to the upper end of the trench through the gate electrode and the first insulating film. Forming a wide first trench including a step, and forming a gate electrode embedded in the inner wall of the trench through the gate insulating film;
Forming a gate lead electrode connected to the gate electrode and extending in the trench to the upper end thereof, and a wide second trench.
Forming a gate electrode embedded in the inner wall of the trench through the gate insulating film;
A step of forming an insulating film to bury the trench, and a narrow third trench connecting the second trench and the second trench, and the gate of the first trench An electrode and the gate electrode of the second trench are connected by the gate electrode of the third trench, and the active layer lead electrode of the first trench and the gate lead electrode of the second trench are connected to the first trench. 3. A method of manufacturing a semiconductor device, wherein the semiconductor device is divided by three trenches. A step of forming a recessed portion penetrating the first semiconductor layer in the first trench; and a second conductive structure in which a portion of the surface of the recessed portion is exposed immediately below the first semiconductor layer. Forming a second semiconductor layer of a mold, and at least a part of the active layer lead electrode is connected to the first semiconductor layer and the second semiconductor layer exposed in the recess. The method of manufacturing a semiconductor device according to claim 7. 9. The device according to claim 8, wherein in the first trench, all of the active layer lead electrodes are connected to the first semiconductor layer and the second semiconductor layer exposed in the recess. A method for manufacturing a semiconductor device. Forming a polysilicon lead electrode on the inner wall of the first trench via the gate electrode and an insulating film in the first trench; and the first semiconductor exposed between the polysilicon lead electrode Forming a recess that penetrates the layer and extends to the semiconductor layer immediately below the first semiconductor layer; and a first portion of the surface of the recess that is exposed immediately below the first semiconductor layer. Forming a second-conductivity-type second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer have at least a part of the active layer lead electrode exposed in the recess. The method for manufacturing a semiconductor device according to claim 7, wherein the connection is made between the polysilicon lead electrodes.

Images