JP5533011B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device suitable for a trench gate type MOSFET having a trench contact structure.

  Semiconductor devices having a trench gate structure include a trench gate type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and a trench gate type IGBT (Insulated Gate Bipolar Transistor).

FIG. 5 is a cross-sectional view of a main part of a conventional n-channel trench gate type MOSFET.
The manufacturing process is shown below. First, a thick insulating film (oxide film) 3 is formed on the surface of an n-type silicon semiconductor substrate composed of an n ⁺ drain region 1 and a high resistivity n ⁻ drift region 2. Next, a p-type well region 4 is selectively formed using the opened insulating film 3 as a mask. Then, a plurality of trenches 5 reaching the n ⁻ drift region 2 from the surface of the well region 4 are formed, and a gate electrode 7 is embedded therein via a gate insulating film 6. An n ⁺ source region 8 and a p ⁺ contact region 9 deeper than the n ⁺ source region 8 are formed on the surface of the well region 4 sandwiched between the trenches 5, and then the n ⁺ source region 8 and the p ⁺ contact region 9 are electrically connected to the surface. A source electrode 10 is provided for contact. At this time, the gate electrode 7 is insulated from the source electrode 10 by the interlayer insulating film (BPSG film) 11. In addition, a metal gate electrode that contacts the gate electrode 7 is provided in a cross section (not shown). Finally, the drain electrode 12 is provided in contact with the n ⁺ drain region 1. In this way, a trench gate type MOSFET is manufactured.

In the trench gate type IGBT, a p-type semiconductor region electrically connected to the back surface of the drain region 1 is further formed in FIG.
The conventional trench gate type MOSFET shown in FIG. 5 employs a “trench gate structure”, thereby increasing the channel width and realizing significant miniaturization. However, if the structure shown in FIG. 5 is miniaturized, specifically, the cell pitch (distance between the parallel trench gates) is reduced, the source contact area becomes smaller, and the contact resistance increases. In order to solve this problem, Patent Documents 1 and 2 disclose a semiconductor device in which a contact area is expanded using a so-called trench contact structure. Here, as shown in FIG. 6, the trench contact structure has an electrical connection with the contact region 9 at the bottom (bottom surface) of the contact trench 14 and an electrical connection with the source region 8 at the side wall. It expands the source contact area.

  However, in the trench contact structures disclosed in Patent Documents 1 and 2, after the contact trench 14 is formed by RIE (Reactive Ion Etching), ions are implanted into the bottom portion and diffused to form the contact region 9. . For this reason, the implanted ions diffuse laterally, and the distance from the channel is reduced, which may affect the threshold voltage. In addition to reducing the cell pitch, when the source region 8 is made shallow, the contact area between the source electrode and the source region (hereinafter also referred to as “source contact area”) is reduced on the side wall of the contact trench 14. Further, if a high concentration source region is formed also on the side wall of the contact trench 14 in order to secure this source contact area, the concentration gradient between the source region and the well region 4 becomes steep and there is a problem that the avalanche resistance is lowered. It was.

  In order to solve this problem, in Patent Documents 3 and 4, as shown in FIGS. 7A to 7C, after forming the contact trench 14, a protective film 15 is formed on the side wall of the contact trench 14. It is described that ion implantation for forming the contact region 9 is performed in the formed state. In addition, as shown in FIG. 7D, a trench contact structure including a contact region 9 having a width narrower than the width of the contact trench 14 is described.

JP 2003-101019 A JP 2003-92405 A JP 2006-140239 A JP 2009-43966 A

  However, in the trench contact structures disclosed in Patent Documents 3 and 4, it is necessary to add a step of forming the protective film 15 on the side wall of the contact trench 14 and a step of removing the protective film 15, leading to an increase in cost. .

  The present invention has been made in view of these problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device that can be miniaturized by a simple method.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a semiconductor substrate having a first conductivity type, a first semiconductor region having a second conductivity type formed on a surface of the semiconductor substrate, and the first semiconductor. A first conductive type second semiconductor region formed on the surface of the region, a first trench extending from the second semiconductor region through the first semiconductor region to the semiconductor substrate, and an inner wall of the first trench An insulating layer provided; a gate electrode that fills the inside of the first trench through the insulating layer; and a bottom in the second semiconductor region, or the first semiconductor layer penetrating through the second semiconductor region. In a method of manufacturing a semiconductor device comprising: a second trench having a bottom in a semiconductor region; and a second conductivity type high concentration region in contact with the first semiconductor region at the bottom of the second trench.
Forming a first insulating film on the second semiconductor region; forming an opening in the first insulating film to expose a part of the second semiconductor region; and the first insulation. Forming the second trench in the second semiconductor region by anisotropic etching using the film as a mask, and retreating the inner wall of the second trench by isotropic etching using the first insulating film as a mask. a step of extending the said first insulating film is a second conductivity type dopant as a mask ions are implanted into the bottom of the second trench, and annealing, and etching the first insulating film said first Expanding the width of the opening of the insulating film to be larger than the width of the opening of the second trench, and performing these steps in this order.

In the method for manufacturing the semiconductor device,
The first insulating film is a laminated film of an HTO film and a BPSG film formed on the HTO film, and the BPSG film is reflowed by annealing in the annealing step.

In the method of manufacturing a semiconductor device, the second insulating film may be further etched after the step of etching the first insulating film to increase the width of the opening of the first insulating film to be larger than the opening width of the second trench. The method includes a step of embedding Al or an Al—Si alloy in the trench by sputtering.

  According to the method of manufacturing a semiconductor device of the present invention, ion implantation for forming a contact region is performed in a well region using an interlayer insulating film having an opening width narrower than that of the contact trench as a mask. Ions are not implanted into the sidewall. Therefore, a semiconductor device having a small contact resistance between the source electrode and the source region can be provided.

  In addition, after forming a trench by anisotropic etching using an interlayer insulating film having a narrow opening width as a mask, isotropic etching is performed to widen the width of the trench, thereby improving the burying property of the source electrode. For this reason, a low-cost semiconductor device can be provided without adding a process such as embedding the plug electrode in the trench.

  In addition, when the opening of the interlayer insulating film is widened, the contact area with the source region can be increased by widening the opening to be wider than the opening width of the contact trench, and a semiconductor device with low contact resistance is provided. can do.

  From the above, it is possible to provide a semiconductor device that achieves both cell pitch reduction and low cost.

It is principal part sectional drawing which shows the structure in the middle of manufacture of the trench gate type MOSFET which concerns on Example 1 of this invention. It is principal part sectional drawing which shows the structure in the middle of manufacture of the trench gate type MOSFET which concerns on Example 1 of this invention. It is principal part sectional drawing which shows the structure in the middle of manufacture of the trench gate type MOSFET which concerns on Example 1 of this invention. It is principal part sectional drawing of the trench gate type MOSFET which concerns on Example 1 of this invention. It is principal part sectional drawing of the conventional trench gate type MOSFET. It is principal part sectional drawing of the trench gate type MOSFET which has a trench contact structure. It is principal part sectional drawing of the trench gate type MOSFET which has a trench contact structure.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Here, an n-channel trench gate type MOSFET will be taken as an example and described according to its manufacturing method. The same reference numerals are used for portions corresponding to the configurations of the prior art in FIGS. In the following embodiments, the first conductivity type is n-type and the second conductivity type is p-type. The + and-symbols indicate that the n-type or p-type impurity concentration is relatively high or low.

  This example is an embodiment of the first semiconductor device of the present invention. 1 to 4 are main-portion cross-sectional views showing a manufacturing process of the first semiconductor device, and show a cross section perpendicular to the longitudinal direction of a trench formed in a stripe shape. Moreover, FIG.1 (c)-FIG.2 (c) have shown only the flame | frame A (area | region enclosed with the broken line) in FIG.1 (b).

First, as shown in FIG. 1A, a silicon semiconductor substrate having an n ⁺ drain region 1 and having a high resistivity n-type epitaxial layer is prepared. An oxide film 3 having an opening is formed on an n drift region 2 (n type epitaxial layer) having a high specific resistance, boron ions are implanted and driven in, and a p type well region 4 is selectively formed. The insulating film (oxide film) 3 may be formed by LOCOS (Local Oxidation of Silicon) or STI (Shallow Trench Isolation).

Next, as shown in FIG. 1B, a stripe-shaped trench 5 reaching the n drift region 2 from the surface of the p-type well region 4 is formed by anisotropic etching. In order to clean the inside of the trench 5, a cleaning process is performed with a dilute solution of hydrofluoric acid, followed by a hydrogen annealing process. By this treatment, the shape of the opening and bottom of the trench 5 is rounded. A gate electrode 7 is embedded in the trench 5 through a gate insulating film (oxide film) 6. As the gate electrode 7, it is usually preferable to deposit polycrystalline silicon doped with n-type by CVD (Chemical Vapor Deposition). Then, the gate insulating film 6 on the substrate surface is removed, and a screen oxide film 13 is formed as shown in FIG.

Next, after forming the n ⁺ source region 8 as shown in FIG. 1D, an HTO (High Temperature Oxide) film 16 and a BPSG film (boro-phosphosilicate glass film) 17 are deposited, and a screen oxide film 13 is formed. Then, an interlayer insulating film 11 made of the HTO film 16 and the BPSG film 17 and having a thickness of about 0.8 μm is formed. The thicknesses of the HTO film 16 and the BPSG film 17 are about 0.2 μm and 0.6 μm, respectively. The source region 8 is formed by As (arsenic) ion implantation and drive-in processing. The depth is about 0.4 to 0.6 μm. The source region 8 may be formed before the trench 5 is formed.

  Next, as shown in FIG. 2A, the interlayer insulating film 11 is removed and opened by anisotropic etching (RIE) using a mask (not shown), and anisotropic etching is performed using the interlayer insulating film 11 as a mask. Striped contact trenches 14 having a width of 0.2 μm and a depth of 0.3 to 0.5 μm are formed.

  Subsequently, as shown in FIG. 2 (b), the contact trench 14 is etched by isotropic etching such as CDE (chemical dry etching) so as to be broadened by about 0.1 to 0.2 μm as a whole. The contact trench 14 is preferably deeper than the source region 8 and reaches the p-well region 4. The interlayer insulating film 11 has a ridge that projects over the contact trench 14.

Next, as shown in FIG. 2C, a heat treatment of about 850 ° C. is performed in an oxygen and hydrogen atmosphere to form a screen oxide film 18 having a thickness of 15 nm on the inner surface of the contact trench 14. The screen oxide film 18 may be formed as necessary. Next, BF ₂ ions are implanted in a direction perpendicular to the semiconductor substrate. Implantation is performed at a dose of BF ₂ ions of 3.0 × 10 ¹⁵ cm ⁻² and an acceleration voltage of 50 keV. Note that the side wall of the contact trench 14 is behind the ridge of the interlayer insulating film 11, and ions are not implanted into the side wall.

Next, as shown in FIG. 3A, activation annealing is performed at 900 ° C. for 30 minutes in a nitrogen gas atmosphere so that the p ⁺ contact region 9 reaches the p well region 4 at the bottom of the contact trench 14. Form. Simultaneously with this activation, reflow of the BPSG film 17 is also performed. The HTO film 16 prevents diffusion of impurities from the BPSG film 17 to the semiconductor substrate, and becomes a foundation for reflow.

Next, as shown in FIG. 3B, wet treatment with hydrofluoric acid or isotropic etching such as CDE is performed to etch the interlayer insulating film 11 by at least about 0.15 μm to 0.25 μm. The opening width H (width of the lower end of the opening of the interlayer insulating film 11 in contact with the semiconductor substrate) is made wider than the opening width h of the contact trench 14 (opening width of the upper end of the contact trench 14). Remove the part. At this time, the screen oxide film 18 is also removed. In this embodiment, the interlayer insulating film 11 is retracted so that the surface of the n ⁺ source region 8 is exposed. However, the opening width H of the interlayer insulating film 11 and the opening width h of the contact trench 14 are the same. Etching may be performed so as to recede to the extent that the flange portion of the interlayer insulating film 11 is eliminated. That is, the etching may be performed so that the width H ≧ the width h.

  Here, the BPSG film 17 has a mountain shape around the gate electrode 7 by reflow. Therefore, the breakdown voltage between the gate and the source is ensured, and the aspect ratio when the source electrode 10 is formed by filling the contact trench 14 with a metal material such as Al (aluminum) or an Al—Si alloy is reduced.

Finally, as shown in FIG. 4, the source electrode 10 that is in contact with the surfaces of the n ⁺ source region 8 and the p ⁺ contact region 9 is formed by reflow sputtering with an Al—Si alloy, and the gate electrode 7 has a cross section not shown. A metal gate electrode in contact with the drain electrode 12 is provided on the back surface. The source electrode 10 may be made of aluminum.

  In the semiconductor device manufactured in this way, the width T of the bottom of the stripe-shaped contact trench 14 is 0.3 to 0.4 μm, whereas the width t of the contact region 9 is 0.2 μm. Here, the shape of the bottom part of the contact trench 14 and the part of the contact region 9 exposed at the bottom part of the contact trench 14 are elongated rectangles, and the widths T and t are the distances between the long sides of the respective rectangles. In the present invention, it is important that t <T in order to secure the distance between the contact region 9 and the trench 5, and further, the distance from the sidewall of the trench 5 to the contact region 9 is preferably 0.2 μm or more. .

  In the above embodiment, the trench shape is exemplified as a stripe shape, but it may be a square pattern or a circular pattern. As the contact trenches, there are strip-like grooves (elongated rectangular parallelepiped grooves (including those having a trapezoidal or U-shaped cross section) as described in the embodiment in order to secure a contact area between the source region and the contact region and the electrode. In addition, the stripe-shaped trench may be formed in a zigzag shape or a corrugated shape in order to secure a contact area, and when the shape of the trench having the gate insulating film is a square shape, a circular pattern, etc. In these cases, the widths T and t may be appropriately selected so that the distance between the trench having the gate insulating film and the contact region can be secured.

  In the above embodiment, an n-channel trench gate type MOSFET has been described as an example. However, the present invention relates to a structure of a contact trench and a manufacturing method thereof, and other source and drain structures are optional. Can be selected. Therefore, the present invention can be applied not only to the MOSFET but also to an IGBT or the like as long as it has a contact trench. In addition to silicon, a semiconductor substrate made of silicon carbide (SiC) can be used.

1 Drain region 2 Drift region 3 Insulating film (oxide film)
4 well region 5 trench 6 gate insulating film (oxide film)
7 Gate electrode 8 Source region 9 Contact region 10 Source electrode 11 Interlayer insulating film 12 Drain electrode 13 Screen oxide film 15 Protective film 14 Contact trench 16 HTO film 17 BPSG film 18 Screen oxide film T Bottom width of contact trench t Width of contact region 9 H Width of opening of interlayer insulating film 11 h Width of opening of contact trench 14

Claims (3)

A first conductivity type semiconductor substrate; a second conductivity type first semiconductor region formed on the surface of the semiconductor substrate; and a first conductivity type second semiconductor region formed on the surface of the first semiconductor region; A first trench extending from the second semiconductor region through the first semiconductor region to the semiconductor substrate, an insulating layer provided on an inner wall of the first trench, and an interior of the first trench through the insulating layer And a second trench having a bottom in the second semiconductor region or penetrating the second semiconductor region and having a bottom in the first semiconductor region, and a bottom of the second trench And a high concentration region of a second conductivity type in contact with the first semiconductor region.
Forming a first insulating film on the second semiconductor region; forming an opening in the first insulating film to expose a part of the second semiconductor region; and the first insulation. Forming the second trench in the second semiconductor region by anisotropic etching using the film as a mask, and retreating the inner wall of the second trench by isotropic etching using the first insulating film as a mask. a step of extending the said first insulating film is a second conductivity type dopant as a mask ions are implanted into the bottom of the second trench, and annealing, and etching the first insulating film said first Expanding the width of the opening of the insulating film to be equal to or larger than the width of the opening of the second trench, and performing these steps in this order. The first insulating film is a laminated film of an HTO film and a BPSG film formed on the HTO film, and the BPSG film is reflowed by annealing in the annealing step. The manufacturing method of the semiconductor device of description. After the step of etching the first insulating film and expanding the width of the opening of the first insulating film to be equal to or larger than the opening width of the second trench, Al or Al—Si alloy is sputtered into the second trench. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of embedding.

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