JP6258561B1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP6258561B1
JP6258561B1 JP2017521166A JP2017521166A JP6258561B1 JP 6258561 B1 JP6258561 B1 JP 6258561B1 JP 2017521166 A JP2017521166 A JP 2017521166A JP 2017521166 A JP2017521166 A JP 2017521166A JP 6258561 B1 JP6258561 B1 JP 6258561B1
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conductor
region
overvoltage protection
protection diode
semiconductor device
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JPWO2017203671A1 (en
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涼平 小谷
涼平 小谷
松原　寿樹
寿樹 松原
石塚　信隆
信隆 石塚
雅人 三川
雅人 三川
浩 押野
浩 押野
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Shindengen Electric Manufacturing Co Ltd
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Abstract

【課題】耐圧の低下を抑制し、信頼性を向上させることが可能な半導体装置を提供する。【解決手段】実施形態の半導体装置１では、逆バイアス印加状態において絶縁膜４近傍の拡散層３が空乏化するように導体部６，７の端部が過電圧保護ダイオード５に電気的に接続され、および／または、逆バイアス印加状態において絶縁膜４近傍の周辺半導体領域１０が空乏化するように導体部８，９の端部が過電圧保護ダイオード５に電気的に接続されている。A semiconductor device capable of suppressing a decrease in breakdown voltage and improving reliability is provided. In the semiconductor device according to the embodiment, the end portions of the conductor portions are electrically connected to the overvoltage protection diode so that the diffusion layer near the insulating film is depleted in the reverse bias applied state. And / or the ends of the conductor portions 8 and 9 are electrically connected to the overvoltage protection diode 5 so that the peripheral semiconductor region 10 in the vicinity of the insulating film 4 is depleted in the reverse bias applied state.

Description

本発明は、半導体装置に関する。   The present invention relates to a semiconductor device.

従来、いわゆるＭＯＳ（Ｍｅｔａｌ−Ｏｘｉｄｅ−Ｓｅｍｉｃｏｎｄｕｃｔｏｒ）構造を有する半導体装置が知られている。このＭＯＳ構造を有する半導体装置（以下「ＭＯＳ型半導体装置」という。）には、例えば、ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）や、ＭＯＳＦＥＴ（ＭＯＳ Ｆｉｅｌｄ Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒ）がある。   Conventionally, a semiconductor device having a so-called MOS (Metal-Oxide-Semiconductor) structure is known. Examples of the semiconductor device having the MOS structure (hereinafter referred to as “MOS type semiconductor device”) include an IGBT (Insulated Gate Bipolar Transistor) and a MOSFET (MOS Field Effect Transistor).

従来、ＭＯＳ型半導体装置では過電圧保護対策として、直列接続されたツェナーダイオードが設けられる。具体的には、ＭＯＳ型半導体装置の耐圧よりも低い電圧でブレークダウンするように設計されたツェナーダイオードをコレクタ−ゲート間に設けている（例えば特許文献１参照）。   Conventionally, in a MOS type semiconductor device, a Zener diode connected in series is provided as an overvoltage protection measure. Specifically, a Zener diode designed to break down at a voltage lower than the breakdown voltage of the MOS type semiconductor device is provided between the collector and the gate (see, for example, Patent Document 1).

ＭＯＳ型半導体装置では、耐圧を確保するために半導体基板の周縁部に耐圧領域を設け、この耐圧領域に沿って導体部（フィールドプレートとも呼ばれる。）を形成する。この導体部は、半導体基板上に形成された絶縁膜の上に設けられる。これにより、耐圧領域の表面電位を安定化させて半導体装置の信頼性を向上させている。   In the MOS type semiconductor device, a withstand voltage region is provided in the peripheral portion of the semiconductor substrate in order to ensure a withstand voltage, and a conductor portion (also referred to as a field plate) is formed along the withstand voltage region. This conductor portion is provided on an insulating film formed on the semiconductor substrate. This stabilizes the surface potential of the withstand voltage region and improves the reliability of the semiconductor device.

特開２００９−１１１３０４号公報JP 2009-111304 A

ところで、上記の半導体装置において、導体部と半導体基板との間に介在するシリコン酸化膜等の絶縁膜中には、Ｎａイオン等の可動イオンが含まれる。このため、例えばＩＧＢＴのコレクタ電極を高電位に接続し且つエミッタ電極を接地した場合、絶縁膜中の可動イオンが移動することによって、半導体装置の耐圧が局所的に低下するおそれがあった。   By the way, in the semiconductor device described above, movable ions such as Na ions are contained in an insulating film such as a silicon oxide film interposed between the conductor portion and the semiconductor substrate. For this reason, for example, when the collector electrode of the IGBT is connected to a high potential and the emitter electrode is grounded, there is a possibility that the withstand voltage of the semiconductor device may locally decrease due to the movement of movable ions in the insulating film.

そこで、本発明は、耐圧の低下を抑制し、信頼性を向上させることが可能な半導体装置を提供することを目的とする。   In view of the above, an object of the present invention is to provide a semiconductor device capable of suppressing a decrease in breakdown voltage and improving reliability.

本発明に係る半導体装置は、
半導体基板の一方の主面と他方の主面との間に主電流が流れる半導体装置であって、
前記半導体基板の前記一方の主面には、活性領域と、前記活性領域を取り囲み、前記半導体基板の周縁部を含む耐圧領域とが設けられ、
前記半導体装置は、
前記耐圧領域の前記一方の主面に選択的に形成され、前記活性領域を取り囲む第２導電型の拡散層と、
前記拡散層上、および当該拡散層の外側に位置する第１導電型の周辺半導体領域上に形成された絶縁膜と、
前記活性領域側から前記半導体基板の周縁部へ向かって前記絶縁膜上に交互に隣接配置された第１導電型の半導体層と第２導電型の半導体層とを有する過電圧保護ダイオードと、
前記絶縁膜上に前記耐圧領域に沿って形成された第１の導体部および第２の導体部と、を備え、
前記第１の導体部は、前記絶縁膜を介して前記拡散層の上方に配置され、前記第２の導体部は、前記絶縁膜を介して前記周辺半導体領域の上方に配置されており、
逆バイアス印加状態において前記絶縁膜近傍の前記拡散層が空乏化するように前記第１の導体部の端部が前記過電圧保護ダイオードに電気的に接続され、および／または、前記逆バイアス印加状態において前記絶縁膜近傍の前記周辺半導体領域が空乏化するように前記第２の導体部の端部が前記過電圧保護ダイオードに電気的に接続されていることを特徴とする。A semiconductor device according to the present invention includes:
A semiconductor device in which a main current flows between one main surface and the other main surface of a semiconductor substrate,
The one main surface of the semiconductor substrate is provided with an active region and a breakdown voltage region that surrounds the active region and includes a peripheral portion of the semiconductor substrate,
The semiconductor device includes:
A second conductivity type diffusion layer selectively formed on the one main surface of the breakdown voltage region and surrounding the active region;
An insulating film formed on the diffusion layer and on the peripheral semiconductor region of the first conductivity type located outside the diffusion layer;
An overvoltage protection diode having a first conductive type semiconductor layer and a second conductive type semiconductor layer alternately disposed adjacent to each other on the insulating film from the active region side toward a peripheral edge of the semiconductor substrate;
A first conductor portion and a second conductor portion formed on the insulating film along the withstand voltage region;
The first conductor portion is disposed above the diffusion layer via the insulating film, and the second conductor portion is disposed above the peripheral semiconductor region via the insulating film,
The end portion of the first conductor portion is electrically connected to the overvoltage protection diode so that the diffusion layer in the vicinity of the insulating film is depleted in the reverse bias applied state, and / or in the reverse bias applied state. An end portion of the second conductor portion is electrically connected to the overvoltage protection diode so that the peripheral semiconductor region in the vicinity of the insulating film is depleted.

また、前記半導体装置において、
前記第１導電型がＮ型であり、前記第２導電型がＰ型であり、
前記第１の導体部の端部は、前記逆バイアス印加状態において前記第１の導体部の電位が自身の直下における前記拡散層の電位よりも高くなるように前記過電圧保護ダイオードの側面の第１の部位に電気的に接続され、
前記第２の導体部の端部は、前記逆バイアス印加状態において前記第２の導体部の電位が自身の直下における前記周辺半導体領域の電位よりも低くなるように前記過電圧保護ダイオードの前記側面の第２の部位に電気的に接続されているようにしてもよい。In the semiconductor device,
The first conductivity type is N-type, the second conductivity type is P-type,
The end portion of the first conductor portion is a first side surface of the overvoltage protection diode so that the potential of the first conductor portion is higher than the potential of the diffusion layer immediately below the first conductor portion when the reverse bias is applied. Is electrically connected to
The end portion of the second conductor portion is formed on the side surface of the overvoltage protection diode so that the potential of the second conductor portion is lower than the potential of the peripheral semiconductor region immediately below the second conductor portion when the reverse bias is applied. It may be electrically connected to the second part.

また、前記半導体装置において、
前記第１の導体部は、
前記半導体基板の周縁部に沿って延在する第１の導体構成部と、
前記第１の導体構成部に一端が接続され、前記過電圧保護ダイオードの近傍まで延在する第２の導体構成部と、
前記第２の導体構成部と前記過電圧保護ダイオードを電気的に接続する第３の導体構成部と、を有し、
前記第２の導体構成部は、前記第１の導体構成部よりも幅広に形成され、
前記第３の導体構成部は、前記第２の導体構成部の他端の幅よりも幅狭に形成され、かつ前記半導体基板の側端側に寄るように設けられているようにしてもよい。In the semiconductor device,
The first conductor portion is
A first conductor component extending along a peripheral edge of the semiconductor substrate;
A second conductor component having one end connected to the first conductor component and extending to the vicinity of the overvoltage protection diode;
A second conductor component that electrically connects the second conductor component and the overvoltage protection diode;
The second conductor component is formed wider than the first conductor component,
The third conductor constituent part may be formed narrower than the width of the other end of the second conductor constituent part and provided so as to approach the side end side of the semiconductor substrate. .

また、前記半導体装置において、
前記第２の導体部は、
前記半導体基板の周縁部に沿って延在する第１の導体構成部と、
前記第１の導体構成部に一端が接続され、前記過電圧保護ダイオードの近傍まで延在する第２の導体構成部と、
前記第２の導体構成部と前記過電圧保護ダイオードを電気的に接続する第３の導体構成部と、を有し、
前記第２の導体構成部は、前記第１の導体構成部よりも幅広に形成され、
前記第３の導体構成部は、前記第２の導体構成部の他端の幅よりも幅狭に形成され、かつ前記活性領域側に寄るように設けられているようにしてもよい。In the semiconductor device,
The second conductor portion is
A first conductor component extending along a peripheral edge of the semiconductor substrate;
A second conductor component having one end connected to the first conductor component and extending to the vicinity of the overvoltage protection diode;
A second conductor component that electrically connects the second conductor component and the overvoltage protection diode;
The second conductor component is formed wider than the first conductor component,
The third conductor constituent portion may be formed narrower than the other end of the second conductor constituent portion and provided so as to be closer to the active region side.

また、前記半導体装置において、
前記第２の導体構成部は、前記過電圧保護ダイオードに近づくにつれて太くなるようにしてもよい。In the semiconductor device,
The second conductor component may become thicker as it approaches the overvoltage protection diode.

また、前記半導体装置において、
前記第１導電型がＰ型であり、前記第２導電型がＮ型であり、
前記第１の導体部の端部は、前記逆バイアス印加状態において前記第１の導体部の電位が自身の直下における前記拡散層の電位よりも低くなるように前記過電圧保護ダイオードの側面の第１の部位に電気的に接続され、
前記第２の導体部の端部は、前記逆バイアス印加状態において前記第２の導体部の電位が自身の直下における前記周辺半導体領域の電位よりも高くなるように前記過電圧保護ダイオードの前記側面の第２の部位に電気的に接続されているようにしてもよい。In the semiconductor device,
The first conductivity type is P-type, the second conductivity type is N-type,
The end portion of the first conductor portion is a first side surface of the overvoltage protection diode so that the potential of the first conductor portion is lower than the potential of the diffusion layer immediately below the first conductor portion when the reverse bias is applied. Is electrically connected to
The end portion of the second conductor portion is formed on the side surface of the overvoltage protection diode so that the potential of the second conductor portion is higher than the potential of the peripheral semiconductor region immediately below the second conductor portion when the reverse bias is applied. It may be electrically connected to the second part.

また、前記半導体装置において、
前記第１の導体部は、
前記半導体基板の周縁部に沿って延在する第１の導体構成部と、
前記第１の導体構成部に一端が接続され、前記過電圧保護ダイオードの近傍まで延在する第２の導体構成部と、
前記第２の導体構成部と前記過電圧保護ダイオードを電気的に接続する第３の導体構成部と、を有し、
前記第２の導体構成部は、前記第１の導体構成部よりも幅広に形成され、
前記第３の導体構成部は、前記第２の導体構成部の他端の幅よりも幅狭に形成され、かつ前記活性領域側に寄るように設けられているようにしてもよい。In the semiconductor device,
The first conductor portion is
A first conductor component extending along a peripheral edge of the semiconductor substrate;
A second conductor component having one end connected to the first conductor component and extending to the vicinity of the overvoltage protection diode;
A second conductor component that electrically connects the second conductor component and the overvoltage protection diode;
The second conductor component is formed wider than the first conductor component,
The third conductor constituent portion may be formed narrower than the other end of the second conductor constituent portion and provided so as to be closer to the active region side.

また、前記半導体装置において、
前記第２の導体部は、
前記半導体基板の周縁部に沿って延在する第１の導体構成部と、
前記第１の導体構成部に一端が接続され、前記過電圧保護ダイオードの近傍まで延在する第２の導体構成部と、
前記第２の導体構成部と前記過電圧保護ダイオードを電気的に接続する第３の導体構成部と、を有し、
前記第２の導体構成部は、前記第１の導体構成部よりも幅広に形成され、
前記第３の導体構成部は、前記第２の導体構成部の他端の幅よりも幅狭に形成され、かつ前記半導体基板の側端側に寄るように設けられているようにしてもよい。In the semiconductor device,
The second conductor portion is
A first conductor component extending along a peripheral edge of the semiconductor substrate;
A second conductor component having one end connected to the first conductor component and extending to the vicinity of the overvoltage protection diode;
A second conductor component that electrically connects the second conductor component and the overvoltage protection diode;
The second conductor component is formed wider than the first conductor component,
The third conductor constituent part may be formed narrower than the width of the other end of the second conductor constituent part and provided so as to approach the side end side of the semiconductor substrate. .

また、前記半導体装置において、
前記第２の導体構成部は、前記過電圧保護ダイオードに近づくにつれて太くなるようにしてもよい。In the semiconductor device,
The second conductor component may become thicker as it approaches the overvoltage protection diode.

また、前記半導体装置において、
前記半導体基板はシリコン基板であり、前記絶縁膜はシリコン酸化膜であるようにしてもよい。In the semiconductor device,
The semiconductor substrate may be a silicon substrate, and the insulating film may be a silicon oxide film.

また、前記半導体装置において、
前記第１の導体部および／または前記第２の導体部は、隣接する前記第１導電型の半導体層と前記第２導電型の半導体層の接合境界を跨ぐようにして前記過電圧保護ダイオードに接続されていてもよい。In the semiconductor device,
The first conductor portion and / or the second conductor portion is connected to the overvoltage protection diode so as to straddle a junction boundary between the adjacent first conductive type semiconductor layer and the second conductive type semiconductor layer. May be.

また、前記半導体装置において、
前記拡散層中に形成された第１導電型の拡散領域と、
前記拡散領域上に形成されたエミッタ電極と、
前記過電圧保護ダイオード上に形成されたゲート電極と、
前記半導体基板の前記他方の主面に形成された第２導電型のコレクタ領域と、
前記コレクタ領域上に形成されたコレクタ電極と、
をさらに備えてもよい。In the semiconductor device,
A diffusion region of a first conductivity type formed in the diffusion layer;
An emitter electrode formed on the diffusion region;
A gate electrode formed on the overvoltage protection diode;
A second conductivity type collector region formed on the other main surface of the semiconductor substrate;
A collector electrode formed on the collector region;
May be further provided.

また、前記半導体装置において、
前記拡散層中に形成された第１導電型の拡散領域と、
前記拡散領域上に形成されたエミッタ電極と、
前記過電圧保護ダイオード上に形成されたゲート電極と、
前記半導体基板の前記他方の主面に形成された第１導電型のドレイン領域と、
前記ドレイン領域上に形成され、前記ドレイン領域とショットキー障壁を形成するコレクタ電極と、
をさらに備えることを特徴とする請求項１〜１０のいずれかに記載の半導体装置。In the semiconductor device,
A diffusion region of a first conductivity type formed in the diffusion layer;
An emitter electrode formed on the diffusion region;
A gate electrode formed on the overvoltage protection diode;
A drain region of a first conductivity type formed on the other main surface of the semiconductor substrate;
A collector electrode formed on the drain region and forming a Schottky barrier with the drain region;
The semiconductor device according to claim 1, further comprising:

また、前記半導体装置において、
前記拡散層中に形成された第１導電型の拡散領域と、
前記拡散領域上に形成されたソース電極と、
前記過電圧保護ダイオード上に形成されたゲート電極と、
前記半導体基板の前記他方の主面に形成された第１導電型のドレイン領域と、
前記ドレイン領域上に形成されたドレイン電極と、
をさらに備えてもよい。In the semiconductor device,
A diffusion region of a first conductivity type formed in the diffusion layer;
A source electrode formed on the diffusion region;
A gate electrode formed on the overvoltage protection diode;
A drain region of a first conductivity type formed on the other main surface of the semiconductor substrate;
A drain electrode formed on the drain region;
May be further provided.

また、前記半導体装置において、
前記耐圧領域の前記一方の主面に選択的に形成され、前記拡散層を取り囲む１本または複数本の第２導電型のガードリングをさらに備えてもよい。In the semiconductor device,
One or a plurality of second-conductivity type guard rings that are selectively formed on the one main surface of the breakdown voltage region and surround the diffusion layer may be further provided.

本発明では、逆バイアス印加状態において絶縁膜近傍の拡散層が空乏化するように第１の導体部の端部が過電圧保護ダイオードの側面に電気的に接続され、および／または、逆バイアス印加状態において絶縁膜近傍の周辺半導体領域が空乏化するように第２の導体部の端部が過電圧保護ダイオードの側面に電気的に接続されている。これにより、逆バイアス印加時においては、空乏化した半導体領域の不純物の電荷によって上記絶縁膜中に分極電荷が生じる。この分極電荷に、絶縁膜中の可動イオンがトラップされるため、可動イオンの移動が抑制されることになる。よって、本発明によれば、逆バイアス印加時における耐圧の低下を抑制し、信頼性を向上させることができる。   In the present invention, the end portion of the first conductor portion is electrically connected to the side surface of the overvoltage protection diode so that the diffusion layer near the insulating film is depleted in the reverse bias application state, and / or the reverse bias application state. In FIG. 2, the end portion of the second conductor portion is electrically connected to the side surface of the overvoltage protection diode so that the peripheral semiconductor region in the vicinity of the insulating film is depleted. As a result, when a reverse bias is applied, polarization charges are generated in the insulating film by charges of impurities in the depleted semiconductor region. Since the movable ions in the insulating film are trapped by this polarization charge, the movement of the movable ions is suppressed. Therefore, according to the present invention, it is possible to suppress a decrease in breakdown voltage during reverse bias application and improve reliability.

第１の実施形態に係る半導体装置１（ＩＧＢＴ）の平面図である。1 is a plan view of a semiconductor device 1 (IGBT) according to a first embodiment. 図１のＩ−Ｉ線に沿う断面図である。It is sectional drawing which follows the II line | wire of FIG. 図１のＩＩ−ＩＩ線に沿う断面図である。It is sectional drawing which follows the II-II line | wire of FIG. 導体部６，７，８，９と過電圧保護ダイオード５との間の接続領域を拡大した平面模式図である。3 is a schematic plan view in which a connection region between conductor portions 6, 7, 8, 9 and an overvoltage protection diode 5 is enlarged. FIG. 逆バイアス印加状態における各領域の電位の一例を示す図である。It is a figure which shows an example of the electric potential of each area | region in a reverse bias application state. 実施形態に係る導体部３１〜３５と過電圧保護ダイオード５の一部を示す平面図である。It is a top view which shows a part of conductor parts 31-35 and the overvoltage protection diode 5 which concern on embodiment. 図６Ａの領域Ｒを拡大した平面図である。It is the top view to which the area | region R of FIG. 6A was expanded. ２本のガードリング２５が設けられた半導体装置１の断面図である。1 is a cross-sectional view of a semiconductor device 1 provided with two guard rings 25. FIG. 拡散層３の導電型がＮ型、周辺半導体領域１０の導電型がＰ型になった場合における、逆バイアス印加状態における各領域の電位の一例を示す図である。It is a figure which shows an example of the electric potential of each area | region in a reverse bias application state when the conductivity type of the diffused layer 3 becomes N type and the conductivity type of the peripheral semiconductor region 10 becomes P type. 第２の実施形態に係る半導体装置１Ａ（縦型ＭＯＳＦＥＴ）の断面図である。FIG. 6 is a cross-sectional view of a semiconductor device 1A (vertical MOSFET) according to a second embodiment. 第１の実施形態の変形例に係る半導体装置１Ｂ（ＩＧＢＴ）の断面図である。It is sectional drawing of the semiconductor device 1B (IGBT) which concerns on the modification of 1st Embodiment.

以下、図面を参照しつつ本発明の実施形態に係る半導体装置について説明する。   A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings.

（第１の実施形態）
本発明の第１の実施形態について説明する。第１の実施形態に係る半導体装置１は、ＩＧＢＴである。(First embodiment)
A first embodiment of the present invention will be described. The semiconductor device 1 according to the first embodiment is an IGBT.

半導体装置１では、半導体基板２の上面２ａ（一方の主面）と下面２ｂ（他方の主面）との間に主電流が流れる。なお、半導体基板２は、本実施形態ではシリコン基板である。ただし、本発明はこれに限るものではなく、その他の半導体基板（例えばＳｉＣ基板、ＧａＮ基板等）であってもよい。また、半導体基板２の導電型は、本実施形態ではＮ型であるが、これに限定されない。   In the semiconductor device 1, a main current flows between the upper surface 2 a (one main surface) and the lower surface 2 b (the other main surface) of the semiconductor substrate 2. The semiconductor substrate 2 is a silicon substrate in this embodiment. However, the present invention is not limited to this, and other semiconductor substrates (for example, SiC substrates, GaN substrates, etc.) may be used. Moreover, although the conductivity type of the semiconductor substrate 2 is N type in this embodiment, it is not limited to this.

図１に示すように、半導体基板２の上面２ａには、主電流が流れる活性領域Ａと、この活性領域Ａを取り囲む耐圧領域Ｂとが設けられている。耐圧領域Ｂは、半導体基板２の周縁部を含む。ここで、「周縁部」とは、半導体基板２の側面を含む、半導体基板２の周縁の部分のことである。なお、図１では、絶縁膜１５、表面保護膜１６、エミッタ電極２１、ゲート電極２２、ストッパ電極２４は図示していない。   As shown in FIG. 1, an active region A in which a main current flows and a breakdown voltage region B surrounding the active region A are provided on the upper surface 2 a of the semiconductor substrate 2. The breakdown voltage region B includes the peripheral edge of the semiconductor substrate 2. Here, the “peripheral portion” is a peripheral portion of the semiconductor substrate 2 including the side surface of the semiconductor substrate 2. In FIG. 1, the insulating film 15, the surface protective film 16, the emitter electrode 21, the gate electrode 22, and the stopper electrode 24 are not shown.

図１〜図３に示すように、半導体装置１は、Ｐ型の拡散層３と、絶縁膜４と、過電圧保護ダイオード５と、導体部６，７，８，９と、Ｐ型のコレクタ領域１２と、Ｎ型の拡散領域１３と、Ｎ型のストッパ領域１４と、エミッタ電極２１と、ゲート電極２２と、コレクタ電極２３と、ストッパ電極２４とを備えている。なお、半導体基板２の上面２ａには、ゲートパット（図示せず）が設けられる。   As shown in FIGS. 1 to 3, the semiconductor device 1 includes a P-type diffusion layer 3, an insulating film 4, an overvoltage protection diode 5, conductor portions 6, 7, 8 and 9, and a P-type collector region. 12, an N type diffusion region 13, an N type stopper region 14, an emitter electrode 21, a gate electrode 22, a collector electrode 23, and a stopper electrode 24. A gate pad (not shown) is provided on the upper surface 2 a of the semiconductor substrate 2.

拡散層３は、耐圧領域Ｂの上面２ａに選択的に形成されており、活性領域Ａを取り囲んでいる。この拡散層３は、ｐ型ベース領域とも呼ばれる。なお、図１の境界Ｐ１とＰ２で囲まれた領域がｐ型ベース領域である。境界Ｐ２が活性領域Ａと耐圧領域Ｂの境界となっている。なお、拡散層３の深さは、例えば２μｍ〜１０μｍである。拡散層３の不純物濃度は、例えば１×１０１４ｃｍ−３〜１×１０１６ｃｍ−３である。The diffusion layer 3 is selectively formed on the upper surface 2 a of the breakdown voltage region B and surrounds the active region A. This diffusion layer 3 is also called a p-type base region. Note that a region surrounded by the boundaries P1 and P2 in FIG. 1 is a p-type base region. The boundary P2 is the boundary between the active region A and the withstand voltage region B. The depth of the diffusion layer 3 is, for example, 2 μm to 10 μm. The impurity concentration of the diffusion layer 3 is, for example, 1 × 10 14 cm −3 to 1 × 10 16 cm −3 .

絶縁膜４は、図２に示すように、拡散層３上、および周辺半導体領域１０上に形成されている。ここで、周辺半導体領域１０は、拡散層３の外側に位置するＮ型の半導体領域である。この周辺半導体領域１０の不純物濃度は、例えば１×１０１３ｃｍ−３〜１×１０１５ｃｍ−３である。As shown in FIG. 2, the insulating film 4 is formed on the diffusion layer 3 and the peripheral semiconductor region 10. Here, the peripheral semiconductor region 10 is an N-type semiconductor region located outside the diffusion layer 3. The impurity concentration of the peripheral semiconductor region 10 is, for example, 1 × 10 13 cm −3 to 1 × 10 15 cm −3 .

絶縁膜４は、例えばフィールド酸化膜である。本実施形態では、絶縁膜４は、シリコン酸化膜（ＳｉＯ２膜）である。絶縁膜４の厚さは、例えば２００ｎｍ〜２０００ｎｍである。The insulating film 4 is a field oxide film, for example. In the present embodiment, the insulating film 4 is a silicon oxide film (SiO 2 film). The thickness of the insulating film 4 is, for example, 200 nm to 2000 nm.

過電圧保護ダイオード５は、活性領域Ａ側から半導体基板２の周縁部へ向かって絶縁膜４上に交互に隣接配置されたＮ型の半導体層５ａとＰ型の半導体層５ｂとを有する。この過電圧保護ダイオード５は、複数のツェナーダイオードが直列接続されたものである。   The overvoltage protection diode 5 includes N-type semiconductor layers 5a and P-type semiconductor layers 5b that are alternately disposed adjacently on the insulating film 4 from the active region A side toward the peripheral edge of the semiconductor substrate 2. The overvoltage protection diode 5 is formed by connecting a plurality of Zener diodes in series.

拡散領域１３は、拡散層３中に形成されたＮ型の半導体領域である。図２に示すように、この拡散領域１３上にエミッタ電極２１が形成されている。なお、拡散領域１３の不純物濃度は、例えば１×１０１９ｃｍ−３〜１×１０２１ｃｍ−３である。The diffusion region 13 is an N-type semiconductor region formed in the diffusion layer 3. As shown in FIG. 2, an emitter electrode 21 is formed on the diffusion region 13. The impurity concentration of the diffusion region 13 is, for example, 1 × 10 19 cm −3 to 1 × 10 21 cm −3 .

Ｎ型のストッパ領域１４は、半導体基板２の側端における上面２ａに形成されている。ストッパ領域１４の不純物濃度は周辺半導体領域１０よりも高い。ストッパ領域１４上に、ストッパ電極２４が形成されている。このストッパ電極２４は、過電圧保護ダイオード５の他端に電気的に接続されている。   The N-type stopper region 14 is formed on the upper surface 2 a at the side end of the semiconductor substrate 2. The impurity concentration of the stopper region 14 is higher than that of the peripheral semiconductor region 10. A stopper electrode 24 is formed on the stopper region 14. The stopper electrode 24 is electrically connected to the other end of the overvoltage protection diode 5.

ゲート電極２２は、絶縁膜４を介して拡散層３の上方に設けられている。このゲート電極２２は、本実施形態では、過電圧保護ダイオード５上に形成されている。より詳しくは、図２に示すように、ゲート電極２２は過電圧保護ダイオード５の活性領域Ａ側の一端に電気的に接続されている。   The gate electrode 22 is provided above the diffusion layer 3 with the insulating film 4 interposed therebetween. The gate electrode 22 is formed on the overvoltage protection diode 5 in this embodiment. More specifically, as shown in FIG. 2, the gate electrode 22 is electrically connected to one end of the overvoltage protection diode 5 on the active region A side.

Ｐ型のコレクタ領域１２は、半導体基板２の下面２ｂに形成されている。このコレクタ領域１２の不純物濃度は、例えば１×１０１７ｃｍ−３〜１×１０１９ｃｍ−３である。図２に示すように、コレクタ領域１２上にコレクタ電極２３が形成されている。なお、コレクタ領域１２の上にＮ型のバッファ領域１１が設けられてもよい。このバッファ領域１１の不純物濃度は、例えば１×１０１６ｃｍ−３〜１×１０１８ｃｍ−３である。The P-type collector region 12 is formed on the lower surface 2 b of the semiconductor substrate 2. The impurity concentration of the collector region 12 is, for example, 1 × 10 17 cm −3 to 1 × 10 19 cm −3 . As shown in FIG. 2, a collector electrode 23 is formed on the collector region 12. Note that an N-type buffer region 11 may be provided on the collector region 12. The impurity concentration of the buffer region 11 is, for example, 1 × 10 16 cm −3 to 1 × 10 18 cm −3 .

また、図１および図２に示すように、半導体装置１は、過電圧保護ダイオード５を被覆する絶縁膜１５と、半導体装置１の上面２ａ側全体を被覆する表面保護膜１６とをさらに備えている。絶縁膜１５は、例えばＢＰＳＧ（Ｂｏｒｏｎ Ｐｈｏｓｐｈｏｒｏｕｓ Ｓｉｌｉｃａｔｅ Ｇｌａｓｓ）膜である。表面保護膜１６は、図２に示すように、半導体基板２の上面２ａ側全体を被覆している。表面保護膜１６は、例えばポリイミド膜である。   As shown in FIGS. 1 and 2, the semiconductor device 1 further includes an insulating film 15 that covers the overvoltage protection diode 5 and a surface protective film 16 that covers the entire upper surface 2 a side of the semiconductor device 1. . The insulating film 15 is, for example, a BPSG (Boron Phosphorous Silicate Glass) film. As shown in FIG. 2, the surface protective film 16 covers the entire upper surface 2 a side of the semiconductor substrate 2. The surface protective film 16 is a polyimide film, for example.

次に、耐圧領域Ｂに設けられた導体部６，７，８，９について詳しく説明する。   Next, the conductor parts 6, 7, 8, and 9 provided in the withstand voltage region B will be described in detail.

図１に示すように、導体部６，７（第１の導体部）および導体部８，９（第２の導体部）は、絶縁膜４上に耐圧領域Ｂに沿って形成されている。導体部６，７，８，９（より正確には、導体構成部６ａ，７ａ，８ａ，９ａ）は、互いに平行に形成されている。導体部６，７，８，９は、例えばポリシリコンまたはアルミニウム等から構成される。なお、導体部の本数は４本に限るものではない。   As shown in FIG. 1, the conductor portions 6 and 7 (first conductor portion) and the conductor portions 8 and 9 (second conductor portion) are formed on the insulating film 4 along the breakdown voltage region B. The conductor portions 6, 7, 8, 9 (more precisely, the conductor constituent portions 6a, 7a, 8a, 9a) are formed in parallel to each other. The conductor parts 6, 7, 8, 9 are made of, for example, polysilicon or aluminum. Note that the number of conductor portions is not limited to four.

図３に示すように、導体部６，７は、絶縁膜４を介して拡散層３の上方に配置されており、導体部８，９は、絶縁膜４を介して周辺半導体領域１０の上方に配置されている。   As shown in FIG. 3, the conductor portions 6 and 7 are disposed above the diffusion layer 3 via the insulating film 4, and the conductor portions 8 and 9 are located above the peripheral semiconductor region 10 via the insulating film 4. Is arranged.

図４に示すように、導体部６，７，８，９は、導体構成部６ａ，７ａ，８ａ，９ａ（第１の導体構成部）と、導体構成部６ｂ，７ｂ，８ｂ，９ｂ（第２の導体構成部）と、導体構成部６ｃ，７ｃ，８ｃ，９ｃ（第３の導体構成部）とを有している。なお、図４は、導体部６，７，８，９の概略構成を説明するための模式図であり、図１の平面図と対応するものではない。   As shown in FIG. 4, the conductor parts 6, 7, 8, and 9 are composed of conductor constituent parts 6a, 7a, 8a, and 9a (first conductor constituent parts) and conductor constituent parts 6b, 7b, 8b, and 9b (first conductor constituent parts). 2 conductor constituent parts) and conductor constituent parts 6c, 7c, 8c, 9c (third conductor constituent parts). 4 is a schematic diagram for explaining a schematic configuration of the conductor portions 6, 7, 8, and 9, and does not correspond to the plan view of FIG.

導体構成部６ａ，７ａ，８ａ，９ａは、導体部６，７，８，９のうち、半導体基板２の周縁部（側端）に沿って延在する部分である。導体構成部６ｂ，７ｂ，８ｂ，９ｂは、導体構成部６ａ，７ａ，８ａ，９ａに一端が接続され、過電圧保護ダイオード５の近傍まで延在している。導体構成部６ｃ，７ｃ，８ｃ，９ｃは、導体構成部６ｂ，７ｂ，８ｂ，９ｂと過電圧保護ダイオード５を電気的に接続する。   The conductor constituent portions 6 a, 7 a, 8 a, and 9 a are portions extending along the peripheral edge (side end) of the semiconductor substrate 2 among the conductor portions 6, 7, 8, and 9. The conductor constituent parts 6b, 7b, 8b, 9b are connected at one end to the conductor constituent parts 6a, 7a, 8a, 9a and extend to the vicinity of the overvoltage protection diode 5. The conductor constituent parts 6c, 7c, 8c, 9c electrically connect the conductor constituent parts 6b, 7b, 8b, 9b and the overvoltage protection diode 5.

図４に示すように、導体構成部６ｂ，７ｂ，８ｂ，９ｂは、導体構成部６ａ，７ａ，８ａ，９ａよりも幅広に形成されている。また、導体構成部６ｃ，７ｃ，８ｃ，９ｃは、導体構成部６ｂ，７ｂ，８ｂ，９ｂの他端（過電圧保護ダイオード５側の端部）の幅よりも幅狭に形成されている。そして、導体構成部６ｃ，７ｃ，８ｃ，９ｃは、拡散層３と周辺半導体領域１０間のｐｎ接合境界Ｐ１側に寄るように設けられている。すなわち、図４において、導体構成部６ｃ、７ｃは右側に寄るように設けられ、導体構成部８ｃ，９ｃは左側に寄るように設けられている。より一般的には、導体構成部６ｃ，７ｃは半導体基板２の側端側（高電位側）に寄るように設けられ、導体構成部８ｃ，９ｃは、半導体基板２の活性領域Ａ側（低電位側）に寄るように設けられている。   As shown in FIG. 4, the conductor constituent portions 6b, 7b, 8b, 9b are formed wider than the conductor constituent portions 6a, 7a, 8a, 9a. The conductor constituent parts 6c, 7c, 8c, 9c are formed to be narrower than the width of the other end (end part on the overvoltage protection diode 5 side) of the conductor constituent parts 6b, 7b, 8b, 9b. The conductor constituent portions 6 c, 7 c, 8 c, and 9 c are provided so as to approach the pn junction boundary P 1 side between the diffusion layer 3 and the peripheral semiconductor region 10. That is, in FIG. 4, the conductor constituent parts 6c and 7c are provided so as to approach the right side, and the conductor constituent parts 8c and 9c are provided so as to approach the left side. More generally, the conductor constituent portions 6c and 7c are provided so as to approach the side end side (high potential side) of the semiconductor substrate 2, and the conductor constituent portions 8c and 9c are provided on the active region A side (low side) of the semiconductor substrate 2. (Potential side).

次に、図５を参照して、上記半導体装置１の逆バイアス印加状態における各領域の電位について具体的に説明する。ここで、「逆バイアス印加状態」は、第１の実施形態では、コレクタ電極２３が高電位（例えば直流電源の正極）に接続され、エミッタ電極２１が接地され、ゲート電極２２にＩＧＢＴがオンしない程度の低電圧が印加された状態のことである。また、図５中の数値は、コレクタ電極２３に４００Ｖの高電位を接続し、エミッタ電極２１を接地し、ゲート電極２２に１０〜２０ＶのＯＦＦ電圧を印加した場合の例を示している。   Next, with reference to FIG. 5, the potential of each region in the reverse bias application state of the semiconductor device 1 will be specifically described. Here, in the “reverse bias applied state”, in the first embodiment, the collector electrode 23 is connected to a high potential (for example, the positive electrode of the DC power supply), the emitter electrode 21 is grounded, and the IGBT is not turned on to the gate electrode 22. This is a state in which a low voltage of about a level is applied. The numerical values in FIG. 5 show an example in which a high potential of 400 V is connected to the collector electrode 23, the emitter electrode 21 is grounded, and an OFF voltage of 10 to 20 V is applied to the gate electrode 22.

逆バイアス印加状態において、図５に示すように、絶縁膜４近傍の拡散層３が空乏化するように、導体部６，７の端部は過電圧保護ダイオード５の側面に電気的に接続されている。より具体的には、逆バイアス印加状態において導体部６，７の電位が自身の直下における拡散層３の電位よりも高くなるように、導体部６，７の端部は過電圧保護ダイオード５の側面の第１の部位に電気的に接続されている。これは、導体構成部６ｃ、７ｃがｐｎ接合境界Ｐ１側（すなわち、高電位側）に寄るように設けられていることに対応する。   In the reverse bias applied state, as shown in FIG. 5, the end portions of the conductor portions 6 and 7 are electrically connected to the side surface of the overvoltage protection diode 5 so that the diffusion layer 3 in the vicinity of the insulating film 4 is depleted. Yes. More specifically, the end portions of the conductor portions 6 and 7 are side surfaces of the overvoltage protection diode 5 so that the potentials of the conductor portions 6 and 7 are higher than the potential of the diffusion layer 3 immediately below the reverse bias application state. Is electrically connected to the first portion of the. This corresponds to the conductor constituent portions 6c and 7c being provided so as to approach the pn junction boundary P1 side (that is, the high potential side).

同様に、逆バイアス印加状態において絶縁膜４近傍の周辺半導体領域１０が空乏化するように、導体部８，９の端部は過電圧保護ダイオード５の側面に電気的に接続されている。より具体的には、逆バイアス印加状態において導体部８，９の電位が自身の直下における周辺半導体領域１０の電位よりも低くなるように、導体部８，９の端部は過電圧保護ダイオード５の当該側面の第２の部位に電気的に接続されている。これは、導体構成部８ｃ、９ｃがｐｎ接合境界Ｐ１側（すなわち、低電位側）に寄るように設けられていることに対応する。   Similarly, the end portions of the conductor portions 8 and 9 are electrically connected to the side surface of the overvoltage protection diode 5 so that the peripheral semiconductor region 10 near the insulating film 4 is depleted in the reverse bias applied state. More specifically, the end portions of the conductor portions 8 and 9 are connected to the overvoltage protection diode 5 so that the potentials of the conductor portions 8 and 9 are lower than the potential of the peripheral semiconductor region 10 immediately under the reverse bias applied state. It is electrically connected to the second part of the side surface. This corresponds to the conductor components 8c and 9c being provided so as to be closer to the pn junction boundary P1 side (that is, the low potential side).

上記のように導体部６，７，８，９の端部が過電圧保護ダイオード５に接続されることにより、図５のように絶縁膜４の近傍に空乏領域が発生する。   By connecting the end portions of the conductor portions 6, 7, 8, 9 to the overvoltage protection diode 5 as described above, a depletion region is generated in the vicinity of the insulating film 4 as shown in FIG.

すなわち、導体構成部６ａの電位（１２５Ｖ）は、導体構成部６ａの直下における拡散層３の電位（１００Ｖ）より高いため、絶縁膜４近傍におけるＰ型の拡散層３が空乏化する。同様に、導体構成部７ａの電位（２２５Ｖ）は、導体構成部７ａの直下における拡散層３の電位（２００Ｖ）より高いため、絶縁膜４近傍の拡散層３が空乏化する。そして、このように空乏化した半導体領域における不純物の電荷（すなわち、アクセプタの負電荷）によって、絶縁膜４中に正の分極電荷が生じる。   That is, since the potential (125V) of the conductor component 6a is higher than the potential (100V) of the diffusion layer 3 immediately below the conductor component 6a, the P-type diffusion layer 3 in the vicinity of the insulating film 4 is depleted. Similarly, since the potential (225V) of the conductor component 7a is higher than the potential (200V) of the diffusion layer 3 immediately below the conductor component 7a, the diffusion layer 3 near the insulating film 4 is depleted. Then, a positive polarization charge is generated in the insulating film 4 by the charge of the impurity in the semiconductor region thus depleted (that is, the negative charge of the acceptor).

導体構成部８ａの電位（２７５Ｖ）は、導体構成部８ａの直下における周辺半導体領域１０の電位（３００Ｖ）より低いため、絶縁膜４近傍におけるＮ型の周辺半導体領域１０が空乏化する。同様に、導体構成部９ａの電位（３７５Ｖ）は、導体構成部９ａの直下における周辺半導体領域１０の電位（４００Ｖ）より低いため、絶縁膜４近傍の周辺半導体領域１０が空乏化する。そして、このように空乏化した半導体領域における不純物の電荷（すなわち、ドナーの正電荷）によって、絶縁膜４中に負の分極電荷が生じる。   Since the potential (275V) of the conductor constituent portion 8a is lower than the potential (300V) of the peripheral semiconductor region 10 immediately below the conductor constituent portion 8a, the N-type peripheral semiconductor region 10 in the vicinity of the insulating film 4 is depleted. Similarly, since the potential (375 V) of the conductor component 9a is lower than the potential (400 V) of the peripheral semiconductor region 10 immediately below the conductor component 9a, the peripheral semiconductor region 10 near the insulating film 4 is depleted. Then, a negative polarization charge is generated in the insulating film 4 due to the charge of the impurity (that is, the positive charge of the donor) in the semiconductor region thus depleted.

上記のようにして絶縁膜４中に分極電荷が生じる。この分極電荷に、絶縁膜４中のＮａイオン等の可動イオンがトラップされるため、可動イオンの移動が抑制されることになる。これにより、本実施形態によれば、耐圧の低下を抑制し、信頼性を向上させることができる半導体装置１を提供することができる。   As described above, polarization charges are generated in the insulating film 4. Since the movable ions such as Na ions in the insulating film 4 are trapped by this polarization charge, the movement of the movable ions is suppressed. Thereby, according to this embodiment, the semiconductor device 1 which can suppress the fall of a pressure | voltage resistance and can improve reliability can be provided.

上記のように、導体部６，７は、導体構成部６ｂ，７ｂにより過電圧保護ダイオード５の高電位側（半導体基板２の側端側）に変位して接続され、導体部８，９は、導体構成部８ｂ，９ｂにより過電圧保護ダイオード５の低電位側（活性領域Ａ側）に変位して接続される。   As described above, the conductor parts 6 and 7 are displaced and connected to the high potential side (side end side of the semiconductor substrate 2) of the overvoltage protection diode 5 by the conductor constituent parts 6b and 7b, and the conductor parts 8 and 9 are The conductor components 8b and 9b are displaced and connected to the low potential side (active region A side) of the overvoltage protection diode 5.

なお、導体部６，７，８，９の全てが上記構成を有することは必須ではなく、必要に応じて導体部６，７，８，９のうち少なくともいずれか一つが上記構成を有するようにしてもよい。   Note that it is not essential that all of the conductor portions 6, 7, 8, 9 have the above-described configuration, and at least one of the conductor portions 6, 7, 8, 9 has the above-described configuration as necessary. May be.

また、導体部の形状について、図４で説明したものの他にも様々なものが想定可能である。例えば、図６Ａでは、５本の導体部、すなわち、導体部３１，３２，３３（第１の導体部）および導体部３４，３５（第２の導体部）が図示されている。これら導体部３１，３２，３３，３４，３５は、導体構成部３１ａ，３２ａ，３３ａ，３４ａ，３５ａ（第１の導体構成部）と、導体構成部３１ｂ，３２ｂ，３３ｂ，３４ｂ，３５ｂ（第２の導体構成部）と、導体構成部３１ｃ，３２ｃ，３３ｃ，３４ｃ，３５ｃ（第３の導体構成部）とを有する。   In addition to the shape described in FIG. 4, various shapes of the conductor portion can be assumed. For example, in FIG. 6A, five conductor portions, that is, conductor portions 31, 32, 33 (first conductor portion) and conductor portions 34, 35 (second conductor portion) are illustrated. The conductor portions 31, 32, 33, 34, and 35 are composed of the conductor constituent portions 31a, 32a, 33a, 34a, and 35a (first conductor constituent portions) and the conductor constituent portions 31b, 32b, 33b, 34b, and 35b (first portion). 2 conductor constituent parts) and conductor constituent parts 31c, 32c, 33c, 34c, 35c (third conductor constituent parts).

図６Ａに示すように、導体構成部３１ｂ，３２ｂ，３３ｂ，３４ｂ，３５ｂは、活性領域Ａに近づきつつ過電圧保護ダイオード５の近傍まで延在している。換言すれば、導体構成部３１ｂ，３２ｂ，３３ｂ，３４ｂ，３５ｂは、過電圧保護ダイオード５から遠ざかるにつれて半導体基板２の側端に寄るように設けられている。これにより、導体構成部３１ａ，３２ａ，３３ａ，３４ａ，３５ａ間の距離を短くして活性領域Ａの面積を広く確保しつつ、図５で説明したのと同様に、逆バイアス印加状態における空乏化領域を形成することができる。   As shown in FIG. 6A, the conductor constituent portions 31b, 32b, 33b, 34b, and 35b extend to the vicinity of the overvoltage protection diode 5 while approaching the active region A. In other words, the conductor constituent portions 31 b, 32 b, 33 b, 34 b, and 35 b are provided so as to approach the side end of the semiconductor substrate 2 as the distance from the overvoltage protection diode 5 increases. As a result, the distance between the conductor constituent portions 31a, 32a, 33a, 34a, and 35a is shortened to secure a large area of the active region A, and the depletion in the reverse bias applied state is performed as described with reference to FIG. Regions can be formed.

また、導体構成部３１ｂ，３２ｂ，３３ｂ，３４ｂ，３５ｂは、図６Ａに示すように、過電圧保護ダイオード５に近づくにつれて太くなるように形成されている。これにより、過電圧保護ダイオード５の延在方向（図６Ａの上下方向）に導体構成部３１ｃ，３２ｃ，３３ｃ，３４ｃ，３５ｃとの接続点から離れるにつれて、逆バイアス印加状態における電位差が大きくなる。電位差とは、導体部６，７の電位と直下の拡散層３の電位との差、あるいは、逆バイアス印加状態における導体部８，９の電位と直下の周辺半導体領域１０の電位との差のことである。   Further, the conductor constituent portions 31b, 32b, 33b, 34b, and 35b are formed so as to become thicker as they approach the overvoltage protection diode 5, as shown in FIG. 6A. As a result, the potential difference in the reverse bias applied state increases as the distance from the connection point with the conductor components 31c, 32c, 33c, 34c, and 35c increases in the extending direction of the overvoltage protection diode 5 (vertical direction in FIG. 6A). The potential difference is the difference between the potential of the conductor portions 6 and 7 and the potential of the diffusion layer 3 immediately below, or the difference between the potential of the conductor portions 8 and 9 and the potential of the peripheral semiconductor region 10 immediately below in the reverse bias applied state. That is.

例えば、図６Ｂにおいて、導体構成部３１ｂの端点Ｅ１における電位差は導体構成部３１ｃ側の端点Ｅ２における電位差よりも大きくなるため、絶縁膜４中に分極電荷が大きくなって可動イオンの移動をより効果的に抑制することができる。   For example, in FIG. 6B, since the potential difference at the end point E1 of the conductor constituting portion 31b is larger than the potential difference at the end point E2 on the conductor constituting portion 31c side, the polarization charge increases in the insulating film 4 and the movement of mobile ions becomes more effective. Can be suppressed.

図６Ａおよび図６Ｂに示すように、導体構成部３１ｃ〜３５ｃは、過電圧保護ダイオード５の半導体層５ａまたは半導体層５ｂに接続されている。例えば導体構成部３１ｃ〜３５ｃがポリシリコン等の半導体から構成される場合、導体構成部３１ｃ〜３５ｃは、半導体層５ａおよび半導体層５ｂのうち、自身の導電型と同じ導電型の半導体層に接続されている。また、導体構成部３１ｃ〜３５ｃは、互いに異なる導電型であってもよい。   As illustrated in FIGS. 6A and 6B, the conductor constituent portions 31 c to 35 c are connected to the semiconductor layer 5 a or the semiconductor layer 5 b of the overvoltage protection diode 5. For example, when the conductor constituent portions 31c to 35c are made of a semiconductor such as polysilicon, the conductor constituent portions 31c to 35c are connected to a semiconductor layer having the same conductivity type as that of the semiconductor layer 5a and the semiconductor layer 5b. Has been. Also, the conductor constituent portions 31c to 35c may have different conductivity types.

なお、導体部３１，３２，３３および／または導体部３４，３５は、隣接する半導体層５ａと半導体層５ｂの接合境界を跨ぐようにして過電圧保護ダイオード５に接続されてもよい。すなわち、導体部３１〜３５は、隣接する半導体層５ａと半導体層５ｂの両方に接続されてもよい。ここで、隣接する半導体層５ａと半導体層５ｂの接合境界を跨ぐとは、隣接する２つの半導体層を跨ぐ場合に限らず、隣接する３つ以上の半導体層（例えば、隣接する半導体層５ａ、半導体層５ｂおよび半導体層５ａ）を跨ぐ場合も含まれる。このように導体部３１〜３５は少なくとも一部分で自身の同じ導電型の半導体層に接続することで、導体部３１〜３５の下方に位置する半導体領域の表層部分を空乏化させることが可能である。   The conductor portions 31, 32, 33 and / or the conductor portions 34, 35 may be connected to the overvoltage protection diode 5 so as to straddle the junction boundary between the adjacent semiconductor layers 5a and 5b. That is, the conductor portions 31 to 35 may be connected to both the adjacent semiconductor layer 5a and the semiconductor layer 5b. Here, straddling the junction boundary between the adjacent semiconductor layers 5a and 5b is not limited to straddling two adjacent semiconductor layers, but three or more adjacent semiconductor layers (for example, adjacent semiconductor layers 5a, 5a, The case of straddling the semiconductor layer 5b and the semiconductor layer 5a) is also included. In this way, the conductor portions 31 to 35 are at least partially connected to the semiconductor layer of the same conductivity type, so that the surface layer portion of the semiconductor region located below the conductor portions 31 to 35 can be depleted. .

また、半導体装置１には、図７に示すように、高耐圧化のために、Ｐ型のガードリング２５が拡散層３を取り囲むように設けられていてもよい。このガードリング２５は、耐圧領域Ｂの上面２ａに選択的に形成されている。ガードリングの本数は、２本に限らず、１本または３本以上であってもよい。ガードリング２５の上方に導体部が配置される場合、当該導体部は過電圧保護ダイオード５のうち高電位側に変位した部位に電気的に接続される。   In addition, as shown in FIG. 7, a P-type guard ring 25 may be provided in the semiconductor device 1 so as to surround the diffusion layer 3 in order to increase the breakdown voltage. The guard ring 25 is selectively formed on the upper surface 2a of the breakdown voltage region B. The number of guard rings is not limited to two, and may be one or three or more. When the conductor portion is disposed above the guard ring 25, the conductor portion is electrically connected to a portion of the overvoltage protection diode 5 that is displaced to the high potential side.

また、半導体装置１の各半導体領域の導電型は上記したものと逆であってもよい。すなわち、拡散層３がＮ型、周辺半導体領域１０がＰ型であってもよい。この場合、図８に示すように、逆バイアス印加状態において導体部６，７の電位が自身の直下における拡散層３の電位よりも低くなるように、導体部６，７の端部は過電圧保護ダイオード５の側面の第１の部位に電気的に接続される。同様に、逆バイアス印加状態において導体部８，９の電位が自身の直下における周辺半導体領域１０の電位よりも高くなるように、導体部８，９の端部は過電圧保護ダイオード５の当該側面の第２の部位に電気的に接続される。このことは、導体構成部６ｃ，７ｃ，８ｃ，９ｃはそれぞれ、ｐｎ接合境界Ｐ１から遠ざかるように設けられることを意味する。   Further, the conductivity type of each semiconductor region of the semiconductor device 1 may be opposite to that described above. That is, the diffusion layer 3 may be N-type and the peripheral semiconductor region 10 may be P-type. In this case, as shown in FIG. 8, the end portions of the conductor portions 6 and 7 are overvoltage protected so that the potential of the conductor portions 6 and 7 is lower than the potential of the diffusion layer 3 immediately below the reverse bias applied state. It is electrically connected to the first part on the side surface of the diode 5. Similarly, the end portions of the conductor portions 8 and 9 are formed on the side surfaces of the overvoltage protection diode 5 so that the potentials of the conductor portions 8 and 9 are higher than the potential of the peripheral semiconductor region 10 immediately under the reverse bias applied state. It is electrically connected to the second part. This means that the conductor constituent parts 6c, 7c, 8c, 9c are provided so as to be away from the pn junction boundary P1.

したがって、一般的に言えば、Ｐ型半導体領域の上方に位置する導体部は、過電圧保護ダイオード５のうち高電位側に変位した部位に電気的に接続され、Ｎ型半導体領域の上方に位置する導体部は、過電圧保護ダイオード５のうち低電位側に変位した部位に電気的に接続される。これにより、逆バイアス印加状態において、導体部の下方に位置する半導体領域の表層部分を空乏化させることができる。   Therefore, generally speaking, the conductor portion located above the P-type semiconductor region is electrically connected to a portion of the overvoltage protection diode 5 displaced to the high potential side, and located above the N-type semiconductor region. The conductor portion is electrically connected to a portion of the overvoltage protection diode 5 that is displaced to the low potential side. Thereby, in the reverse bias applied state, the surface layer portion of the semiconductor region located below the conductor portion can be depleted.

上記のように、本実施形態では、導体部６，７，８，９の過電圧保護ダイオード５への接続先を直下の半導体層の導電型に応じて変えることで、絶縁膜４近傍の周辺半導体領域１０が空乏化するように積極的に導体部６，７，８，９の電位を制御する。これにより、絶縁膜４の可動イオンの移動を十分に抑制することができる。   As described above, in the present embodiment, the connection destination of the conductor portions 6, 7, 8, 9 to the overvoltage protection diode 5 is changed according to the conductivity type of the semiconductor layer immediately below, thereby allowing the peripheral semiconductor in the vicinity of the insulating film 4. The potentials of the conductor portions 6, 7, 8, and 9 are positively controlled so that the region 10 is depleted. Thereby, the movement of the movable ions of the insulating film 4 can be sufficiently suppressed.

なお、ＩＧＢＴの構成は上記の半導体装置１に限らない。例えば、変形例に係る半導体装置１Ｂは、図１０に示すように、Ｐ型のコレクタ領域１２に代えてＮ型のドレイン領域１２Ｂを有し、かつ、このドレイン領域１２Ｂとショットキー障壁を形成するコレクタ電極２３を有するものであってもよい。この場合、コレクタ電極２３は、白金、モリブデン等からなるバリアメタルを有する。   The configuration of the IGBT is not limited to the semiconductor device 1 described above. For example, as shown in FIG. 10, the semiconductor device 1B according to the modification has an N-type drain region 12B instead of the P-type collector region 12, and forms a Schottky barrier with the drain region 12B. It may have a collector electrode 23. In this case, the collector electrode 23 has a barrier metal made of platinum, molybdenum or the like.

（第２の実施形態）
次に、本発明の第２の実施形態について説明する。第２の実施形態に係る半導体装置１Ａは、縦型ＭＯＳＦＥＴである。半導体装置１Ａの平面図は、図１と同様である。図９は、半導体装置１Ａの断面図であり、第１の実施形態で説明した図２に対応する。なお、図９において、第１の実施形態と同じ構成要素には同じ符号を付している。以下、第１の実施形態との相違点を中心に説明する。(Second Embodiment)
Next, a second embodiment of the present invention will be described. The semiconductor device 1A according to the second embodiment is a vertical MOSFET. A plan view of the semiconductor device 1A is the same as FIG. FIG. 9 is a cross-sectional view of the semiconductor device 1A and corresponds to FIG. 2 described in the first embodiment. In FIG. 9, the same components as those in the first embodiment are denoted by the same reference numerals. Hereinafter, a description will be given focusing on differences from the first embodiment.

半導体装置１Ａは、Ｐ型の拡散層３と、絶縁膜４と、過電圧保護ダイオード５と、導体部６，７，８，９と、Ｎ型のドレイン領域１２Ａと、Ｎ型の拡散領域１３と、Ｎ型のストッパ領域１４と、ソース電極２１Ａと、ゲート電極２２と、ドレイン電極２３Ａと、ストッパ電極２４とを備えている。ドレイン領域１２Ａは、半導体基板２の下面２ｂに形成されており、このドレイン領域１２Ａ上にドレイン電極２３Ａが形成されている。また、ソース電極２１Ａは、拡散領域１３上に形成されている。   The semiconductor device 1A includes a P-type diffusion layer 3, an insulating film 4, an overvoltage protection diode 5, conductor portions 6, 7, 8, and 9, an N-type drain region 12A, and an N-type diffusion region 13. , An N-type stopper region 14, a source electrode 21A, a gate electrode 22, a drain electrode 23A, and a stopper electrode 24. The drain region 12A is formed on the lower surface 2b of the semiconductor substrate 2, and the drain electrode 23A is formed on the drain region 12A. Further, the source electrode 21 </ b> A is formed on the diffusion region 13.

半導体装置１Ａにおいて、導体部６，７の端部は逆バイアス印加状態において絶縁膜４近傍の拡散層３が空乏化するように過電圧保護ダイオード５の側面に電気的に接続されており、また、導体部８，９の端部は絶縁膜４近傍の周辺半導体領域１０が空乏化するように過電圧保護ダイオード５の側面に電気的に接続されている。なお、第２の実施形態において、「逆バイアス印加状態」は、ドレイン電極２３Ａが高電位（例えば直流電源の正極）に接続され、ソース電極２１Ａが接地され、ゲート電極２２に縦型ＭＯＳＦＥＴがオンしない程度の低電圧が印加された状態のことである。   In the semiconductor device 1A, the end portions of the conductor portions 6 and 7 are electrically connected to the side surface of the overvoltage protection diode 5 so that the diffusion layer 3 in the vicinity of the insulating film 4 is depleted in the reverse bias applied state. The end portions of the conductor portions 8 and 9 are electrically connected to the side surface of the overvoltage protection diode 5 so that the peripheral semiconductor region 10 near the insulating film 4 is depleted. In the second embodiment, in the “reverse bias applied state”, the drain electrode 23A is connected to a high potential (for example, the positive electrode of a DC power supply), the source electrode 21A is grounded, and the vertical MOSFET is turned on to the gate electrode 22. This is a state in which a low voltage is applied to such an extent that it does not occur.

第２の実施形態によれば、第１の実施形態の場合と同様の作用が得られるため、耐圧の低下を抑制し、信頼性を向上させることができる半導体装置１Ａを提供することができる。   According to the second embodiment, since the same operation as in the case of the first embodiment can be obtained, it is possible to provide the semiconductor device 1A that can suppress the decrease in breakdown voltage and improve the reliability.

上記の記載に基づいて、当業者であれば、本発明の追加の効果や種々の変形を想到できるかもしれないが、本発明の態様は、上述した個々の実施形態に限定されるものではない。異なる実施形態にわたる構成要素を適宜組み合わせてもよい。特許請求の範囲に規定された内容及びその均等物から導き出される本発明の概念的な思想と趣旨を逸脱しない範囲で種々の追加、変更及び部分的削除が可能である。   Based on the above description, those skilled in the art may be able to conceive additional effects and various modifications of the present invention, but the aspects of the present invention are not limited to the individual embodiments described above. . You may combine suitably the component covering different embodiment. Various additions, modifications, and partial deletions can be made without departing from the concept and spirit of the present invention derived from the contents defined in the claims and equivalents thereof.

１，１Ａ，１Ｂ 半導体装置
２ 半導体基板
２ａ 上面
２ｂ 下面
３ 拡散層
４ 絶縁膜
５ 過電圧保護ダイオード
５ａ，５ｂ 半導体層
６，７，８，９，３１，３２，３３，３４，３５ 導体部
６ａ，７ａ，８ａ，９ａ，６ｂ，７ｂ，８ｂ，９ｂ，６ｃ，７ｃ，８ｃ，９ｃ 導体構成部
１０ 周辺半導体領域
１１ バッファ領域
１２ コレクタ領域
１２Ａ，１２Ｂ ドレイン領域
１３ 拡散領域
１４ ストッパ領域
１５ 絶縁膜
１６ 表面保護膜
２１ エミッタ電極
２１Ａ ソース電極
２２ ゲート電極
２３ コレクタ電極
２３Ａ ドレイン電極
２４ ストッパ電極
２５ ガードリング
Ａ 活性領域
Ｂ 耐圧領域
Ｅ１，Ｅ２ 端点
Ｐ１，Ｐ２ （拡散層３の）境界
Ｒ 領域1, 1A, 1B Semiconductor device 2 Semiconductor substrate 2a Upper surface 2b Lower surface 3 Diffusion layer 4 Insulating film 5 Overvoltage protection diode 5a, 5b Semiconductor layers 6, 7, 8, 9, 31, 32, 33, 34, 35 Conductor portion 6a, 7a, 8a, 9a, 6b, 7b, 8b, 9b, 6c, 7c, 8c, 9c Conductor component 10 Peripheral semiconductor region 11 Buffer region 12 Collector region 12A, 12B Drain region 13 Diffusion region 14 Stopper region 15 Insulating film 16 Surface Protective film 21 Emitter electrode 21A Source electrode 22 Gate electrode 23 Collector electrode 23A Drain electrode 24 Stopper electrode 25 Guard ring A Active region B Withstand voltage region E1, E2 End point P1, P2 Boundary R region (of diffusion layer 3)

Claims (14)

半導体基板の一方の主面と他方の主面との間に主電流が流れる半導体装置であって、
前記半導体基板の前記一方の主面には、活性領域と、前記活性領域を取り囲み、前記半導体基板の周縁部を含む耐圧領域とが設けられ、
前記半導体装置は、
前記耐圧領域の前記一方の主面に選択的に形成され、前記活性領域を取り囲む第２導電型の拡散層と、
前記拡散層上、および当該拡散層の外側に位置する第１導電型の周辺半導体領域上に形成された絶縁膜と、
前記活性領域側から前記半導体基板の周縁部へ向かって前記絶縁膜上に交互に隣接配置された第１導電型の半導体層と第２導電型の半導体層とを有する過電圧保護ダイオードと、
前記絶縁膜上に前記耐圧領域に沿って形成された第１の導体部および第２の導体部と、を備え、
前記第１の導体部は、前記絶縁膜を介して前記拡散層の上方に配置され、前記第２の導体部は、前記絶縁膜を介して前記周辺半導体領域の上方に配置されており、
逆バイアス印加状態において前記絶縁膜近傍の前記拡散層が空乏化するように前記第１の導体部の端部が前記過電圧保護ダイオードに電気的に接続され、
前記第１導電型がＮ型であり、前記第２導電型がＰ型であり、
前記第１の導体部の端部は、前記逆バイアス印加状態において前記第１の導体部の電位が自身の直下における前記拡散層の電位よりも高くなるように前記過電圧保護ダイオードの側面の第１の部位に電気的に接続され、
前記第２の導体部の端部は、前記逆バイアス印加状態において前記第２の導体部の電位が自身の直下における前記周辺半導体領域の電位よりも低くなるように前記過電圧保護ダイオードの前記側面の第２の部位に電気的に接続されていることを特徴とする半導体装置。 A semiconductor device in which a main current flows between one main surface and the other main surface of a semiconductor substrate,
The one main surface of the semiconductor substrate is provided with an active region and a breakdown voltage region that surrounds the active region and includes a peripheral portion of the semiconductor substrate,
The semiconductor device includes:
A second conductivity type diffusion layer selectively formed on the one main surface of the breakdown voltage region and surrounding the active region;
An insulating film formed on the diffusion layer and on the peripheral semiconductor region of the first conductivity type located outside the diffusion layer;
An overvoltage protection diode having a first conductive type semiconductor layer and a second conductive type semiconductor layer alternately disposed adjacent to each other on the insulating film from the active region side toward a peripheral edge of the semiconductor substrate;
A first conductor portion and a second conductor portion formed on the insulating film along the withstand voltage region;
The first conductor portion is disposed above the diffusion layer via the insulating film, and the second conductor portion is disposed above the peripheral semiconductor region via the insulating film,
An end portion of the first conductor portion is electrically connected to the overvoltage protection diode so that the diffusion layer in the vicinity of the insulating film is depleted in a reverse bias application state,
The first conductivity type is N-type, the second conductivity type is P-type,
The end portion of the first conductor portion is a first side surface of the overvoltage protection diode so that the potential of the first conductor portion is higher than the potential of the diffusion layer immediately below the first conductor portion when the reverse bias is applied. Is electrically connected to
The end portion of the second conductor portion is formed on the side surface of the overvoltage protection diode so that the potential of the second conductor portion is lower than the potential of the peripheral semiconductor region immediately below the second conductor portion when the reverse bias is applied. A semiconductor device, wherein the semiconductor device is electrically connected to the second part . 前記第１の導体部は、
前記半導体基板の周縁部に沿って延在する第１の導体構成部と、
前記第１の導体構成部に一端が接続され、前記過電圧保護ダイオードの近傍まで延在する第２の導体構成部と、
前記第２の導体構成部と前記過電圧保護ダイオードを電気的に接続する第３の導体構成部と、を有し、
前記第２の導体構成部は、前記第１の導体構成部よりも幅広に形成され、
前記第３の導体構成部は、前記第２の導体構成部の他端の幅よりも幅狭に形成され、かつ前記半導体基板の側端側に寄るように設けられていることを特徴とする請求項１に記載の半導体装置。 The first conductor portion is
A first conductor component extending along a peripheral edge of the semiconductor substrate;
A second conductor component having one end connected to the first conductor component and extending to the vicinity of the overvoltage protection diode;
A second conductor component that electrically connects the second conductor component and the overvoltage protection diode;
The second conductor component is formed wider than the first conductor component,
The third conductor component is formed narrower than the other end of the second conductor component, and is provided so as to be closer to the side end of the semiconductor substrate. The semiconductor device according to claim 1 . 前記第２の導体部は、
前記半導体基板の周縁部に沿って延在する第１の導体構成部と、
前記第１の導体構成部に一端が接続され、前記過電圧保護ダイオードの近傍まで延在する第２の導体構成部と、
前記第２の導体構成部と前記過電圧保護ダイオードを電気的に接続する第３の導体構成部と、を有し、
前記第２の導体構成部は、前記第１の導体構成部よりも幅広に形成され、
前記第３の導体構成部は、前記第２の導体構成部の他端の幅よりも幅狭に形成され、かつ前記活性領域側に寄るように設けられていることを特徴とする請求項１に記載の半導体装置。 The second conductor portion is
A first conductor component extending along a peripheral edge of the semiconductor substrate;
A second conductor component having one end connected to the first conductor component and extending to the vicinity of the overvoltage protection diode;
A second conductor component that electrically connects the second conductor component and the overvoltage protection diode;
The second conductor component is formed wider than the first conductor component,
It said third conductor arrangement portion, claim, characterized in that it said than the second width of the other end of the conductor arrangement portion is formed in a narrow, and provided so as to stop at the active region side 1 A semiconductor device according to 1. 前記第２の導体構成部は、前記過電圧保護ダイオードに近づくにつれて太くなることを特徴とする請求項２または３に記載の半導体装置。 4. The semiconductor device according to claim 2, wherein the second conductor constituent portion becomes thicker as it approaches the overvoltage protection diode. 5. 半導体基板の一方の主面と他方の主面との間に主電流が流れる半導体装置であって、
前記半導体基板の前記一方の主面には、活性領域と、前記活性領域を取り囲み、前記半導体基板の周縁部を含む耐圧領域とが設けられ、
前記半導体装置は、
前記耐圧領域の前記一方の主面に選択的に形成され、前記活性領域を取り囲む第２導電型の拡散層と、
前記拡散層上、および当該拡散層の外側に位置する第１導電型の周辺半導体領域上に形成された絶縁膜と、
前記活性領域側から前記半導体基板の周縁部へ向かって前記絶縁膜上に交互に隣接配置された第１導電型の半導体層と第２導電型の半導体層とを有する過電圧保護ダイオードと、
前記絶縁膜上に前記耐圧領域に沿って形成された第１の導体部および第２の導体部と、を備え、
前記第１の導体部は、前記絶縁膜を介して前記拡散層の上方に配置され、前記第２の導体部は、前記絶縁膜を介して前記周辺半導体領域の上方に配置されており、
逆バイアス印加状態において前記絶縁膜近傍の前記拡散層が空乏化するように前記第１の導体部の端部が前記過電圧保護ダイオードに電気的に接続され、
前記第１導電型がＰ型であり、前記第２導電型がＮ型であり、
前記第１の導体部の端部は、前記逆バイアス印加状態において前記第１の導体部の電位が自身の直下における前記拡散層の電位よりも低くなるように前記過電圧保護ダイオードの側面の第１の部位に電気的に接続され、
前記第２の導体部の端部は、前記逆バイアス印加状態において前記第２の導体部の電位が自身の直下における前記周辺半導体領域の電位よりも高くなるように前記過電圧保護ダイオードの前記側面の第２の部位に電気的に接続されていることを特徴とする半導体装置。 A semiconductor device in which a main current flows between one main surface and the other main surface of a semiconductor substrate,
The one main surface of the semiconductor substrate is provided with an active region and a breakdown voltage region that surrounds the active region and includes a peripheral portion of the semiconductor substrate,
The semiconductor device includes:
A second conductivity type diffusion layer selectively formed on the one main surface of the breakdown voltage region and surrounding the active region;
An insulating film formed on the diffusion layer and on the peripheral semiconductor region of the first conductivity type located outside the diffusion layer;
An overvoltage protection diode having a first conductive type semiconductor layer and a second conductive type semiconductor layer alternately disposed adjacent to each other on the insulating film from the active region side toward a peripheral edge of the semiconductor substrate;
A first conductor portion and a second conductor portion formed on the insulating film along the withstand voltage region;
The first conductor portion is disposed above the diffusion layer via the insulating film, and the second conductor portion is disposed above the peripheral semiconductor region via the insulating film,
An end portion of the first conductor portion is electrically connected to the overvoltage protection diode so that the diffusion layer in the vicinity of the insulating film is depleted in a reverse bias application state,
The first conductivity type is P-type, the second conductivity type is N-type,
The end portion of the first conductor portion is a first side surface of the overvoltage protection diode so that the potential of the first conductor portion is lower than the potential of the diffusion layer immediately below the first conductor portion when the reverse bias is applied. Is electrically connected to
The end portion of the second conductor portion is formed on the side surface of the overvoltage protection diode so that the potential of the second conductor portion is higher than the potential of the peripheral semiconductor region immediately below the second conductor portion when the reverse bias is applied. A semiconductor device, wherein the semiconductor device is electrically connected to the second part. 前記第１の導体部は、
前記半導体基板の周縁部に沿って延在する第１の導体構成部と、
前記第１の導体構成部に一端が接続され、前記過電圧保護ダイオードの近傍まで延在する第２の導体構成部と、
前記第２の導体構成部と前記過電圧保護ダイオードを電気的に接続する第３の導体構成部と、を有し、
前記第２の導体構成部は、前記第１の導体構成部よりも幅広に形成され、
前記第３の導体構成部は、前記第２の導体構成部の他端の幅よりも幅狭に形成され、かつ前記活性領域側に寄るように設けられていることを特徴とする請求項５に記載の半導体装置。 The first conductor portion is
A first conductor component extending along a peripheral edge of the semiconductor substrate;
A second conductor component having one end connected to the first conductor component and extending to the vicinity of the overvoltage protection diode;
A second conductor component that electrically connects the second conductor component and the overvoltage protection diode;
The second conductor component is formed wider than the first conductor component,
It said third conductor arrangement portion, claim, characterized in that the width is formed narrower, and provided so as to stop at the active region side than the width of the other end of the second conductor arrangement portion 5 A semiconductor device according to 1. 前記第２の導体部は、
前記半導体基板の周縁部に沿って延在する第１の導体構成部と、
前記第１の導体構成部に一端が接続され、前記過電圧保護ダイオードの近傍まで延在する第２の導体構成部と、
前記第２の導体構成部と前記過電圧保護ダイオードを電気的に接続する第３の導体構成部と、を有し、
前記第２の導体構成部は、前記第１の導体構成部よりも幅広に形成され、
前記第３の導体構成部は、前記第２の導体構成部の他端の幅よりも幅狭に形成され、かつ前記半導体基板の側端側に寄るように設けられていることを特徴とする請求項５に記載の半導体装置。 The second conductor portion is
A first conductor component extending along a peripheral edge of the semiconductor substrate;
A second conductor component having one end connected to the first conductor component and extending to the vicinity of the overvoltage protection diode;
A second conductor component that electrically connects the second conductor component and the overvoltage protection diode;
The second conductor component is formed wider than the first conductor component,
The third conductor component is formed narrower than the other end of the second conductor component, and is provided so as to be closer to the side end of the semiconductor substrate. The semiconductor device according to claim 5 . 前記第２の導体構成部は、前記過電圧保護ダイオードに近づくにつれて太くなることを特徴とする請求項６または７に記載の半導体装置。 The semiconductor device according to claim 6, wherein the second conductor constituent portion becomes thicker as it approaches the overvoltage protection diode. 前記半導体基板はシリコン基板であり、前記絶縁膜はシリコン酸化膜であることを特徴とする請求項１〜８のいずれかに記載の半導体装置。 The semiconductor device according to claim 1, wherein the semiconductor substrate is a silicon substrate, and the insulating film is a silicon oxide film. 前記第１の導体部および／または前記第２の導体部は、隣接する前記第１導電型の半導体層と前記第２導電型の半導体層の接合境界を跨ぐようにして前記過電圧保護ダイオードに接続されていることを特徴とする請求項１〜９のいずれかに記載の半導体装置。 The first conductor portion and / or the second conductor portion is connected to the overvoltage protection diode so as to straddle a junction boundary between the adjacent first conductive type semiconductor layer and the second conductive type semiconductor layer. The semiconductor device according to claim 1 , wherein the semiconductor device is formed. 前記拡散層中に形成された第１導電型の拡散領域と、
前記拡散領域上に形成されたエミッタ電極と、
前記過電圧保護ダイオード上に形成されたゲート電極と、
前記半導体基板の前記他方の主面に形成された第２導電型のコレクタ領域と、
前記コレクタ領域上に形成されたコレクタ電極と、
をさらに備えることを特徴とする請求項１〜１０のいずれかに記載の半導体装置。 A diffusion region of a first conductivity type formed in the diffusion layer;
An emitter electrode formed on the diffusion region;
A gate electrode formed on the overvoltage protection diode;
A second conductivity type collector region formed on the other main surface of the semiconductor substrate;
A collector electrode formed on the collector region;
The semiconductor device according to claim 1 , further comprising: 前記拡散層中に形成された第１導電型の拡散領域と、
前記拡散領域上に形成されたエミッタ電極と、
前記過電圧保護ダイオード上に形成されたゲート電極と、
前記半導体基板の前記他方の主面に形成された第１導電型のドレイン領域と、
前記ドレイン領域上に形成され、前記ドレイン領域とショットキー障壁を形成するコレクタ電極と、
をさらに備えることを特徴とする請求項１〜１０のいずれかに記載の半導体装置。 A diffusion region of a first conductivity type formed in the diffusion layer;
An emitter electrode formed on the diffusion region;
A gate electrode formed on the overvoltage protection diode;
A drain region of a first conductivity type formed on the other main surface of the semiconductor substrate;
A collector electrode formed on the drain region and forming a Schottky barrier with the drain region;
The semiconductor device according to claim 1 , further comprising: 前記拡散層中に形成された第１導電型の拡散領域と、
前記拡散領域上に形成されたソース電極と、
前記過電圧保護ダイオード上に形成されたゲート電極と、
前記半導体基板の前記他方の主面に形成された第１導電型のドレイン領域と、
前記ドレイン領域上に形成されたドレイン電極と、
をさらに備えることを特徴とする請求項１〜１０のいずれかに記載の半導体装置。 A diffusion region of a first conductivity type formed in the diffusion layer;
A source electrode formed on the diffusion region;
A gate electrode formed on the overvoltage protection diode;
A drain region of a first conductivity type formed on the other main surface of the semiconductor substrate;
A drain electrode formed on the drain region;
The semiconductor device according to claim 1 , further comprising: 前記耐圧領域の前記一方の主面に選択的に形成され、前記拡散層を取り囲む１本または複数本の第２導電型のガードリングをさらに備えることを特徴とする請求項１〜１３のいずれかに記載の半導体装置。 14. The semiconductor device according to claim 1 , further comprising one or a plurality of second conductivity type guard rings that are selectively formed on the one main surface of the breakdown voltage region and surround the diffusion layer . A semiconductor device according to 1.
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