JP5517688B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having high withstand voltage.

  In a semiconductor device, the breakdown voltage of the pn junction is the absolute value of the reverse voltage when the electric field strength reaches the breakdown electric field strength determined by the physical properties of the semiconductor substrate (that is, breakdown) at any of the peripheral portions of the injection layer where electric field concentration occurs. Defined by value.

  In a conventional high breakdown voltage semiconductor device, the reverse breakdown voltage (hereinafter referred to as breakdown voltage) of a pn junction composed of an n-type semiconductor substrate and a high concentration p type injection layer (active region) is the peripheral edge of the high concentration p type injection layer. It was limited by the concentration of the electric field on the cylindrical junction. Therefore, by forming a low-concentration p-type injection layer at the terminal portion of the semiconductor device adjacent to the peripheral portion of the high-concentration p-type injection layer, electric field concentration at the peripheral portion of the high-concentration p-type injection layer is alleviated. The reverse breakdown voltage of the pn junction can be increased (for example, Patent Document 1). This low-concentration p-type injection layer is generally called a RESURF (Reduced Surface Field) layer or a JTE (Junction Termination Extension).

  Even in the above structure, electric field concentration occurs at the peripheral portions of the high concentration p-type injection layer and the low concentration p-type injection layer. By further forming a low-concentration p-type injection layer (low-concentration p-type injection layer) adjacent to the peripheral edge of the low-concentration p-type injection layer, the breakdown voltage of the pn junction can be further increased (for example, a patent) Reference 2).

  In the semiconductor device disclosed in Patent Document 1, the electric field strength at the peripheral portion of the low concentration p-type injection layer is increased by increasing the injection amount of the low concentration p-type injection layer, and the electric field strength at the peripheral portion of the high concentration p-type injection layer. Decreases. The maximum breakdown voltage can be obtained when the peripheral edge of the high concentration p-type implantation layer and the peripheral edge of the low concentration p-type implantation layer simultaneously break down.

  In Patent Document 2, the electric field strength at the peripheral portion of the low concentration p-type injection layer is lowered by the low concentration p-type injection layer. Therefore, the injection amount of the low-concentration p-type injection layer can be increased more than that in Patent Document 1, and the electric field strength at the peripheral portion of the high-concentration p-type injection layer can be reduced. As a result, in the semiconductor device of Patent Document 2, the withstand voltage under the condition that the peripheral portion of the high-concentration p-type implantation layer and the peripheral portion of the low-concentration p-type implantation layer breakdown simultaneously is higher than that of Patent Document 1. In the semiconductor device of Patent Document 2, when the high-concentration p-type injection layer peripheral portion, the low-concentration p-type injection layer peripheral portion, and the low-concentration p-type injection layer peripheral portion simultaneously break down, the maximum breakdown voltage is obtained. Is obtained.

JP-A-5-63213 Japanese Patent No. 3997551 JP 2008-18125 A

R. Stengl and U.S. Gosele, “VARIATION OF LATERAL DOPING-A NEW CONNECT TO AVOID HIGH VOLTAGE BRAKDOWN OF PLANAR JUNCTIONS,” IEDM 85, p. 154, 1985.

  In such a pn junction consisting of an n-type semiconductor substrate and a high-concentration p-type injection layer formed on the substrate surface, a low-concentration p-type injection layer and a low-concentration p-type implantation adjacent to the periphery of the high-concentration p-type injection layer. In a semiconductor device provided with a layer, the breakdown voltage can be increased by increasing the injection amount of the low-concentration p-type injection layer. However, the injection amount of the low-concentration p-type injection layer is the peripheral portion of the low-concentration p-type injection layer. There was a problem of being limited by surrender. For this reason, in order to obtain a desired pressure | voltage resistance, the area of the termination | terminus part had to be enlarged.

  As a solution to this problem, there is a structure in which a floating field plate (FFP (Floating Field Plate)) as shown in Patent Document 3 is provided. The floating field plate of this document is overlaid with the field plate on the source electrode side. Since the wrapping position is disposed, the place where the floating field plate can be disposed is only in the vicinity of the source electrode. Therefore, the range in which the floating field plate of the document affects the electric field strength on the substrate surface is limited to the vicinity of the source electrode, and the width of the terminal portion is wide, particularly in a semiconductor device having a high breakdown voltage on the order of kV (kilovolt). If the effect was small.

  In view of the above, the present invention provides a semiconductor device that has a higher breakdown voltage without changing the area of the termination, in other words, can reduce the area of the termination without reducing the breakdown voltage. For the purpose.

One embodiment of the present invention is a semiconductor device, a first conductivity type semiconductor substrate, and a second conductivity type first impurity which is selectively formed on a surface of the semiconductor substrate and is an active region of the semiconductor device. A second conductivity type second impurity region selectively formed on the surface of the semiconductor substrate adjacent to the first impurity layer and having a lower impurity concentration than the first impurity layer, and the second impurity region. A third impurity region of a second conductivity type, which is selectively formed on the surface of the semiconductor substrate adjacent to the impurity region and has a lower impurity concentration than the first impurity layer, the second impurity region, and the third impurity region And a first floating field plate formed on the semiconductor substrate at the boundary with the impurity region via an insulating layer.

According to one aspect of the present invention, there is provided a semiconductor device having a first conductivity type semiconductor substrate and a second conductivity type second substrate which is selectively formed on a surface of the semiconductor substrate and is an active region of the semiconductor device. A second impurity region of a second conductivity type, which is selectively formed on the surface of the semiconductor substrate adjacent to the first impurity layer and having a lower impurity concentration than the first impurity layer; Adjacent to the second impurity region, selectively formed on the surface of the semiconductor substrate and having a lower impurity concentration than the first impurity layer, a second impurity region of the second conductivity type, the second impurity region, By providing a first floating field plate formed on the semiconductor substrate at the boundary with the third impurity region via an insulating layer, the voltage is divided by the first floating field plate appropriately at an intermediate potential. Since the, to achieve higher breakdown voltage without changing the area of the end portion, it is possible to reduce the area of the end portion without reducing the breakdown voltage in other words. In addition, the number of chips that can be manufactured from one wafer is increased, and cost reduction can be expected.

  Here, the effect when the field plate and the first floating field plate are separated on a plane will be described. When the field plate and the first floating field plate are not spaced apart from each other, i.e., have a structure in which they overlap each other, the capacitive coupling between the field plate and the first floating field plate is usually the first floating field plate and the substrate. It becomes stronger than the capacitive coupling between the surfaces. Therefore, the potential of the first floating field plate is close to the potential of the field plate, and the first floating field plate has an effect close to that of the field plate.

  In this case, if the first floating field plate is stretched too much, breakdown will first occur on the substrate surface located below the tip of the first floating field plate. That is, no matter how wide the second impurity region and the third impurity region are, the position where the first floating field plate can be disposed is limited to the vicinity of the first impurity layer. That is, the range in which the first floating field plate affects the electric field strength on the substrate surface is limited to the vicinity of the first impurity layer. On the other hand, when the field plate and the first floating field plate are spaced apart on a plane, there is no restriction on the position where the first floating field plate is disposed. Therefore, it is possible to influence the electric field strength at a location away from the first impurity layer using the first floating field plate. When the first floating field plate overlaps the second impurity region and the third impurity region, an effect of increasing the breakdown voltage is obtained by the mechanism described in the embodiment.

  The most important thing here is that when the field plate and the first floating field plate are overlapped, the effect is limited to the vicinity of the first impurity layer, whereas the field plate and the first floating field plate are on the plane. When the first floating field plate is separated and overlaps the second impurity region and the third impurity region, the second impurity region and the third impurity region separated from the first impurity layer can be affected. is there.

  The above-described features are particularly prominent when a wide second impurity region and third impurity region are required in a semiconductor device having a high breakdown voltage of the order of kV (kilovolt) or more.

It is sectional drawing which shows the semiconductor device by Embodiment 1 of this invention. It is a schematic diagram explaining the effect of this invention. It is a schematic diagram explaining the effect of this invention. It is a schematic diagram explaining the effect of this invention. It is a schematic diagram which shows the effect of FFP of Embodiment 1 of this invention. It is sectional drawing which shows the semiconductor device by the modification of Embodiment 1 of this invention. It is a figure which shows the result of having performed device simulation with respect to Embodiment 1 of this invention. It is sectional drawing which shows the semiconductor device by the modification of Embodiment 1 of this invention. It is sectional drawing which shows the semiconductor device by the modification of Embodiment 1 of this invention. It is a schematic diagram which shows the cross section around FFP of Embodiment 2 of this invention. It is sectional drawing which shows the semiconductor device by Embodiment 3 of this invention. It is sectional drawing which shows the semiconductor device by Embodiment 3 of this invention.

<A. Embodiment 1>
<A-1. Configuration>
1 is a cross-sectional view showing a terminal portion (an outer peripheral portion of a semiconductor chip) of a semiconductor device according to a first embodiment of the present invention. The main joint side is the left direction in the figure, and the dicing line side is the right direction in the figure. This end portion is arranged in a ring shape between the main junction and the dicing line when viewed in plan view.

As shown in FIG. 1A, a semiconductor device according to the present invention is selectively formed on a drift layer 1 which is an n-type silicon semiconductor substrate having an impurity concentration of 10 ¹⁴ cm ⁻³ or less, and on the surface of the drift layer 1. A base 2 (first impurity layer) that is an active region of the semiconductor device that forms a pn junction with the drift layer 1, and a low-concentration p-type injection layer adjacent to the periphery of the base 2 Thus, the resurf layer 3 (second impurity region) having a lower impurity concentration than the base 2 selectively formed on the surface of the drift layer 1 and a further lower concentration p-type injection layer adjacent to the peripheral portion of the resurf layer 3 The resurf layer 4 (third impurity region) having a lower impurity concentration than the base 2 and the cathode electrode 7 formed below the drift layer 1 are provided selectively on the surface of the drift layer 1.

  Further, the semiconductor device is connected to the channel stopper 5 formed on the surface of the drift layer 1 so as to be separated from the RESURF layer 4, the anode electrode 6 formed on the base 2, and the base 2, and the base 2 and RESURF layer 3 are connected. The field plate 9 formed on the drift layer 1 at the boundary between the field plate 10, the field plate 10 formed on the channel stopper 5, the insulating layer 8 formed on the drift layer 1, and the field plate 9 on the plane An FFP 11 (first floating field plate) is formed on the drift layer 1 at the boundary between the RESURF layer 3 and the RESURF layer 4 through the insulating layer 8 so as to overlap with each other.

  The RESURF layer 3 and the RESURF layer 4 may be formed by different injection processes, respectively, or when the RESURF layer 4 is formed, the RESURF layer 3 is also injected into a region to be the RESURF layer 3, and a difference injection amount is set later. The RESURF layer 3 may be formed by implantation. Therefore, the cross-sectional view of the terminal portion of the semiconductor device according to the first embodiment may have a shape in which the RESURF layer 13 surrounds (includes) the RESURF layer 12 as shown in FIG.

  The voltage is applied to the anode electrode 6 on the base 2 and the cathode electrode 7 on the back surface of the substrate. As shown in FIG. 1, the base 2, the anode electrode 6, and the cathode electrode 7 are formed over the entire main junction. When the anode electrode 6 is grounded, the cathode electrode 7 is set to a positive voltage, so that a reverse voltage is applied to the pn junction, and the base 2, the resurf layer 3, the resurf layer 4 that are p-type injection layers, and the n-type A depletion layer spreads from the pn junction boundary with the drift layer 1 which is a semiconductor substrate.

  A field plate 9 covering the RESURF layer 3 is connected to the base 2 via an insulating layer 8. A channel stopper 5 which is a high-concentration n-type injection layer is provided outside the RESURF layer 4 (on the dicing line side on the right side in the figure), and the channel stopper 5 has a field that slightly covers the RESURF layer 4 via an insulating layer 8. The plate 10 is connected.

  Here, the field plate 9 is at the same potential as the anode electrode 6, and when a reverse voltage is applied to the pn junction, holes are collected on the surface of the substrate to equivalently reduce the curvature of the curved portion of the base 2. Thus, there is an effect of reducing the electric field strength and canceling out electrons on the substrate surface attracted by positive fixed charges existing in the insulating layer 8 in the vicinity of the semiconductor-insulator interface.

  Intuitively, both effects are an image of extending the boundary of the depletion layer on the substrate surface toward the tip of the field plate 9. The channel stopper 5 and the field plate 10 have substantially the same potential as the cathode electrode 7 when the depletion layer does not reach the dicing line, suppresses excessive extension of the depletion layer, and prevents reach through to the channel stopper 5. There is a role.

<A-2. Operation>
The operation of the first embodiment will be described in order with reference to FIGS. 2, 3, and 4 show a cross-sectional view (each figure (a)) of the terminal portion of the semiconductor device and an image diagram (each figure (b)) of the electric field intensity in the vicinity of the substrate surface corresponding to each. . The location where the electric field actually concentrates (impact point) is somewhere from the top surface of the substrate to the vicinity of the depth of the injection layer, but for simplicity here, the impact point is aligned with a certain depth near the surface of the substrate. Is assumed.

  FIG. 2A shows a structure in which a RESURF layer 104 that is a single-concentration p-type injection layer is adjacent to the base 2. Here, the impact point is at the base 2 (P +) curved portion a point, the RESURF layer 104 (P−−) end (or the lower end of the tip of the field plate 10 connected to the channel stopper 5) b point, and the base 2 This is a lower point c at the tip of the connected field plate 9. Here, for simplicity, it is assumed that the electric field intensity at point c is always lower than that at point a (this balance can be adjusted by changing the width of the field plate, but is not considered here).

The balance of the electric field strength at point a and point b can be adjusted by the injection amount of the RESURF layer 104. Increasing the injection amount of the RESURF layer 104 decreases the electric field strength at point a and increases the electric field strength at point b. Here, when the implantation amount of the RESURF layer 104 is adjusted so that the electric field strength at the point a and the electric field strength at the point b at the time of breakdown are substantially equal (solid line graph in FIG. 2B), the maximum breakdown voltage is obtained. can get. The injection amount of the RESURF layer 104 at this time is approximately 1 × 10 ¹² cm ⁻² . By increasing the injection amount of the RESURF layer 104 beyond this optimum condition, the electric field intensity at the point a can be further reduced, but breakdown occurs at the point b before the point a, resulting in a decrease in breakdown voltage (FIG. 2 (b) dotted line graph).

  As shown in FIG. 3 (a), the RESURF layer 3 (injection layer slightly increased in the amount of injection on the base 2 side of the RESURF layer 4 (P--) corresponding to the RESURF layer 104 in FIG. P-) is provided. In this structure, the electric field concentrates on the curved portion d point of the RESURF layer 3 in addition to the points a, b, and c in FIG. Here, when the injection amount of the RESURF layer 3 is increased, the electric field intensity at the point d is increased and the electric field intensity at the point a is decreased, but the electric field intensity at the point b is only slightly increased. If the injection amount of the RESURF layer 3 is slightly increased and the injection amount of the RESURF layer 4 is slightly decreased with respect to the injection amount of the RESURF layer 104 which was the optimum condition in FIG. In addition, the line integral value of the electric field on the substrate surface (approximately, the area surrounded by the graph) can be increased, and a higher breakdown voltage can be obtained (solid line graph in FIG. 3B).

  Intuitively speaking, the largest factor that can increase the breakdown voltage by the structure of FIG. 3A is that the portion of the RESURF layer 3 that is not covered by the field plate 9 by increasing the injection amount of the RESURF layer 3 (point c) (B) to (d) is increased. In the structure of FIG. 3A, the upper limit of the injection amount of the RESURF layer is limited by the electric field strength at the point d (dotted line graph of FIG. 3B).

  Therefore, as shown in FIG. 4A, by providing the FFP 11 that overlaps the RESURF layer 3 and the RESURF layer 4, the electric field intensity peak at the point d is changed to the points e and f below the tip of the FFP 11. They can be shared (FIG. 4B). Here, by installing the FFP 11, the line integral value of the electric field on the substrate surface (because the line integral along the substrate surface does not affect the vertical electric field component generated by the FFP 11), By sharing the electric field concentrated at one point by two points, the height of the electric field strength peak can be lowered.

  That is, by providing the FFP, the voltage applied to each RESURF layer can be adjusted, and the electric field at the peripheral portion of the RESURF layer 3 can be reduced. As a result, the injection amount of the RESURF layer 3 can be further increased, and the withstand voltage can be further improved.

  That is, in FIG. 3, in the implantation condition (dotted line graph in FIG. 3B) where the point d yields at the applied voltage Vb, by providing the FFP 11 as shown in FIG. 4A, the breakdown at the applied voltage Vb is reduced. Thus, even higher voltages can be applied without breakdown (solid line graph in FIG. 4B). In other words, the injection amount of the RESURF layer 3 under the optimum condition of FIG. 4 is higher than that of FIG. 3, and the breakdown voltage under the optimum condition of FIG. 4 is higher than that of FIG.

  Here, if the FFP 11 is connected to the top surface of the substrate at point e (that is, it is not floating), the electric field component in the vertical direction becomes too large at the top surface of the substrate at point f, and the breakdown voltage drops dramatically. That is, the effect of increasing the breakdown voltage is obtained only when the field plate is floating.

  FIG. 5 is a schematic diagram showing the effect of FFP11. This figure shows the potential in each case (FIG. 5A) when the FFP 11 is not provided (FIG. 5A) and when it is provided (FIG. 5B) in the vicinity of the boundary between the RESURF layer 3 and the RESURF layer 4. 5 (c) (d)) and electric field strength (FIGS. 5 (e) and (f)).

  When the FFP 11 is provided, the potential of the FFP 11 becomes an intermediate potential determined by the potential distribution on the substrate surface covered by the FFP 11. Here, in FIG. 5, for simplicity, an intermediate potential is taken at the boundary between the RESURF layer 3 and the RESURF layer 4, but this is not always true. Also, the electric field strength is not actually symmetrical.

  Therefore, a potential difference is generated between the FFP 11 and the substrate surface, and the carrier distribution is modulated on the substrate surface (FIG. 5B). Of the substrate surface corresponding to the lower part of the FFP 11 tip, fixed electrons (inversion layer) are generated on the RESURF layer 3 side, and fixed holes are generated on the RESURF layer 4 side. In order to maintain electrical neutrality, charges of opposite signs accumulate in the RESURF layer 3 and the RESURF layer 4 by the amount of those fixed carriers (FIG. 5B).

  As a result, the electric field intensity peak at the boundary between the RESURF layer 3 and the RESURF layer 4 disappears as shown in the solid line graphs of FIGS. 5D and 5F, and instead an electric field intensity peak is generated at the lower part of the tip of the FFP 11. To do. Of course, when the FFP 11 is not provided, the electric field strength peak still exists (FIGS. 5C and 5E).

  By appropriately setting the overlap amount of the FFP 11 with respect to the RESURF layer 3 and the RESURF layer 4, the electric field strength at the lower part of both ends of the FFP 11 can be made lower than the electric field strength when the FFP 11 is not provided. However, since the electric field on the substrate surface has a considerable amount of electric field component between the FFP 11 and the substrate surface (mainly, the electric field component in the vertical direction with respect to the substrate surface), the width of the FFP 11 is too large (opposing the FFP 11). If the potential difference from the surface of the substrate is too large), the breakdown voltage is lowered due to the breakdown at the lower end of the tip of the FFP 11.

  By the way, in a semiconductor device having a RESURF layer at the terminal end, the simplest method for increasing the breakdown voltage is to increase the width of the RESURF layer. However, in that case, the area of the termination portion becomes large, and the area of the semiconductor device also becomes large. One of the major features of the present invention is that the breakdown voltage can be improved without changing the width of the RESURF layer (and consequently the area of the terminal portion and the semiconductor device). Conversely, if the present invention is used, the width of the RESURF layer necessary to satisfy a certain breakdown voltage can be reduced, and the area of the semiconductor device can be reduced. Can be increased.

  In the present invention, the FFP has an appropriate intermediate potential without being strongly influenced by the potential on the source electrode side, and the breakdown voltage of the semiconductor device can be improved.

  Note that the same effect can be obtained even if the signs of the carriers of all the elements constituting the semiconductor device of the first embodiment are reversed.

  In Embodiment 1, the widths of the plurality of RESURF layers are drawn close to each other, but the widths of the RESURF layers may be different from each other. The depths of the plurality of RESURF layers do not have to be the same, and the depth of the RESURF layer adjacent to the base 2 may be shallower than the base 2.

  The semiconductor substrate may be made of any semiconductor material such as silicon carbide (SiC) or gallium nitride (GaN).

  In the first embodiment, a diode is used as an example of the semiconductor device. However, a metal-oxide-field-effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a thyristor-type pn junction pn junction, or the like. Any semiconductor device may be used as long as it has the following.

  In the first embodiment, the field plate 9 may be omitted if the electric field strength at the peripheral edge of the base 2 can be sufficiently suppressed without the field plate 9.

  For example, in FIG. 4, when the field strengths at points b, e, and f at the time of breakdown are sufficiently higher than the field strengths at points a and c, the breakdown voltage changes greatly even if the field plate 9 is omitted. do not do.

  Further, even if the injection method (VLD (Variation of Lateral Doping)) of Non-Patent Document 1 that relaxes the curvature of the cylindrical joint of the base 2 is used, the electric field strength at the peripheral portion of the base 2 can be suppressed. In some cases, the field plate 9 can be omitted.

<A-3. Modification 1>
FIG. 6 is a cross-sectional view showing a first modification of the present invention. In FIG. 6, the same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. In the structure shown in FIG. 1, the RESURF layer 3 and the RESURF layer 4, and the RESURF layer 12 and the RESURF layer 13 are formed adjacent to each other, but as shown in FIG. 6, the RESURF layer 100 (second impurity region) and The RESURF layer 101 (third impurity region) may be adjacent to each other while being separated from each other. The RESURF layer 100 of the FFP 11 (first floating field plate) that is spaced apart from the field plate 9 on a plane and formed on the drift layer 1 in the gap portion between the RESURF layer 100 and the RESURF layer 101 via the insulating layer 8. The amount of overlap with respect to is larger than that with respect to the RESURF layer 101.

FIG. 7 shows the result of device simulation performed on an n-type silicon semiconductor substrate having an impurity concentration of 10 ¹⁴ cm ⁻³ or less. Here, the width of the RESURF layer and the RESURF layer is 290 μm, and the implantation depth (junction depth) is 6 μm.

As shown in FIG. 7, when the FFP 11 is provided (surface concentration 6 × 10 ¹⁵ cm ⁻³ , 2 × 10 ¹⁵ cm) as compared with the case where the FFP is not provided in which the surface concentration of the adjacent RESURF layer is variously changed. ^-3 ) shows that the static withstand voltage is improved (3901 V). Further, it can be seen that the static withstand voltage is improved (3763 V) when the FFP 11 is provided, compared to the case where the FFP is not provided in the adjacent RESURF layers (separation distance 30 μm) while being separated.

<A-4. Modification 2>
In the structure of the semiconductor device shown in FIGS. 1 and 6, there are two RESURF layers with different implantation amounts. However, the RESURF layers with different implantation amounts may be further increased. FIG. 8 is a cross-sectional view showing a second modification of the present invention, in which there are three RESURF layers with different injection amounts.

  In FIG. 8A, a resurf layer 16 (fourth impurity layer) that is selectively formed on the surface of the drift layer 1 adjacent to the resurf layer 4 and has a lower impurity concentration than the base 2, and the resurf layer 4. Further, an FFP 18 (second floating field plate) is further formed on the drift layer 1 at the boundary between the RESURF layer 16 and the RESURF layer 16 via the insulating layer 8.

  In FIG. 8B, a resurf layer 21 (fourth impurity layer) which is adjacent to the RESURF layer 101 and is adjacent to the RESURF layer 101 and selectively formed on the surface of the drift layer 1 and having a lower impurity concentration than the base 2; Further provided is an FFP 18 (second floating field plate) formed on the drift layer 1 in the gap portion between the RESURF layer 101 and the RESURF layer 21 via the insulating layer 8. In FIG. 8, the same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In FIG. 8A, the adjacent RESURF layers 3, 4, 16 decrease in the injection amount in the order of distance from the base 2, and the FFPs 17, 18 overlap the RESURF layers with different injection amounts via the insulating layer 8.

  Further, in FIG. 8B, the resurf layers 100, 101, and 21 adjacent to each other while being separated from each other have a smaller amount of injection in the order of distance from the base 2, and the FFPs 17 and 18 have the insulating layer 8 added to the resurf layers having different amounts of injection. Overlap through.

  In this way, a higher withstand voltage than that of the first embodiment can be obtained by reducing the injection amount in stages. Further, if there is a portion having a relatively low electric field strength in the peripheral portion of the RESURF layer, the FFPs 17 and 18 may not be provided in that portion. For example, if the electric field strength at the peripheral portion of the RESURF layer 4 in FIG. 8A is relatively weak, the FFP 18 may not be provided.

<A-5. Modification 3>
Since the FFP 11 is in a floating state, as shown in FIG. 9, the reliability is improved if the surface of the element is not charged by an external charge. The shield layer 103 is provided with an interval sufficiently larger than the interval (d1) between the drift layer 1 and the FFP 11 separated from the upper portion (d2) of the FFP 11.

  The shield layer 103 may be any of a module package, a metal wiring such as an aluminum wiring of a MOSFET, a semi-insulating silicon nitride film, and a semi-insulating film such as SIPOS (Semi-Insulating Poly-crystalline Silicon).

  Even when the RESURF layers are formed adjacent to each other while being separated, the same effect is obtained.

<A-6. Effect>
According to the first embodiment of the present invention, a semiconductor device includes a drift layer 1 as a first conductivity type semiconductor substrate and an active region of the semiconductor device selectively formed on the surface of the drift layer 1. A base 2 as a first impurity layer of a certain second conductivity type, and a second conductivity type second that is selectively formed on the surface of the drift layer 1 adjacent to the base 2 and has a lower impurity concentration than the base 2. Resurf layers 3 and 12 that are impurity regions, and adjacent to RESURF layers 3 and 12, are selectively formed on the surface of drift layer 1, and have a lower impurity concentration than the RESURF layers 3 and 12. A field plate 9 connected to the base 2 and the drift layer 1 at the boundary between the base 2 and the RESURF layers 3 and 12; Spaced apart and reser By providing the first floating field plate FFP 11 formed on the drift layer 1 at the boundary between the layers 3 and 12 and the RESURF layers 4 and 13 via the insulating layer 8, the intermediate potential is appropriately set. Since the voltage is shared by the FFP 11, higher breakdown voltage can be realized without changing the area of the termination, in other words, the area of the termination can be reduced without reducing the breakdown voltage. In addition, the number of chips that can be manufactured from one wafer is increased, and cost reduction can be expected.

  Further, according to the first embodiment of the present invention, in the semiconductor device, the RESURF layer 12 as the second impurity region is included in the RESURF layer 13 as the third impurity region. The voltage is shared by the FFP 11 thus formed, and a high breakdown voltage semiconductor device can be obtained.

  Further, according to the first embodiment of the present invention, in the semiconductor device, the RESURF as the third impurity region is selectively formed on the surface of the drift layer 1 adjacent to the RESURF layer 4 as the third impurity region. Resurf layer 16 as a second impurity layer of the second conductivity type having a lower impurity concentration than layer 4, and formed on insulating layer 8 on drift layer 1 at the boundary between resurf layer 4 and resurf layer 16. Further, by further providing the FFP 18 as the second floating field plate, a semiconductor device having a higher breakdown voltage can be obtained.

  Also, according to the first embodiment of the present invention, there is provided a semiconductor device, which is a drift layer 1 as a first conductivity type semiconductor substrate, and the activity of the semiconductor device selectively formed on the surface of the drift layer 1. The base 2 as the first impurity layer of the second conductivity type, which is a region, and the second conductivity type that is selectively formed on the surface of the drift layer 1 adjacent to the base 2 and has a lower impurity concentration than the base 2. A resurf layer 100 that is the second impurity region is adjacent to the RESURF layer 100 while being separated from the RESURF layer 100, and is selectively formed on the surface of the drift layer 1, and has a lower impurity concentration than the RESURF layer 100. A resurf layer 101 as an impurity region and a field plate 9 connected to the base 2 and formed on the drift layer 1 at the boundary between the base 2 and the resurf layer 100, and spaced apart from the field plate 9 on a plane By providing the FFP 11 as the first floating field plate formed on the drift layer 1 in the gap portion between the RESURF layer 100 and the RESURF layer 101 via the insulating layer 8, the FFP 11 having an appropriate intermediate potential can be obtained. Therefore, the higher breakdown voltage can be realized without changing the area of the termination portion. In other words, the termination area can be reduced without lowering the breakdown voltage. In addition, the number of chips that can be manufactured from one wafer is increased, and cost reduction can be expected.

  Further, according to the first embodiment of the present invention, in the semiconductor device, the third impurity region is selectively formed on the surface of the drift layer 1 adjacent to the RESURF layer 101 as the third impurity region while being separated from the RESURF layer 101. On the drift layer 1 in the gap between the RESURF layer 101 and the RESURF layer 21 as the third impurity region, and the RESURF layer 21 as the fourth impurity layer of the second conductivity type having a lower impurity concentration than the RESURF layer 101 as Further, an FFP 18 as a second floating field plate formed through the insulating layer 8 is further provided, whereby a semiconductor device having a higher breakdown voltage can be obtained.

  Further, according to the first embodiment of the present invention, in the semiconductor device, the insulating layer 8 thicker than the insulating layer 8 between the drift layer 1 and the floating field plate is provided on the field plate 9 and the floating field plate 11. By further including the formed shield layer 103, the element surface is not charged by the external charge by the shield layer 103, and the reliability is improved.

<B. Second Embodiment>
<B-1. Configuration>
FIG. 10 is a cross-sectional view of the periphery of the semiconductor device of the present invention where the FFP 11 is provided. In FIG. 10 (a), an FFP 32 (overlapping both of the RESURF layer 3 (P−) and the end of the FFP 11 via an insulating layer 8 (not shown) using a metal wiring above the FFP 11 is used. A third floating field plate is provided.

  The role of the FFP 32 is to share the electric field strength at the lower portion (point e) of the FFP 11 tip on the RESURF layer 3 side with the lower portion (point g) of the FFP 32 tip. By providing the FFP 32 in this way, the breakdown voltage can be further improved. The FFP 32 is capacitively coupled to the FFP 11 via the insulating layer 8, and the potential and electric field strength can be adjusted by adjusting the amount of overlap between the FFP 11 and the FFP 32. Note that the final potentials of the FFP 11 and the FFP 32 are determined by capacitive coupling between the FFP 11, the FFP 32, and the substrate surface.

  Further, as shown in FIG. 10B, FFPs 33 that overlap with the insulating layer 8 may be provided on both the RESURF layer 4 (P−−) and the end of the FFP 11. In this case, the electric field strength at the lower part (point f) of the tip of the FFP 11 on the RESURF layer 4 side is shared by the lower part (point h) of the tip of the FFP 33. By providing the FFP 33 in this way, the breakdown voltage can be further improved.

  Further, as shown in FIG. 10C, the wirings 34 and 35 may be connected by a via hole 36 to form the FFP 45. Here, the capacitance value between the FFP 11 and the FFP 45 can be adjusted by the overlap amount of the FFP 11 and the wiring 34. The advantage of this shape is that the number of FFPs can be increased so that the FFP 46 is formed using two metal wiring layers (wirings 37 and 38 are connected by via holes 39). That is, the number of FFP is not limited.

  Further, FFP 47 and FFP 48 may be provided on the RESURF 4 side of the FFP 11. Here, the FFP 47 is formed by connecting the wiring 40 and the wiring 41 through the via hole 42. However, unlike the FFP 48, the wiring 43 and the wiring 44 are not connected through the via hole, so that the FFP 47 and the wiring 44 are connected. The capacitive coupling between them can also be weakened.

  The shape of FIG. 10 is an example, and the shapes shown in FIGS. 10A, 10B, and 10C may be combined. Further, although two metal wiring layers are used in FIG. 10, a shape having a plurality of FFPs that are capacitively coupled to each other using three or more wiring layers may be used.

  Here, as shown in FIG. 10, when a plurality of FFPs are further provided for the FFP 11, not only the electric field intensity at the lower part of the tip of the FFP but also the electric field intensity at other impact points is affected. Therefore, the use of the second embodiment does not necessarily provide a higher breakdown voltage than that of the first embodiment. In order to obtain a higher withstand voltage than in the first embodiment, it is necessary to optimize the injection amount of all the RESURF layers, the overlap amount between the FFP and the RESURF layer, and the overlap amount between the FFPs.

  Even when the RESURF layers are formed adjacent to each other while being separated, the same effect is obtained.

<B-2. Effect>
According to the second embodiment of the present invention, in the semiconductor device, the FFPs 32 and 33 serving as the third floating field plate are formed on the end portion of the FFP 11 serving as the first floating field plate via the insulating layer 8. By further providing, the electric field strength can be shared and the breakdown voltage can be further improved.

<C. Embodiment 3>
<C-1. Configuration>
FIG. 11 is a cross-sectional view showing a terminal portion of the semiconductor device according to the third embodiment of the present invention. The field plates 9 and 10 and the FFP 11 are connected by a shield layer 51 that is a semi-insulating film. The shield layer 51 is formed on the FFP 11 without the insulating layer 8 interposed therebetween. Here, the shield layer 51 has a much higher resistivity than the drift layer 1 that is a semiconductor substrate (the sheet resistance of the shield layer 51 that is a semi-insulating film is, for example, on the order of 10 ¹⁸ Ω / □). Acts as a shield against external charges. Since the FFP 11 is connected to the field plates 9 and 10 through the finite resistance of the shield layer 51, it is not exactly at the floating potential. However, when the time constant determined by the resistance of the shield layer 51 and the capacitance between the FFP 11 and the substrate surface is sufficiently large with respect to the period of voltage change, the potential of the FFP 11 is not fixed and can be regarded as floating.

  Further, like the FFP 11 in FIG. 12A and the FFP 54 in FIG. 12B, the shield layers 52 and 53, which are semi-insulating films, may not be connected. That is, the shield layers 52 and 53 are connected to the field plates 9 and 10 and are formed on the FFPs 11 and 54 via the insulating layer 8. In this case, the FFPs 11 and 54 are completely floating. 12A shows a case where the field plates 9 and 10 and the FFP 11 are formed of the same wiring layer, and FIG. 12B shows a case where the FFP 54 is formed between the wiring layer and the substrate on which the field plates 9 and 10 are formed. The case where it forms with the existing wiring layer is shown.

  Even when the RESURF layers are formed adjacent to each other while being separated, the same effect is obtained.

<C-2. Effect>
According to the third embodiment of the present invention, the semiconductor device is connected to the field plates 9 and 10 and formed on the FFPs 11 and 54 as the first floating field plates with or without the insulating layer 8 interposed therebetween. Further, by providing the semi-insulating shield layers 51, 52, 53, the shield layers 51, 52, 53 function as a shield against external charges, and the reliability is improved.

  1 drift layer, 2 base, 3, 4, 12, 13, 16, 21, 100, 101, 104 RESURF layer, 5 channel stopper, 6 anode electrode, 7 cathode electrode, 8 insulating layer, 9, 10 field plate, 11 , 17, 18, 32, 33, 45, 46, 47, 48, 54 FFP, 34, 35, 37, 38, 40, 41, 43, 44 Wiring, 36, 39, 42 Via hole, 51, 52, 53, 103 Shield layer.

Claims (8)

A semiconductor device,
A first conductivity type semiconductor substrate;
A first impurity layer of a second conductivity type, which is an active region of the semiconductor device, selectively formed on the surface of the semiconductor substrate;
A second impurity region of a second conductivity type, which is selectively formed on the surface of the semiconductor substrate adjacent to the first impurity layer and has a lower impurity concentration than the first impurity layer;
A third impurity region of a second conductivity type, which is selectively formed on the surface of the semiconductor substrate adjacent to the second impurity region and has a lower impurity concentration than the second impurity region;
A first floating field plate formed on the semiconductor substrate at an interface between the second impurity region and the third impurity region via an insulating layer;
Semiconductor device. A field plate connected to the first impurity layer and formed on the semiconductor substrate at a boundary portion between the first impurity layer and the second impurity region;
The first floating field plate is formed to be spaced apart from the field plate on a plane.
The semiconductor device according to claim 1. The second impurity region is included in the third impurity region;
The semiconductor device according to claim 1. A fourth impurity layer of a second conductivity type, which is selectively formed on the surface of the semiconductor substrate adjacent to the third impurity region and has a lower impurity concentration than the third impurity region;
A second floating field plate formed on the semiconductor substrate at the boundary between the third impurity region and the fourth impurity layer via the insulating layer;
The semiconductor device according to any one of claims 1 to 3. A semi-insulating shield layer connected to the field plate and formed on / without the insulating layer on the first floating field plate;
The semiconductor device according to claim 2 . A shield layer formed on the field plate and the first floating field plate via an insulating layer thicker than the insulating layer between the semiconductor substrate and the first floating field plate;
The semiconductor device according to claim 2 . A third floating field plate formed on an end of the first floating field plate via an insulating layer;
The semiconductor device according to any one of claims 1-6. The surface impurity concentration of the second impurity region is 3 to 6 × 10 ¹⁵ cm ⁻³ ;
The surface impurity concentration of the third impurity region is 2-4 × 10 ¹⁵ cm ⁻³ .
The semiconductor device according to any one of claims 1-7.

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