JPH06275852A - High breakdown strength semiconductor device - Google Patents
High breakdown strength semiconductor deviceInfo
- Publication number
- JPH06275852A JPH06275852A JP5833693A JP5833693A JPH06275852A JP H06275852 A JPH06275852 A JP H06275852A JP 5833693 A JP5833693 A JP 5833693A JP 5833693 A JP5833693 A JP 5833693A JP H06275852 A JPH06275852 A JP H06275852A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- semi
- guard ring
- ring region
- potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は高耐圧化のためにガード
リング及び半絶縁膜を有する高耐圧半導体装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high breakdown voltage semiconductor device having a guard ring and a semi-insulating film for increasing the breakdown voltage.
【０００２】[0002]
【従来の技術】従来、高耐圧半導体装置のパッケージ内
に充填されるゲル等の表面保護材や外部からの影響によ
り、ターミネーション部の絶縁膜６上に誘起した電荷が
チップ表面まで影響し、空乏層の伸びを止めてしまい、
その結果阻止耐圧が劣化してしまうという問題があっ
た。この問題を解決するために、電界シールド層として
半絶縁膜８が用いられている。このような高耐圧半導体
装置の一例として、特開昭50−115479号公報に記載の従
来の装置を図２に示す。Ｎ型シリコン基板１に拡散によ
って形成されたＰ型のガードリング領域２が形成されて
いる。また、Ｎ型シリコン基板１の縁部にはＮ型チャネ
ルストッパー領域５が形成されている。Ｐ型のガードリ
ング領域２とＮ型チャネルストッパー領域５の間のＮ型
シリコン基板１の表面上にはＳｉＯ2 ，Ａｌ2Ｏ3等の絶
縁膜６が覆っている。Ｐ型のガードリング領域２および
Ｎ型チャネルストッパー領域５にはＡＬ等の導電材料の
電極４が接触し、Ｐ型のガードリング領域２から絶縁膜
６の上を覆ってシリコン表面の電荷を緩和するためのＳ
ｉＣ，ＫＡｓ，Ｓｉ，Ｇｅまたはアモルファスまたは多
結晶のアンチモン硫化物等の半絶縁膜８がチップ外周に
向かって伸び、Ｎ型チャネルストッパー領域５に電極４
を介して接触している。2. Description of the Related Art Conventionally, due to a surface protective material such as gel filled in a package of a high breakdown voltage semiconductor device or an influence from the outside, an electric charge induced on an insulating film 6 of a termination portion influences the surface of a chip, resulting in depletion. Stops the growth of layers,
As a result, there is a problem that the blocking breakdown voltage is deteriorated. In order to solve this problem, the semi-insulating film 8 is used as the electric field shield layer. As an example of such a high breakdown voltage semiconductor device, a conventional device described in Japanese Patent Laid-Open No. 50-115479 is shown in FIG. A P-type guard ring region 2 formed by diffusion is formed on an N-type silicon substrate 1. Further, an N-type channel stopper region 5 is formed at the edge of the N-type silicon substrate 1. An insulating film 6 of SiO 2 , Al 2 O 3 or the like is covered on the surface of the N-type silicon substrate 1 between the P-type guard ring region 2 and the N-type channel stopper region 5. An electrode 4 made of a conductive material such as AL is in contact with the P-type guard ring region 2 and the N-type channel stopper region 5 to cover the insulating film 6 from the P-type guard ring region 2 and relax the electric charge on the silicon surface. S to do
A semi-insulating film 8 such as iC, KAs, Si, Ge or amorphous or polycrystalline antimony sulfide extends toward the outer periphery of the chip, and an electrode 4 is formed in the N-type channel stopper region 5.
Are in contact through.
【０００３】[0003]
【発明が解決しようとする課題】上記従来構造では、図
２に示すようにＮ型シリコン基板１の表面電位に対して
負電位がフィールドプレート効果を与え、ＰＮ接合に広
がる空乏層１０および１１が表面においてＮ層側のみに
拡張される。空乏層１０および１１がＮ層のみに大きく
広がると、阻止耐圧を確保するためにガードリング領域
２とチャネルストッパー５の間隔を広げることや、Ｎ型
シリコン基板１の比抵抗を上げる必要があるが、ガード
リング領域２とチャネルストッパー５の間隔を広げると
チップ寸法が大きくなり、コストが上がってしまう。ま
た、Ｎ型シリコン基板１の比抵抗を上げると、チップの
抵抗分が増加し、素子の特性を犠牲にしてしまうという
問題があった。本発明の目的は、上述の問題を解決して
Ｎ型シリコン基板１の比抵抗を上げたりガードリング領
域２とチャネルストッパー５の間隔を広げることなく、
空乏層１０および１１のＮ層側への伸びを抑制し、高耐
圧を確保する高耐圧半導体装置を提供することにある。In the above conventional structure, as shown in FIG. 2, the negative potential exerts a field plate effect on the surface potential of the N-type silicon substrate 1, and the depletion layers 10 and 11 spreading in the PN junction are formed. Only the N layer side is expanded on the surface. If the depletion layers 10 and 11 spread greatly only in the N layer, it is necessary to widen the interval between the guard ring region 2 and the channel stopper 5 and increase the specific resistance of the N-type silicon substrate 1 in order to secure the blocking breakdown voltage. Increasing the distance between the guard ring region 2 and the channel stopper 5 increases the chip size and increases the cost. Further, if the specific resistance of the N-type silicon substrate 1 is increased, the resistance of the chip is increased, and the characteristics of the element are sacrificed. An object of the present invention is to solve the above-mentioned problems and to increase the specific resistance of the N-type silicon substrate 1 or to widen the interval between the guard ring region 2 and the channel stopper 5,
An object of the present invention is to provide a high breakdown voltage semiconductor device that suppresses the expansion of the depletion layers 10 and 11 toward the N layer side and secures a high breakdown voltage.
【０００４】[0004]
【課題を解決するための手段】上述の問題を達成するた
めに、図１に示す本発明はＮ型シリコン基板１の両主表
面に主電極を備え、一面のＮ型のシリコン基板１の表面
にＰ型の第一のガードリング領域２が選択的に形成さ
れ、第一のガードリング領域２より低濃度のＰ型の第二
のガードリング領域３が、前記第一のガードリング領域
２に接して形成され、他面の主電極と同電位になる縁部
側への基板表面部にチャネルストッパー領域５が選択的
に形成され、前記ガードリング領域２および３を形成し
た主表面上に第一の絶縁膜６を有し、この第一の絶縁膜
６上が半絶縁膜８で覆われた高耐圧半導体装置におい
て、前記第二のガードリング領域３の主表面のＰＮ接合
での電位と同位置での前記半絶縁膜８の電位を一致させ
且つＰ側，Ｎ側両方にフィールドプレート効果を持たせ
るように半絶縁膜８上の電位分布即ち抵抗率分布を調整
する。具体的には、Ｐ型層側では半絶縁膜８上の電位を
Ｎ型シリコン基板１の表面よりも高く、Ｎ型層側では半
絶縁膜８上の電位をＮ型シリコン基板１の表面よりも低
くしておくことで目的を実現できる。また、この半絶縁
膜８の上に応力を吸収可能な絶縁膜７が設けられること
が有効である。半絶縁膜８はプラズマCVD法またはμ波
ＣＶＤ法で形成されたＳｉＮまたはＳｉＯであり、半絶
縁膜８の横方向の抵抗分布の制御はＯ2あるいはＮ2によ
るイオン打ち込みにより調整可能である。In order to achieve the above-mentioned problems, the present invention shown in FIG. 1 has main electrodes on both main surfaces of an N-type silicon substrate 1, and the surface of one N-type silicon substrate 1 is provided. A P-type first guard ring region 2 is selectively formed in the first guard ring region 2, and a P-type second guard ring region 3 having a lower concentration than the first guard ring region 2 is formed in the first guard ring region 2. A channel stopper region 5 is selectively formed on the substrate surface portion which is formed in contact with the other surface and has the same potential as the main electrode on the other surface, and the channel stopper region 5 is formed on the main surface on which the guard ring regions 2 and 3 are formed. In the high breakdown voltage semiconductor device having one insulating film 6 and the first insulating film 6 covered with the semi-insulating film 8, the potential at the PN junction on the main surface of the second guard ring region 3 is At the same position, the potentials of the semi-insulating film 8 are made to be the same, and both the P side and the N side are So as to have a I over field plate effect to adjust the potential distribution i.e. resistivity distribution on the semi-insulating film 8. Specifically, the potential on the semi-insulating film 8 is higher than that on the surface of the N-type silicon substrate 1 on the P-type layer side, and the potential on the semi-insulating film 8 is higher than that on the N-type silicon substrate 1 on the N-type layer side. The purpose can be achieved by keeping it low. Further, it is effective that the insulating film 7 capable of absorbing stress is provided on the semi-insulating film 8. The semi-insulating film 8 is SiN or SiO formed by the plasma CVD method or the μ wave CVD method, and the lateral resistance distribution of the semi-insulating film 8 can be controlled by ion implantation with O 2 or N 2 .
【０００５】[0005]
【作用】前記第二のガードリング領域３のＮ型シリコン
基板１の表面のＰＮ接合での電位と、これと同位置での
半絶縁膜８の電位を一致させることにより、第二のガー
ドリング領域３のＮ型シリコン基板１の表面を境にして
ＰＮ接合のＰ層，Ｎ層共に空乏層１０および１１が広が
るので、ガードリング領域２とチャネルストッパー５の
間隔を広げたり、Ｎ型シリコン基板１の比抵抗を高くす
ることなく、高耐圧化を実現できる。この時の半絶縁膜
８上の電位とＮ型シリコン基板１の表面の電位は図１に
示すように、半絶縁膜８上の電位がＮ型シリコン基板１
の表面の電位に対してＰ層上では高く、Ｎ層上では低く
しておく。したがって、フィールドプレートの効果がＰ
層，Ｎ層の両方に作用しその結果、空乏層１０および１
１がＰＮ接合のＰ層，Ｎ層の両方に広がる。Ｐ層側へも
空乏層１０を伸ばすことにより、同じ耐圧を得るための
Ｎ層への空乏層１１の伸びを抑制できるのでＮ型シリコ
ン基板１の不純物濃度を従来よりも高くすることができ
る。これにより、素子のバルク特性を犠牲にすることな
く、耐圧を確保できる。また、Ｎ型シリコン基板１の不
純物濃度を高くできることで、シリコン表面に存在する
界面電荷の影響を受けにくい安定した阻止特性が得られ
る。また、半絶縁膜８は、例えば抵抗の調整が可能なＰ
−ＳｉＮ膜またはＰ−ＳｉＯ膜で形成することにより電
界をシールドでき、空乏層１０および１１のＮ型シリコ
ン基板１の表面に平行な広がりに対する半絶縁膜８上の
表面保護材中などの電荷の影響を防止することができ
る。また、この半絶縁膜８の材料が応力に対して不向き
な場合、この膜上に応力を吸収することのできる第二の
絶縁膜７を積層すれば半絶縁膜８にクラックが生じるの
を防止できる。By matching the potential at the PN junction on the surface of the N-type silicon substrate 1 in the second guard ring region 3 with the potential at the semi-insulating film 8 at the same position, the second guard ring is formed. Since the depletion layers 10 and 11 spread in both the P layer and the N layer of the PN junction with the surface of the N-type silicon substrate 1 in the region 3 as a boundary, the gap between the guard ring region 2 and the channel stopper 5 can be widened, or the N-type silicon substrate can be formed. High breakdown voltage can be realized without increasing the specific resistance of 1. At this time, the potential on the semi-insulating film 8 and the potential on the surface of the N-type silicon substrate 1 are as shown in FIG.
The potential on the surface of P is high on the P layer and low on the N layer. Therefore, the effect of the field plate is P
Acting on both the N and N layers, resulting in depletion layers 10 and 1
1 spreads on both the P and N layers of the PN junction. By extending the depletion layer 10 to the P layer side as well, the extension of the depletion layer 11 to the N layer for obtaining the same breakdown voltage can be suppressed, so that the impurity concentration of the N-type silicon substrate 1 can be made higher than before. Thereby, the breakdown voltage can be secured without sacrificing the bulk characteristics of the device. In addition, since the impurity concentration of the N-type silicon substrate 1 can be increased, stable blocking characteristics that are not easily influenced by the interface charges existing on the silicon surface can be obtained. Further, the semi-insulating film 8 is made of, for example, P whose resistance can be adjusted.
The -SiN film or the P-SiO film can shield an electric field, and the depletion layers 10 and 11 can spread charges parallel to the surface of the N-type silicon substrate 1 in the surface protective material on the semi-insulating film 8 and the like. The influence can be prevented. When the material of the semi-insulating film 8 is unsuitable for stress, the second insulating film 7 capable of absorbing the stress is laminated on the film to prevent the semi-insulating film 8 from being cracked. it can.
【０００６】[0006]
【実施例】図１は本発明の一実施例を示す。半導体素体
は図２と同様であるが、本発明は、ガードリング領域を
濃度の高い領域２と低い領域３の２つの拡散層を形成す
ることにより、ガードリング領域の角部での電界の高い
部分を緩和するようにしている。半絶縁膜８は、第一の
ガードリング領域２およびチャネルストッパー５にもＡ
Ｌ電極４により接触している。半絶縁膜８の上にはパッ
シベーション用として低温で生成されたＳｉＯ2 あるい
はＳｉＮより形成される第二の絶縁膜７が覆っている。
このような構造をもつ半導体装置は樹脂製のパッケージ
の中に入れられ、空間には例えばゲルのような表面保護
材が充填されている。Ｎ型シリコン基板１の表面電位と
半絶縁膜８上の電位の関係は、第二のガードリング領域
３の主表面のＰＮ接合での電位とこれと同位置での前記
半絶縁膜８の電位を一致させ且つＰ側，Ｎ側両方にフィ
ールドプレート効果を持たせるようにＰ型層側では半絶
縁膜８上の電位をＮ型シリコン基板１の表面よりも高
く、Ｎ型層側では半絶縁膜８上の電位をＮ型シリコン基
板１の表面よりも低くする。FIG. 1 shows an embodiment of the present invention. Although the semiconductor element body is similar to that of FIG. 2, the present invention forms two diffusion layers of a high concentration region 2 and a low concentration region 3 in the guard ring region, so that the electric field at the corners of the guard ring region is I try to alleviate the high part. The semi-insulating film 8 is formed on the first guard ring region 2 and the channel stopper 5 as well.
The L electrode 4 makes contact. The semi-insulating film 8 is covered with a second insulating film 7 made of SiO 2 or SiN generated at low temperature for passivation.
The semiconductor device having such a structure is placed in a resin package, and the space is filled with a surface protective material such as gel. The relationship between the surface potential of the N-type silicon substrate 1 and the potential on the semi-insulating film 8 is the potential at the PN junction on the main surface of the second guard ring region 3 and the potential of the semi-insulating film 8 at the same position. And the field plate effect is provided on both the P side and the N side, the potential on the semi-insulating film 8 is higher than that on the surface of the N-type silicon substrate 1 on the P-type layer side, and semi-insulating on the N-type layer side. The potential on the film 8 is made lower than that on the surface of the N-type silicon substrate 1.
【０００７】図３は本発明のフィールドプレート効果を
さらに高めた他の一実施例を示す。半絶縁膜８の抵抗率
を図に示すように第二のガードリング領域３の端部上を
境に例えばＯ2あるいはＮ2を選択的にイオン打ち込みす
ることにより、左右で抵抗率に分布を持たせる。即ち、
半絶縁膜８上の電位を図１の構造に比べＰ型層側では高
く、Ｎ型層側では低くする。これにより、フィールドプ
レート効果を図１の本発明の構造よりさらに向上させる
ことができる。FIG. 3 shows another embodiment in which the field plate effect of the present invention is further enhanced. As shown in the figure, the resistivity of the semi-insulating film 8 is selectively ion-implanted with, for example, O 2 or N 2 at the end of the second guard ring region 3 as a boundary so that the resistivity is distributed on the left and right sides. To have. That is,
The potential on the semi-insulating film 8 is set higher on the P-type layer side and lower on the N-type layer side than in the structure of FIG. As a result, the field plate effect can be further improved as compared with the structure of the present invention shown in FIG.
【０００８】図４は本発明の一実施例の高耐圧半導体装
置の製造方法の一例を示す。まず、（ａ）シリコン基板
１上に熱酸化により膜厚が２μｍのＳｉＯ2 からなる第
一の絶縁膜６を全面に形成し、その後、二度のフォトエ
ッチングにより、Ａ部の第一の絶縁膜６を全て取り除
き、Ｂ部の第一の絶縁膜６を、この後の第二のガードリ
ング領域３にイオン打ち込みのできる例えば残り膜厚が
０.５μｍ までエッチングする。次に、（ｂ）フォトレ
ジストをマスクとし、横方向寸法が６５μｍの第一のガ
ードリング領域２に例えばボロンをイオン打ち込み後、
拡散し、この第一のガードリング領域２に接するように
横方向寸法が５０μｍ第二のガードリング領域３を同様
に形成する。この第二のガードリング領域３は第一のガ
ードリング領域２より縦方向の深さが浅く、且つ濃度が
低い。次に、チャネルストッパー５は、例えばリンまた
は砒素をイオン打ち込み後、拡散して形成する。第二の
ガードリング領域３とチャネルストッパー５との間の横
方向寸法は１００μｍである。次に（ｃ）シリコン基板
の上に膜厚が３μｍのＡＬ電極４をスパッタ法により堆
積し、フォトエッチングによりパターニングする。次に
(ｄ)ＡＬ電極４および第一の絶縁膜６の上を例えばプラ
ズマＣＶＤによるＰ−ＳｉＮからなる厚さが例えば１μ
ｍの半絶縁膜８を堆積し、部分的にフォトエッチングす
る。半絶縁膜８の材料であるＳｉＮは反応ガスのＳｉＨ
4とＮＨ3の混合比を変えることにより比抵抗をコントロ
ールすることができる。ＳｉＨ4の比率を上げると組成
ＳｉXＮYのＸが大きく、低抵抗化し、ＮＨ3 の比率を上
げると組成ＳｉXＮYのＹが大きくなり高抵抗化となる。
半絶縁膜８の抵抗率は１０7〜１０9Ω・cmの範囲に入る
ようにすれば成膜が容易であり且つ実用的な特性が得ら
れる。この半絶縁膜８は外部、例えばパッケージ注入レ
ジンであるシリコーンゲル中の可動イオンの影響をシー
ルドでき、且つパッシベーション膜としても利用でき
る。次に半絶縁膜８の上に膜厚が１μｍの第二の絶縁膜
７を堆積する。第二の絶縁膜７は半絶縁膜８より軟らか
く、応力を緩和でき、且つ外部からの湿気に対して有効
な耐湿性の高い材料、例えばＰＩＱやＰＳＧなどを用い
る。最後に、シリコン基板１の裏面にドレイン電極９を
形成する。FIG. 4 shows an example of a method of manufacturing a high breakdown voltage semiconductor device according to an embodiment of the present invention. First, (a) a first insulating film 6 made of SiO 2 and having a film thickness of 2 μm is formed on the entire surface of the silicon substrate 1 by thermal oxidation, and then the first insulating film of the portion A is formed by photoetching twice. The film 6 is completely removed, and the first insulating film 6 in the B portion is etched to a subsequent film thickness of 0.5 μm, for example, where ions can be implanted into the second guard ring region 3 thereafter. Next, (b) after ion-implanting, for example, boron into the first guard ring region 2 having a lateral dimension of 65 μm using the photoresist as a mask,
A second guard ring region 3 having a lateral dimension of 50 μm is similarly formed so as to diffuse and contact the first guard ring region 2. The second guard ring region 3 has a shallower depth in the vertical direction and a lower concentration than the first guard ring region 2. Next, the channel stopper 5 is formed by ion-implanting phosphorus or arsenic and then diffusing it. The lateral dimension between the second guard ring region 3 and the channel stopper 5 is 100 μm. Next, (c) an AL electrode 4 having a film thickness of 3 μm is deposited on the silicon substrate by a sputtering method and patterned by photoetching. next
(d) A thickness of, for example, P-SiN formed by plasma CVD on the AL electrode 4 and the first insulating film 6 is, for example, 1 μm.
m semi-insulating film 8 is deposited and partially photoetched. SiN which is a material of the semi-insulating film 8 is SiH which is a reaction gas.
The specific resistance can be controlled by changing the mixing ratio of 4 and NH 3 . If the ratio of SiH 4 is increased, the X of the composition Si X N Y is large and the resistance is lowered, and if the ratio of NH 3 is increased, the Y of the composition Si X N Y is increased and the resistance is increased.
If the resistivity of the semi-insulating film 8 is set within the range of 10 7 to 10 9 Ω · cm, film formation is easy and practical characteristics are obtained. The semi-insulating film 8 can shield the influence of mobile ions in the outside, for example, silicone gel, which is a package injection resin, and can also be used as a passivation film. Next, a second insulating film 7 having a film thickness of 1 μm is deposited on the semi-insulating film 8. The second insulating film 7 is made of a material that is softer than the semi-insulating film 8 and can relieve stress and is highly resistant to moisture from the outside, such as PIQ or PSG. Finally, the drain electrode 9 is formed on the back surface of the silicon substrate 1.
【０００９】図５は本発明の他の実施例を示す。図１の
実施例の第二のガードリング領域３に接する第三のガー
ドリング領域１２を設ける。この第三のガードリング領
域１２の拡散層の濃度は、第二のガードリング領域３よ
りさらに低く、縦方向の深さは、第二のガードリング領
域３よりさらに浅く形成する。この構造により、図１の
構造に比べ横方向へ空乏層を伸ばし易くし、高耐圧を得
る。FIG. 5 shows another embodiment of the present invention. A third guard ring region 12 is provided in contact with the second guard ring region 3 of the embodiment shown in FIG. The concentration of the diffusion layer in the third guard ring region 12 is lower than that in the second guard ring region 3 and the depth in the vertical direction is shallower than that in the second guard ring region 3. With this structure, the depletion layer can be extended in the lateral direction more easily than in the structure of FIG. 1, and a high breakdown voltage can be obtained.
【００１０】図６は本発明の他の実施例を示す。図１の
実施例の構造の第二のガードリング領域３の内部に新た
に第四のガードリング領域１３を設ける。この第四のガ
ードリング領域１３の拡散層の濃度は、第二のガードリ
ング領域３より高く、縦方向の深さは、第二のガードリ
ング領域３より浅く形成する。図１の構造で電界の比較
的高い箇所の一つに第一のガードリング領域２と第二の
ガードリング領域３がシリコン基板内部で交差する部分
があり、図５の構造は、この部分の電界を緩和する方向
に働き、高耐圧を確保するものである。FIG. 6 shows another embodiment of the present invention. A fourth guard ring region 13 is newly provided inside the second guard ring region 3 of the structure of the embodiment shown in FIG. The concentration of the diffusion layer in the fourth guard ring region 13 is higher than that in the second guard ring region 3, and the depth in the vertical direction is shallower than that in the second guard ring region 3. In the structure of FIG. 1, there is a portion where the first guard ring region 2 and the second guard ring region 3 intersect inside the silicon substrate at one of the places where the electric field is relatively high. It works to relax the electric field and ensures a high breakdown voltage.
【００１１】図７は本発明の他の実施例を示す。図６の
構造の第二のガードリング領域３の横方向寸法をやや長
くし、この第二のガードリング領域３の内部に新たに第
五のガードリング領域１４を設けたものである。この第
五のガードリング領域１４の拡散層の濃度は、第二のガ
ードリング領域３より高く、且つ第四のガードリング領
域１３より低い。縦方向の深さは、第四のガードリング
領域１４とほぼ同様である。この構造により、第四のガ
ードリング領域１３の角部で電界が高くなるのを抑え、
空乏層を第五のガードリング領域１４まで伸ばすことに
より、高耐圧を実現する。FIG. 7 shows another embodiment of the present invention. In the structure shown in FIG. 6, the lateral dimension of the second guard ring region 3 is slightly lengthened, and a fifth guard ring region 14 is newly provided inside the second guard ring region 3. The concentration of the diffusion layer in the fifth guard ring region 14 is higher than that in the second guard ring region 3 and lower than that in the fourth guard ring region 13. The depth in the vertical direction is almost the same as that of the fourth guard ring region 14. With this structure, it is possible to prevent the electric field from increasing at the corners of the fourth guard ring region 13,
A high breakdown voltage is realized by extending the depletion layer to the fifth guard ring region 14.
【００１２】[0012]
【発明の効果】本発明によれば、第二のガードリング領
域３のＮ型シリコン基板１の表面のＰＮ接合での電位
と、これと同位置での半絶縁膜８の電位を一致させ且つ
Ｐ側，Ｎ側両方にフィールドプレート効果を持たせるよ
うに半絶縁膜上の電位分布、即ち抵抗率分布を調整する
ことにより、第二のガードリング領域３のＮ型シリコン
基板１の表面を境にしてＰＮ接合のＰ層，Ｎ層共に空乏
層１０，１１が広がるので、第二のガードリング領域３
とチャネルストッパー５の間隔を広げたり、Ｎ型シリコ
ン基板１の比抵抗を高くすることなく、高耐圧化が可能
となる。また、半絶縁膜８は例えば、抵抗の調整が可能
なＰ−ＳｉＮ膜またはＰ−ＳｉＯ膜で形成することによ
り電界をシールドでき、空乏層１０および１１のＮ型シ
リコン基板１の表面に平行広がりに対する半絶縁膜８上
の表面保護材１２中などの電荷の影響を防止することが
できる。また、この半絶縁膜８の材料が応力に対して不
向きな場合、この膜上に応力を吸収することのできる第
二の絶縁膜７を積層することにより半絶縁膜８にクラッ
クが生じるのを防止できる。本発明により阻止耐圧は同
じシリコン基板で従来構造より１００Ｖ高い７００Ｖを
得ることができる。また、ターミネーション領域の横方
向寸法は従来の８５％に縮小できる。According to the present invention, the potential at the PN junction on the surface of the N-type silicon substrate 1 in the second guard ring region 3 and the potential at the semi-insulating film 8 at the same position are made equal to each other. By adjusting the potential distribution on the semi-insulating film, that is, the resistivity distribution so that both the P side and the N side have the field plate effect, the surface of the N type silicon substrate 1 in the second guard ring region 3 is bounded. Since the depletion layers 10 and 11 spread in both the P and N layers of the PN junction, the second guard ring region 3
The breakdown voltage can be increased without widening the interval between the channel stopper 5 and the channel stopper 5 or increasing the specific resistance of the N-type silicon substrate 1. Further, the semi-insulating film 8 can shield an electric field by being formed of, for example, a P-SiN film or a P-SiO film whose resistance can be adjusted, and the depletion layers 10 and 11 extend in parallel with the surface of the N-type silicon substrate 1. It is possible to prevent the influence of charges in the surface protective material 12 on the semi-insulating film 8 and the like. Further, when the material of the semi-insulating film 8 is unsuitable for stress, it is possible to prevent the semi-insulating film 8 from being cracked by laminating the second insulating film 7 capable of absorbing stress on the film. It can be prevented. According to the present invention, 700V, which is 100V higher than that of the conventional structure, can be obtained with the same breakdown voltage on the same silicon substrate. Also, the lateral dimension of the termination region can be reduced to 85% of the conventional size.
【図１】本発明の一実施例のターミネーション部の断面
図である。FIG. 1 is a cross-sectional view of a termination unit according to an embodiment of the present invention.
【図２】従来のターミネーション部の断面図である。FIG. 2 is a cross-sectional view of a conventional termination unit.
【図３】本発明の改良例を示す図である。FIG. 3 is a diagram showing an improved example of the present invention.
【図４】本発明の一実施例の製造方法の断面図である。FIG. 4 is a cross-sectional view of the manufacturing method of the embodiment of the present invention.
【図５】本発明の他の実施例（１）を示す図である。FIG. 5 is a diagram showing another embodiment (1) of the present invention.
【図６】本発明の他の実施例（２）を示す図である。FIG. 6 is a diagram showing another embodiment (2) of the present invention.
【図７】本発明の他の実施例（３）を示す図である。FIG. 7 is a diagram showing another embodiment (3) of the present invention.
１…Ｎ型シリコン基板、２…第一のガードリング領域、
３…第二のガードリング領域、４…ＡＬ電極、５…チャ
ネルストッパー、６…第一の絶縁膜、７…第二の絶縁
膜、８…半絶縁膜、９…ドレイン電極、１０…Ｐ側に広
がる空乏層、１１…Ｎ側に広がる空乏層、１２…第三の
ガードリング領域、１３…第四のガードリング領域、１
４…第五のガードリング領域。1 ... N-type silicon substrate, 2 ... First guard ring region,
3 ... Second guard ring region, 4 ... AL electrode, 5 ... Channel stopper, 6 ... First insulating film, 7 ... Second insulating film, 8 ... Semi-insulating film, 9 ... Drain electrode, 10 ... P side , A depletion layer extending to the N side, 12 ... A third guard ring region, 13 ... A fourth guard ring region, 1
4 ... Fifth guard ring area.
Claims (5)
面の第一導電型の半導体基板の表面に第二導電型の第一
のガードリング領域が選択的に形成され、第一のガード
リング領域より低濃度の第二導電型の第二のガードリン
グ領域が、前記第一のガードリング領域に接して形成さ
れ、他面の主電極と同電位になる縁部側への基板表面部
に前記半導体基板と同一導電型の第三のガードリング領
域が選択的に形成され、前記ガードリング領域を形成し
た主表面上に第一の絶縁膜を有し、この第一の絶縁膜上
を半絶縁膜で覆った高耐圧半導体装置において、前記第
二のガードリング領域の主表面のＰＮ接合での電位と、
同位置での前記半絶縁膜の電位が一致し、Ｐ型半導体上
では半導体表面に比べ半絶縁膜上の電位を高く、Ｎ型半
導体上では半導体表面に比べ半絶縁膜上の電位を低くし
たことを特徴とする高耐圧半導体装置。1. A main electrode is provided on both main surfaces of a semiconductor substrate, and a second conductivity type first guard ring region is selectively formed on the surface of one surface of the first conductivity type semiconductor substrate. The second guard ring region of the second conductivity type having a concentration lower than that of the guard ring region is formed in contact with the first guard ring region, and the substrate surface to the edge side which has the same potential as the main electrode on the other surface. A third guard ring region of the same conductivity type as that of the semiconductor substrate is selectively formed in the portion, and a first insulating film is provided on the main surface on which the guard ring region is formed. In a high withstand voltage semiconductor device in which is covered with a semi-insulating film, a potential at a PN junction on the main surface of the second guard ring region,
The potentials of the semi-insulating film at the same position are the same, the potential on the semi-insulating film is higher on the P-type semiconductor than on the semiconductor surface and lower on the N-type semiconductor than on the semiconductor surface. A high breakdown voltage semiconductor device characterized by the above.
０7〜１０9Ω・cmであることを特徴とする高耐圧半導体
装置。2. The semi-insulating film having a resistivity of 1 according to claim 1.
A high voltage semiconductor device having a resistance of 0 7 to 10 9 Ω · cm.
吸収可能な絶縁膜が設けられたことを特徴とする高耐圧
半導体装置。3. A high breakdown voltage semiconductor device according to claim 1, wherein an insulating film capable of absorbing stress is provided on the semi-insulating film.
ＶＤ法またはμ波ＣＶＤ法で形成されたＳｉＮまたはＳ
ｉＯであることを特徴とする高耐圧半導体装置。4. The semi-insulating film according to claim 1, wherein the semi-insulating film is plasma C
SiN or S formed by VD method or μ wave CVD method
A high voltage semiconductor device characterized by being iO.
制御にＯ2あるいはＮ2によるイオン打ち込みによって行
われることを特徴とする高耐圧半導体装置。5. The high breakdown voltage semiconductor device according to claim 1, wherein the resistance distribution of the semi-insulating film is controlled by ion implantation with O 2 or N 2 .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5833693A JPH06275852A (en) | 1993-03-18 | 1993-03-18 | High breakdown strength semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5833693A JPH06275852A (en) | 1993-03-18 | 1993-03-18 | High breakdown strength semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06275852A true JPH06275852A (en) | 1994-09-30 |
Family
ID=13081482
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5833693A Pending JPH06275852A (en) | 1993-03-18 | 1993-03-18 | High breakdown strength semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06275852A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001036085A (en) * | 1999-06-28 | 2001-02-09 | Intersil Corp | Edge end portion for silicon power device |
| US6316794B1 (en) | 1998-04-22 | 2001-11-13 | Fuji Electric Co., Ltd. | Lateral high voltage semiconductor device with protective silicon nitride film in voltage withstanding region |
| JP2007173705A (en) * | 2005-12-26 | 2007-07-05 | Toyota Central Res & Dev Lab Inc | Nitride semiconductor device |
| DE102009023417A1 (en) | 2008-09-05 | 2010-06-24 | Mitsubishi Electric Corp. | Method for producing a semiconductor device |
| JP2011199223A (en) * | 2010-03-24 | 2011-10-06 | Mitsubishi Electric Corp | Semiconductor device |
| KR101311537B1 (en) * | 2011-09-23 | 2013-09-25 | 주식회사 케이이씨 | Semiconductor device |
| JP2017092360A (en) * | 2015-11-16 | 2017-05-25 | 富士電機株式会社 | Semiconductor device |
-
1993
- 1993-03-18 JP JP5833693A patent/JPH06275852A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6316794B1 (en) | 1998-04-22 | 2001-11-13 | Fuji Electric Co., Ltd. | Lateral high voltage semiconductor device with protective silicon nitride film in voltage withstanding region |
| US6558983B2 (en) | 1998-04-22 | 2003-05-06 | Fuji Electric Co., Ltd. | Semiconductor apparatus and method for manufacturing the same |
| JP2001036085A (en) * | 1999-06-28 | 2001-02-09 | Intersil Corp | Edge end portion for silicon power device |
| JP2007173705A (en) * | 2005-12-26 | 2007-07-05 | Toyota Central Res & Dev Lab Inc | Nitride semiconductor device |
| DE102009023417A1 (en) | 2008-09-05 | 2010-06-24 | Mitsubishi Electric Corp. | Method for producing a semiconductor device |
| US8377832B2 (en) | 2008-09-05 | 2013-02-19 | Mitsubishi Electric Corporation | Method for manufacturing semiconductor device |
| JP2011199223A (en) * | 2010-03-24 | 2011-10-06 | Mitsubishi Electric Corp | Semiconductor device |
| KR101311537B1 (en) * | 2011-09-23 | 2013-09-25 | 주식회사 케이이씨 | Semiconductor device |
| JP2017092360A (en) * | 2015-11-16 | 2017-05-25 | 富士電機株式会社 | Semiconductor device |
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