JP3997551B2 - Planar type semiconductor device - Google Patents

Planar type semiconductor device Download PDF

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JP3997551B2
JP3997551B2 JP31995095A JP31995095A JP3997551B2 JP 3997551 B2 JP3997551 B2 JP 3997551B2 JP 31995095 A JP31995095 A JP 31995095A JP 31995095 A JP31995095 A JP 31995095A JP 3997551 B2 JP3997551 B2 JP 3997551B2
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type region
semiconductor device
impurity
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JPH09162422A (en
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貴之 岩崎
大助 川瀬
俊之 大野
勉 八尾
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Hitachi Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、プレーナ型半導体装置に関する。
【０００２】
【従来の技術】
従来の高耐圧プレーナ型のｐｎ接合ダイオードを図２に示す。図２においてｎ型Ｓｉ基板１０上にエピタキシャル成長させたｎ型Ｓｉ膜１を形成し、ｎ型Ｓｉ膜１表面に拡散またはイオン注入によってｐ+ 型領域２が形成され、その周囲にｐ+ 型領域２より低濃度で浅い構造のｐ- 型領域５が形成されている。ｐ- 型領域５を浅い構造にすることにより、電界緩和の効果をより高めることができる。ｐ+ 型領域２にはＡｌ等の導電材料の電極３が接触している。このような高耐圧半導体装置の一例として、特開平5−63213号公報に記載のものがある。
【０００３】
【発明が解決しようとする課題】
上記従来の技術では、温度が変動すると、不純物の活性化率が変化してｐ- 型領域５のキャリア濃度が変化する。このため、室温において所望の耐圧が得られるようにｐ- 型領域５の不純物濃度を設定しても、高温になるとキャリア濃度が高くなるため、ｐ- 型領域５内の空乏層の広がり状態が変化して耐圧が低下するという問題が有る。
【０００４】
本発明は、このような問題を考慮してなされたものであり、広い温度範囲で高耐圧を安定して得られるプレーナ型半導体装置を提供する。
【０００５】
【課題を解決するための手段】
上記課題を達成するために、本発明は第１導電型の第１の領域と、第１の領域に隣接する第２導電型の第２の領域と、一対の主電極とを備え、一方の主電極が第２の領域と接触するプレーナ型半導体装置において、第１導電型の第１の領域の表面に高不純物濃度の第２導電型の第２の領域が形成され、該第２の領域の周囲に第２の領域より浅く不純物濃度が低い構造の第２導電型の第３の領域が形成され、第３の領域の周囲に第３の領域と同じ深さの、又は浅く不純物濃度が低い構造の第２導電型の第４の領域が形成されていて、かつ、第４の領域には第３の領域に注入した不純物より不純物準位が深く、活性化率が低い不純物を注入したことを特徴とするものである。
【０００６】
上記複数の領域に含まれる不純物の不純物準位が異なっているので、各領域ごとに不純物の活性化率が異なる。従って、ある温度範囲では複数の領域のうちのある領域が所望の耐圧を得るために好ましいキャリア濃度値になり、他の温度範囲では他の領域が好ましいキャリア濃度値になるようにすることが可能になる。すなわち、ｐｎ接合のターミネーション部における第２導電型の半導体層のキャリア濃度を広い温度範囲にわたって、所望の耐圧が得られるような値にすることができる。
【０００７】
なお、第１導電型及び第２導電型は、それぞれｐ型またはｎ型であり、かつ互いに反対の導電型である。
【０００８】
【発明の実施の形態】
図１は本発明の一実施例を示す。本図は、プレーナ型半導体装置のターミネーションを示す。なお、半導体装置としては、トランジスタやダイオード等種々のものがある。ｎ型ＳｉＣ基板１０上にエピタキシャル成長させたｎ型ＳｉＣ膜１が形成される。このｎ型ＳｉＣ膜１表面に高不純物濃度のｐ+ 型領域２が形成され、ｐ+ 型領域２周囲にｐ+ 型領域２より浅く不純物濃度が低い構造のｐ- 型領域５が形成されている。さらに、ｐ- 型領域５の周囲にｐ- 型領域５と同じ深さの、又は浅いｐ- 型領域６が形成されている。ｐ- 型領域６の不純物濃度はｐ+ 型領域２よりも低い。ｐ+ 型領域２にはＡｌなどの導電材料の主電極３がオーミック接触している。またｎ型ＳｉＣ基板１０にはＡｌ主電極４がオーミック接触している。
【０００９】
高不純物濃度のｐ+ 型領域２に近いｐ- 型領域５にはＡｌを注入し、ｐ- 型領域５の周囲に形成するｐ- 型領域６にはＢ等のｐ- 型領域５に注入したＡｌより不純物準位が深く、活性化率が低い不純物を注入する。
【００１０】
室温においては所定の耐圧印加時にｐ- 型領域５及びｐ- 型領域６が空乏化する。高温でｐ- 型領域５は活性化率が上昇し、キャリア濃度が増加するので空乏領域が狭くなるが、ｐ- 型領域６はｐ- 型領域５より活性化率が低くキャリア濃度が低いため空乏化する。したがって、ｐ- 型領域が単一のもののような耐圧の温度による耐圧の変動を防止することができる。
【００１１】
図４にＳｉＣに不純物としてＡｌを用いたときの温度に対するキャリア濃度の変化を示す。ｐ- 型領域５の濃度を斜線領域の範囲に入れる必要がある場合、 Ａｌを１０17cm-3添加すると室温から３８０Ｋまでその濃度範囲に含まれていても、３８０Ｋを超える高温になるとキャリア濃度が増加してこの範囲を逸脱してしまう。
【００１２】
図５はＳｉＣに不純物としてＢを用いたときの温度に対するキャリア濃度の変化を示す。Ｂの不純物準位は３００ｍｅＶでＡｌの２００ｍｅＶより深いので、同量添加した場合でもキャリア濃度はＡｌより低くなる。Ａｌと同様に活性化率の温度依存性のため、高温になるとキャリア濃度は増加する。
【００１３】
したがって、広い温度域にわたって安定した耐圧を得るためには、ｐ- 型領域５にはＡｌが不純物濃度５×１０16cm-3となるように注入し、ｐ- 型領域６にはＢが不純物濃度５×１０16cm-3となるように注入する。室温から４５０Ｋまでは所定の耐圧印加時にｐ-型領域５，ｐ-型領域６ともに空乏化しているが、４５０Ｋを超えるとｐ- 型領域５は十分空乏化しなくなる。４５０Ｋを超える温度範囲ではｐ- 型領域６が最適な濃度範囲となるため、ｐ- 型領域６が空乏化して所定の耐圧を得ることができる。
【００１４】
また、高不純物濃度のｐ+ 型領域２に近いｐ- 型領域５にＡｌ又はＢを注入し、ｐ- 型領域５の周囲に形成するｐ- 型領域６にはｐ- 型領域５に注入した不純物と同じ不純物をｐ- 型領域５より低濃度に注入してもよい。Ｂを例にとると、ｐ- 型領域５にはＢを不純物濃度１×１０18cm-3となるように注入し、ｐ- 型領域６にはＢが不純物濃度１×１０17cm-3となるように注入する。室温から３８０Ｋまでは所定の耐圧印加時にｐ- 型領域５，ｐ- 型領域６ともに空乏化しているが、３８０Ｋを超えるとｐ- 型領域５は十分空乏化しなくなる。しかし、３８０Ｋを超える温度範囲ではｐ- 型領域６が最適な濃度範囲となるため、ｐ- 型領域６が空乏化して所定の耐圧を得ることができる。
【００１５】
図３は高温での電界緩和の効果をさらに高めた他の実施例を示す。本図は、図１と同様に半導体装置のターミネーション部を示す。ｎ型ＳｉＣ基板１０上にエピタキシャル成長させたｎ型ＳｉＣ膜１を形成し、ｎ型ＳｉＣ膜１表面に高不純物濃度のｐ+ 型領域２及びｎ型チャネルストッパー領域８が形成され、ｐ+ 型領域２周囲にｐ- 型領域５が形成されている。さらに、ｐ- 型領域５の周囲にｐ- 型領域６が形成されている。ｐ+ 型領域２とｎ型チャネルストッパー領域８の間のｎ型ＳｉＣ基板１の表面上にはＳｉＯ2 ，Ａｌ2Ｏ3等の絶縁膜７が覆っている。ｐ+ 型領域２およびｎ型チャネルストッパー領域８にはＡｌ電極１１が接触し、ｐ+ 型領域２から絶縁膜７の上を覆ってｎ型基板表面の電荷を緩和するためのＳｉＣ，ＫＡｓ，Ｓｉ，Ｇｅまたはアモルファスまたは多結晶のアンチモン硫化物等の半絶縁膜９がチップ外周に向かって伸び、ｎ型チャネルストッパー領域８にＡｌ電極１１を介して接触している。
【００１６】
従来、高耐圧半導体装置のパッケージ内に充填されるゲル等の表面保護材や、外部からの影響により、ターミネーション部の絶縁膜上に電荷が誘起され、ｐｎ接合に逆電圧を印加し続けると、空乏領域によって生じる高電界によって酸化膜内の電荷特にプラスイオンが動かされ、一部分に集中する。この集められた電荷が作る電界によって表面付近の空乏領域内の電界が増大し、耐圧が劣化してしまう。この問題を解決するために、電界シールド領域として半絶縁膜が用いられている。このような高耐圧半導体装置の一例として、特開昭50−115479号公報に従来の装置が記載されている。ｐ- 型領域６は室温においては最適なキャリア濃度以下に設定されているため室温で使用する限りにおいては、酸化膜内の蓄積した電荷の影響を強く受けると言う欠点がある。上記のような半絶縁膜を設けることにより室温でも電荷の蓄積を防ぎ耐圧の低下を回避することができる。
【００１７】
図６は、本発明の実施例（図１）によるＳｉＣ ｐｎ接合ダイオードの温度と耐圧の関係を、従来例（図２）と比較して示したものである。従来例（図２）のｐ- 型領域５にはＡｌが不純物濃度５×１０16cm-3となるように注入する。また実施例（図１）では、ｐ- 型領域５にはＡｌが不純物濃度５×１０16cm-3となるように注入し、ｐ- 型領域６にはＢが不純物濃度５×１０16cm-3となるように注入する。従来例では４００Ｋを超えると耐圧が急激に低下するが、本発明の実施例では広い温度範囲にわたって耐圧が維持されている。
【００１８】
以上の実施例においては、ＳｉＣ基体を有する半導体装置について説明したが、本発明はＳｉＣに限らずＳｉ等の他の半導体材料の場合でも適用できる。なお、ＳｉＣのようなバンドギャップの広い半導体材料の場合はキャリア濃度の温度変化が大きく、本発明の効果が顕著に現われる。
【００１９】
【発明の効果】
本発明によれば、広い温度範囲において所定の耐圧を安定して得られる。
【図面の簡単な説明】
【図１】本発明の一実施例を示す図である。
【図２】従来例を示す図である。
【図３】本発明の他の実施例を示す図である。
【図４】Ａｌのキャリア濃度の温度依存性を示す図である。
【図５】Ｂのキャリア濃度の温度依存性を示す図である。
【図６】ＳｉＣ ｐｎ接合ダイオードの温度と耐圧の関係。
【符号の説明】
１…ｎ型ＳｉＣ膜、２…ｐ+ 型領域、３，４…Ａｌ主電極、５…第一のｐ- 型領域、６…第二のｐ- 型領域、７…絶縁膜、８…ｎ型チャネルストッパー領域、９…半絶縁膜、１０…ｎ型ＳｉＣ基板、１１…Ａｌ電極。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a planar semiconductor device.
[0002]
[Prior art]
A conventional high voltage planar type pn junction diode is shown in FIG. In FIG. 2, an n-type Si film 1 epitaxially grown on an n-type Si substrate 10 is formed, and a p + -type region 2 is formed on the surface of the n-type Si film 1 by diffusion or ion implantation. A p − type region 5 having a shallower structure than that of 2 is formed. By making the p − type region 5 into a shallow structure, the effect of electric field relaxation can be further enhanced. An electrode 3 made of a conductive material such as Al is in contact with the p + type region 2. An example of such a high breakdown voltage semiconductor device is disclosed in Japanese Patent Laid-Open No. 5-63213.
[0003]
[Problems to be solved by the invention]
In the conventional technique, when the temperature varies, the impurity activation rate changes and the carrier concentration in the p − -type region 5 changes. For this reason, even if the impurity concentration of the p − type region 5 is set so that a desired breakdown voltage can be obtained at room temperature, the carrier concentration increases at a high temperature, so that the depletion layer in the p − type region 5 is expanded. There is a problem that the withstand voltage decreases due to the change.
[0004]
The present invention has been made in consideration of such problems, and provides a planar semiconductor device that can stably obtain a high breakdown voltage in a wide temperature range.
[0005]
[Means for Solving the Problems]
In order to achieve the above object, the present invention comprises a first conductivity type first region, a second conductivity type second region adjacent to the first region, and a pair of main electrodes, In a planar semiconductor device in which a main electrode is in contact with a second region, a second conductivity type second region having a high impurity concentration is formed on the surface of the first conductivity type first region, and the second region A third region of the second conductivity type having a shallower and lower impurity concentration than the second region is formed around the second region, and the third region has the same depth or a shallower impurity concentration as the third region around the third region. A fourth region of the second conductivity type having a low structure is formed, and an impurity having an impurity level deeper than that of the impurity implanted into the third region and having a low activation rate is implanted into the fourth region. It is characterized by this.
[0006]
Since the impurity levels of the impurities contained in the plurality of regions are different, the activation rate of the impurities is different for each region. Therefore, it is possible to make a certain region of a plurality of regions have a preferable carrier concentration value in order to obtain a desired breakdown voltage in a certain temperature range, and to make the other region have a preferable carrier concentration value in another temperature range. become. That is, the carrier concentration of the second conductivity type semiconductor layer in the termination portion of the pn junction can be set to a value that allows a desired breakdown voltage to be obtained over a wide temperature range.
[0007]
The first conductivity type and the second conductivity type are p-type or n-type, respectively, and are opposite to each other.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows an embodiment of the present invention. This figure shows the termination of the planar semiconductor device. There are various types of semiconductor devices such as transistors and diodes. N-type SiC film 1 epitaxially grown on n-type SiC substrate 10 is formed. A p + type region 2 having a high impurity concentration is formed on the surface of the n type SiC film 1, and a p − type region 5 having a shallower and lower impurity concentration than the p + type region 2 is formed around the p + type region 2. Yes. Furthermore, a p − type region 6 having the same depth as that of the p − type region 5 or a shallow p − type region 6 is formed around the p − type region 5. The impurity concentration of the p − type region 6 is lower than that of the p + type region 2. A main electrode 3 made of a conductive material such as Al is in ohmic contact with the p + type region 2. The Al main electrode 4 is in ohmic contact with the n-type SiC substrate 10.
[0009]
P close to p + -type region 2 of high impurity concentration - the type region 5 by injecting Al, p - the type region 6 p such B - - p formed around the mold region 5 poured into a mold region 5 Impurities having a deeper impurity level and lower activation rate than implanted Al are implanted.
[0010]
At room temperature, p − type region 5 and p − type region 6 are depleted when a predetermined breakdown voltage is applied. P at a high temperature - -type region 5 is the activation rate is increased, although the depletion region becomes narrow since the carrier concentration increases, p - -type region 6 p - -type region 5 has a low carrier concentration lower activation rate than Depleted. Therefore, it is possible to prevent fluctuations in the breakdown voltage due to the breakdown voltage temperature, such as a single p − -type region.
[0011]
FIG. 4 shows changes in carrier concentration with respect to temperature when Al is used as an impurity in SiC. When it is necessary to put the concentration of the p - type region 5 in the range of the hatched region, when Al is added at 10 17 cm −3 , the carrier concentration becomes higher than 380 K even if it is included in the concentration range from room temperature to 380 K. Will deviate from this range.
[0012]
FIG. 5 shows the change in carrier concentration with respect to temperature when B is used as an impurity in SiC. Since the impurity level of B is 300 meV and deeper than 200 meV of Al, even when the same amount is added, the carrier concentration is lower than that of Al. As with Al, the carrier concentration increases at higher temperatures because of the temperature dependence of the activation rate.
[0013]
Therefore, in order to obtain a stable breakdown voltage over a wide temperature range, Al is implanted in the p − type region 5 so that the impurity concentration is 5 × 10 16 cm −3, and B is doped in the p − type region 6. Inject to a concentration of 5 × 10 16 cm −3 . From room temperature to 450K, the p − type region 5 and the p − type region 6 are both depleted when a predetermined breakdown voltage is applied, but when the temperature exceeds 450K, the p − type region 5 is not fully depleted. Since the p − type region 6 has an optimum concentration range in the temperature range exceeding 450 K, the p − type region 6 can be depleted and a predetermined breakdown voltage can be obtained.
[0014]
Further, p close to p + -type region 2 of high impurity concentration - -type region 5 by implanting Al or B, p - the type region 6 p - - p formed around the mold region 5 poured into a mold region 5 The same impurity as the doped impurity may be implanted at a lower concentration than the p − type region 5. Taking B as an example, B is implanted into the p − -type region 5 so as to have an impurity concentration of 1 × 10 18 cm −3, and B is implanted into the p − -type region 6 with an impurity concentration of 1 × 10 17 cm −3. Inject so that it becomes. From room temperature to 380K, the p − -type region 5 and the p − -type region 6 are both depleted when a predetermined breakdown voltage is applied. However, when the temperature exceeds 380K, the p − -type region 5 is not fully depleted. However, in a temperature range exceeding 380 K p - for type region 6 is the optimum concentration range, p - -type region 6 can be obtained a predetermined breakdown voltage and depletion.
[0015]
FIG. 3 shows another embodiment in which the effect of electric field relaxation at high temperature is further enhanced. This figure shows the termination part of the semiconductor device as in FIG. An n-type SiC film 1 epitaxially grown on an n-type SiC substrate 10 is formed, and a p + -type region 2 and an n-type channel stopper region 8 having a high impurity concentration are formed on the surface of the n-type SiC film 1. A p − -type region 5 is formed around 2. Further, p - p around the mold region 5 - -type region 6 is formed. An insulating film 7 such as SiO 2 or Al 2 O 3 covers the surface of the n-type SiC substrate 1 between the p + -type region 2 and the n-type channel stopper region 8. An Al electrode 11 is in contact with the p + type region 2 and the n type channel stopper region 8, and covers the insulating film 7 from the p + type region 2 to relieve charges on the surface of the n type substrate. A semi-insulating film 9 such as Si, Ge, amorphous or polycrystalline antimony sulfide extends toward the outer periphery of the chip, and is in contact with the n-type channel stopper region 8 through an Al electrode 11.
[0016]
Conventionally, when a surface protective material such as a gel filled in a package of a high breakdown voltage semiconductor device or an external influence causes a charge to be induced on the insulating film of the termination portion, and a reverse voltage is continuously applied to the pn junction, Due to the high electric field generated by the depletion region, charges in the oxide film, particularly positive ions, are moved and concentrated in a part. The electric field generated by the collected electric charges increases the electric field in the depletion region near the surface and degrades the breakdown voltage. In order to solve this problem, a semi-insulating film is used as an electric field shield region. As an example of such a high voltage semiconductor device, a conventional device is described in Japanese Patent Laid-Open No. 50-115479. Since the p − -type region 6 is set to an optimum carrier concentration or less at room temperature, there is a drawback that it is strongly affected by the charge accumulated in the oxide film as long as it is used at room temperature. By providing the semi-insulating film as described above, charge accumulation can be prevented even at room temperature and a decrease in breakdown voltage can be avoided.
[0017]
FIG. 6 shows the relationship between the temperature and the breakdown voltage of the SiC pn junction diode according to the embodiment of the present invention (FIG. 1) in comparison with the conventional example (FIG. 2). Al is implanted into the p − type region 5 of the conventional example (FIG. 2) so that the impurity concentration is 5 × 10 16 cm −3 . In the embodiment (FIG. 1), Al is implanted into the p − -type region 5 so as to have an impurity concentration of 5 × 10 16 cm −3, and B is implanted into the p − -type region 6 with an impurity concentration of 5 × 10 16 cm 3. Inject to -3 . In the conventional example, when the pressure exceeds 400K, the breakdown voltage sharply decreases, but in the embodiment of the present invention, the breakdown voltage is maintained over a wide temperature range.
[0018]
In the above embodiments, a semiconductor device having a SiC substrate has been described. However, the present invention is not limited to SiC but can be applied to other semiconductor materials such as Si. In the case of a semiconductor material having a wide band gap such as SiC, the temperature change of the carrier concentration is large, and the effect of the present invention is remarkably exhibited.
[0019]
【The invention's effect】
According to the present invention, a predetermined breakdown voltage can be stably obtained over a wide temperature range.
[Brief description of the drawings]
FIG. 1 is a diagram showing an embodiment of the present invention.
FIG. 2 is a diagram showing a conventional example.
FIG. 3 is a diagram showing another embodiment of the present invention.
FIG. 4 is a graph showing the temperature dependence of the carrier concentration of Al.
FIG. 5 is a diagram showing the temperature dependence of the carrier concentration of B.
FIG. 6 shows the relationship between the temperature and breakdown voltage of a SiC pn junction diode.
[Explanation of symbols]
1 ... n-type SiC film, 2 ... p + -type region, 3, 4 ... Al main electrode, 5 ... first p - type region, 6 ... second p - type region, 7: insulating film, 8 ... n Type channel stopper region, 9... Semi-insulating film, 10... N-type SiC substrate, 11.

Claims (3)

第１導電型の第１の領域と、
第１の領域に隣接する第２導電型の第２の領域と、
一対の主電極とを備え、一方の主電極が第２の領域と接触するプレーナ型半導体装置において、
第１導電型の第１の領域の表面に高不純物濃度の第２導電型の第２の領域が形成され、該第２の領域の周囲に第２の領域より浅く不純物濃度が低い構造の第２導電型の第３の領域が形成され、第３の領域の周囲に第３の領域と同じ深さの、又は浅く不純物濃度が低い構造の第２導電型の第４の領域が形成されていて、かつ、第４の領域には第３の領域に注入した不純物より不純物準位が深く、活性化率が低い不純物を注入したことを特徴とする
プレーナ型半導体装置。A first region of a first conductivity type;
A second region of the second conductivity type adjacent to the first region;
In a planar type semiconductor device comprising a pair of main electrodes and one main electrode being in contact with the second region,
A second region of the second conductivity type having a high impurity concentration is formed on the surface of the first region of the first conductivity type, and the second region has a structure in which the impurity concentration is shallower and lower than the second region around the second region. A second conductivity type third region is formed, and a second conductivity type fourth region having the same depth as that of the third region or a shallow structure with a low impurity concentration is formed around the third region. In addition, a planar type semiconductor device is characterized in that an impurity having a deeper impurity level and a lower activation rate is implanted into the fourth region than the impurity implanted into the third region. 請求項１に記載のプレーナ型半導体装置において、
前記第２導電型の第２の領域として高不純物濃度のｐ+ 型領域を形成し、前記第３の領域としてｐ- 型領域を形成し、該第３の領域にはＡｌを注入し、前記第４の領域としてｐ- 型領域を形成し、該第４の領域にはＢ等の第３の領域に注入したＡｌより不純物準位が深く、活性化率が低い不純物を注入したことを特徴とするプレーナ型半導体装置。The planar semiconductor device according to claim 1,
A p + type region having a high impurity concentration is formed as the second region of the second conductivity type, a p − type region is formed as the third region, Al is implanted into the third region, and A p − -type region is formed as a fourth region, and an impurity having an impurity level deeper than that of Al implanted into the third region such as B and having a low activation rate is implanted into the fourth region. A planar semiconductor device. 請求項１に記載のプレーナ型半導体装置において、
ＳｉＣ基板上に前記第１の領域を形成したことを特徴とするプレーナ型半導体装置。The planar semiconductor device according to claim 1,
A planar semiconductor device, wherein the first region is formed on a SiC substrate.
JP31995095A 1995-12-08 1995-12-08 Planar type semiconductor device Expired - Lifetime JP3997551B2 (en)

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