JP3452054B2 - MOSFET - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION 1. Field of the Invention
Edge gate type field effect transistor), IGBT (conductivity)
Modulation transistor), bipolar transistor, die
High withstand voltage and large current capacity semiconductor device applicable to diodes
About the installation. [0002] 2. Description of the Related Art Generally, a semiconductor device has an electrode portion on one side.
It can be broadly divided into a horizontal structure and a vertical structure having electrodes on both sides.
For example, FIG. 10 shows an SOI (silicon) having a horizontal structure.
on-insulator-MOSFET. this
SOI-MOSFET structure is n-channel MOSFET
Offset gate structure.
A p-type channel diffusion layer 7 formed on the edge film 6;
Formed on the channel diffusion layer 7 with the gate insulating film 10 interposed therebetween.
Gate electrode 11 with a field plate
Formed on one end side of the gate electrode 11 in the gate diffusion layer 7.
n⁺Source region 8 and the other end of gate electrode 11
N formed at a spaced position⁺Drain region 9
And an n-type low-concentration drain extending between the drain and the gate
Region (drain drift region) 90 and this low-concentration
And a thick insulating film 12 formed on the rain region 90.
You. The low-concentration drain region 90 is formed by a MOS
Carrier flows by electric field when FET is on
Acts as a drift region and depletes when off
Relax electric field strength and increase withstand voltage. Low concentration drain region 9
0 and the current in the region 90 is increased.
Shortening the path length reduces the drift resistance,
The substantial on-resistance of the MOSFET (drain-source resistance
Anti-) lowering effect, but on the contrary, p-type channel
Junction between the diffusion layer 7 and the n-type low concentration drain region 90
The depletion layer between the drain and the channel that progresses from Ja expands
Difficult to reach the maximum (critical) electric field strength of silicon quickly
As a result, the breakdown voltage (drain-source voltage) decreases.
That is, there is a trade-off between the ON resistance (current capacity) and the breakdown voltage.
Have a relationship. This trade-off relationship is IGBT, bipo
For semiconductor devices such as transistors, diodes, etc.
Is also known to hold in a similar manner. FIG. 11 shows another structure of a lateral type MOSFET.
Show the structure. FIG. 11A shows a p-channel MOSFET.
, P⁻Channel formed on the semiconductor layer 4
A gate insulating film on the diffusion layer and the channel diffusion layer;
Gate electrode 1 with field plate formed via
1 and one end side of the gate electrode 11 in the channel diffusion layer 3
Formed in⁺Source region 18 and gate electrode
11 is a p-type low-concentration drain whose well end is located directly below the other end.
In region (drain drift region) 14 and gate electrode
P formed at a position separated from the other end of the pole 11⁺Type
The drain region 19 and p⁺Adjacent to the source region 18 of the mold
Do n⁺Contact region 71 and p-type low concentration drain
And a thick insulating film 12 formed on the in 14. This
Well-type p-type low-concentration drain
The on-resistance depends on the current path length of the region 14 and the impurity concentration.
And the breakdown voltage are determined in a trade-off relationship. FIG. 11B shows a double diffusion type n-channel MO.
SFET, p⁻Formed on the type semiconductor layer 4
Type low concentration drain layer (drain / drift layer) 22;
On the low concentration drain layer 22 via the gate insulating film 10
A gate electrode 11 with a formed field plate;
One end of the gate electrode 11 in the low concentration drain layer 22
The well-shaped p-type channel diffusion region 17 formed is
Formed in a well shape in the channel diffusion region 17
⁺Type source region 8, gate electrode 11 and spaced apart therefrom
N⁺Formed in the surface layer between the drain region 9
Well-shaped p-type top layer 24 and n⁺Source of type
P adjacent to region 8⁺Contact region 72 and p-type
A thick insulating film 12 formed on the top layer 24
You. Even in such a structure, the n-type low concentration drain layer region
The on-resistance and the resistance to the
The pressure is determined in a trade-off relationship. However, in the structure of FIG.
The concentration drain layer 22 is⁻Type semiconductor layer 4 and the upper
Since it is sandwiched between the p-type top layer 24 and the
Is in the off state, p-type channel diffusion region 17 and p
Not only from the n-junction Ja, but also the n-type low concentration drain layer 2
The depletion layer also extends from the upper and lower pn junctions Jb, Jb.
Therefore, the low-concentration drain layer 22 is depleted quickly.
Thus, a high breakdown voltage structure is provided. The low concentration drain
The impurity concentration of the layer 22 can be increased, and the on-resistance can be reduced.
It is possible to increase the current capacity. On the other hand, as a semiconductor device having a vertical structure,
For example, a trench gate type n-channel MOS shown in FIG.
FETs are known. This structure has a back electrode (not shown).
N) is in conductive contact⁺Formed on the drain layer 29
N-type low concentration drain layer 39 and low concentration drain layer
Gate insulation in trench trench dug on the surface side of 39
Trench gate electrode 21 buried through film 10
And a trench gate electrode on the surface of the lightly doped drain layer 39.
P type channel diffusion layer 2 formed shallow to a depth of about 21
7 and are formed along the upper edge of the trench gate electrode 21.
N⁺Thickness covering the source region 18 and the gate electrode 21
Insulating film 12. Note that a single layer n ⁺Type dray
N layer instead of⁺Mold upper layer and p⁺Mold
With a two-layer structure, an n-type IGBT structure can be obtained.
it can. Even in such a vertical structure, the low concentration drain
When the MOSFET is on, the portion of the
Acts as a drift region that generates a drift current in the
When in the off state, it is depleted to increase the breakdown voltage.
Resistance and breakdown voltage are the thickness of the low concentration drain layer 39 and impurities
Controlled by the concentration, there is a trade-off between the two
It is in. [0008] FIG. 13 shows n of silicon.
The relationship between the ideal withstand voltage and the ideal on-resistance of the channel MOSFET
It is a graph which shows a relationship. Ideal breakdown voltage is pn due to shape effect
It was assumed that there was no reduction in junction breakdown voltage. Ideal ON resistance is low
The resistance of the part other than the drain region is so small that it can be ignored.
I assumed. FIG. 13 shows the vertical n-channel shown in FIG.
The relationship between the ideal withstand voltage and the ideal on-resistance of
Show. The vertical element has a drift current
The direction in which the depletion layer extends and spreads due to the reverse bias when off
Are the same. Only on the low concentration drain layer 39 of FIG.
The ideal breakdown voltage BV in the off state can be approximately calculated by the following equation.
I get it. BV = E_c ²ε₀ε_Siα (2-α) / 2qN_D          (1) E_c: E_c(N_D), Impurity concentration N_DSiri in
Maximum electric field strength of the capacitor ε₀: Dielectric constant of vacuum ε_Si: Dielectric constant of silicon q: unit charge N_D: Impurity concentration of low concentration drain region α: coefficient (0 <α <1) The ideal on-resistance per unit area at the time of on is given by
It can be more approximated. R = αW / μqN_D μ: μ (N_D), Impurity concentration N_DMobility of electrons in Where W = E_cε₀ε_Si/ QN_DIs
And R is R = E_cε₀ε_Siα / μq²N_D ²                    (2) Becomes From equations (1) and (2), qN_DAnd remove α
If, for example, 2/3 is used as the optimum value, R = BV²(27 / 8E_c ³ε₀ε_Siμ) (3) Is obtained. Here, the on-resistance R is equal to the square of the breakdown voltage BV.
Seems like an example, but E_cAnd μ is N_DDepends on
FIG. 13 actually shows BV values of 2.4 to 2.6.
It is proportional to the power. FIG. 13 shows a horizontal type M shown in FIG.
MOSF with OSFET structure replaced with n-channel type
The relationship between the ideal withstand voltage of ET and the ideal on-resistance is shown. This n
Drift when on in channel type MOSFET
The current flows in the horizontal direction, while the
The direction in which the depleted layer extends is not lateral but substantially from the edge of the well
In the vertical direction (upward) from the bottom of the well is faster. Vertically
To obtain a high breakdown voltage with the extended depletion layer, use a low-concentration drain region.
Pn junction surface (well bottom) between channel 14 and channel diffusion layer 3
Depletion to the surface of the low concentration drain layer 14 (well surface)
Must be transformed. Therefore, the low concentration drain region
The maximum value of the doping amount of the 14 nets is S_D= E_cε₀ε_Si/ Q (4) Is limited to Lateral length of low concentration drain region 14
Is L, the ideal breakdown voltage BV is BV = E_cLβ (5) Becomes Where β is an unknown coefficient (0 <β <1)
You. Also, the ideal on-resistance R per unit area is R = L²/ ΜqS_D                                  (6) Approximately. Therefore, L is calculated from the equations (5) and (6).
After erasure and substituting equation (4), R = BV²/ Β²E_c ³ε₀ε_Siμ (7) FIG. 13 shows a horizontal type 2 shown in FIG.
The ideal breakdown voltage of the structure of the heavy diffusion type n-channel MOSFET and
This shows the relationship with the ideal on-resistance. In the structure of FIG.
11A, a p-type top layer 24 is provided in the structure of FIG.
And a depletion layer extending from both the upper and lower sides
The rain layer 22 is depleted early in a pinch. Low concentration drain
Net doping amount S of in region 22_DFigure 11
It can be increased to about twice that of (a).
is there. S_D= 2E_cε₀ε_Si/ Q (8) In such a case, the relationship between the ideal on-resistance R and the ideal withstand voltage BV is as follows. R = BV²/ 2β²E_c ³ε₀ε_Siμ (9) Becomes FIG. 13 shows the relationship between the ON resistance and the breakdown voltage.
Lade-off relationship is slightly improved, but at most twice
Can be set only up to the concentration of
Design flexibility of current capacity and withstand voltage is still low
Has become. In view of the above problems, an object of the present invention is to provide
Improves on-resistance by improving the structure of the drift region.
By greatly relaxing the trade-off between
Despite the withstand voltage, the reduction of the on-resistance
An object is to provide a semiconductor device which can be increased. [0013] Means for Solving the Problems To solve the above problems,
Therefore, the measures taken by the present invention are, for example, the low concentration of the MOSFET.
Drift current flows in the ON state like the drain region
With drift region depleted in off-state together with
FIG. 1 schematically shows the drift region of the body device.
Such as layered structure, fibrous structure or honeycomb structure
A row division structure and a first conductivity type divided drift path
Pn junction interposed between adjacent side surfaces (boundary) in region 1
This is where a second conductivity type partition region 2 to be separated is provided. That is, as shown in FIG.
At least two areas connected in parallel at least at the ends
The above-mentioned plate-shaped first conductivity type (for example, n-type) divided drills
Parallel drift paths having a layered structure with
Split drift path aggregate) 100 and split drift path area
A plate-shaped second intervening between 1, 1 for separating a pn junction
And a conductive type (for example, p-type) partition region 2. Multiple
The second conductive-type partition regions 2 are at least edge-to-edge.
Connected in parallel. The structure of the drift region shown in FIG.
The structure is a fibrous structure, and the first conductive type (n-type) split in a streak shape
Drift path region 1 and stripe-shaped second conductivity type (p-type) partition
The area 2 is arranged in a checkered pattern in the cross section of the aggregate. Further, the first conductivity type (n) shown in FIG.
(Type) Divided drift path region 1 has connecting portions 1a at four corners
ing. As can be clearly seen from FIG.
1st guide of the outermost end (uppermost end or lowermost end) of the
Pn junction separation along the outside of the electric split drift path region 1
A second conductivity type side end region 2a may be provided. When the semiconductor device is on, a plurality of parallel
Drift via column-connected split drift paths 1,1
A current flows, but on the other hand, when in the off state, the first conductivity type
Pn contact between split drift path region 1 and second conductivity type partition region 2
The depletion layer is formed from the first conductivity type divided drift path 1
It spreads inside and is depleted. One second conductive type finish
The depletion edge spreads laterally from both sides of the cutting region 2 so that it is depleted
Very quickly. The second conductivity type partition region 2 is also emptied at the same time.
Depleted. Therefore, the semiconductor device has a high withstand voltage, and n
It is possible to increase the impurity concentration of the mold split drift path region 1.
Therefore, a reduction in on-resistance can be realized. In particular, the book
In the present invention, the second conductive type partition region 2 is adjacent to the side surface from both side surfaces.
Empty to both the first conductivity type divided drift path areas 1 and 1
The depletion end is entering, and the depletion end spreads to both sides
Is effectively acting on the split drift path areas 1, 1
To occupy the second conductivity type partition region 2 for forming a depletion layer.
The width can be halved and the first conductivity type divided drift path region
1 can increase the cross-sectional area, and
The resistance is greatly reduced. The occupied width of the second conductivity type partition region 2 is
Preferably, it is slight. Also, the second conductivity type partition region
It is desirable that the impurity concentration of No. 2 is low. 1st conductivity type split
Increase the number of lift route area 1 per unit area (number of divisions)
The trade-off between on-resistance and breakdown voltage is
Can be reduced to width. In the present invention, a single first conductivity type split drill is provided.
The ideal on-resistance r and the ideal withstand voltage BV for the shift path region 1
Is a trade-off relation of the following formula.
Assuming that it is infinitesimal, the ideal on-resistance r is given by equation (9)
N times the ideal on-resistance R of r = NR = BV²/ 2β²E_c ³ε₀ε_Siμ (10) And the relationship between the ideal on-resistance R and the ideal withstand voltage BV of the entire parallel drift path group is: R = BV²/ 2Nβ²E_c ³ε₀ε_Siμ (11) Becomes Therefore, the larger the number N of divisions of the drift region,
A semiconductor device with extremely low on-resistance can be realized.
You can see that. That is, the present invention provides a second conductivity type channel region.
First conductivity type source region and second conductivity type channel formed in
Gate formed on the side wall of the
A second conductivity type channel region and a first conductivity type.
It extends between the drain region and the
Drain and depletion in the off state
In a MOSFET having a drift region,
The lift area is connected in parallel and stacked in the thickness direction of the substrate.
Parallel drift having a plurality of first conductivity type split drift path regions
Drift path group and adjacent to the first conductivity type divided drift path area
A second conductivity type partition region interposed between them,
Uppermost and lowermost first conductivity type components of the parallel drift path group
A second conductivity type side end region is provided outside the split drift path region.
And the net dope in the second conductive type side end region.
2 × 10¹²cm²And the first conductive
Mold split drift path region, second conductivity type partition region, and second conductivity
It is characterized in that the length with the mold side end region is substantially equal. Such
The first conductivity type split drift path region
Depletion can be accelerated even if the concentration is increased.
Providing MOSFETs that realize high withstand voltage while reducing resistance
Can be provided. [0021] [0022] BRIEF DESCRIPTION OF THE DRAWINGS FIG.
Explanation will be given based on the plane. [Embodiment 1] FIG. 2A shows an embodiment of the present invention.
FIG. 9 shows a horizontal type SOI-MOSFET according to the first embodiment.
2 (b) is cut along the line AA 'in FIG. 2 (a).
FIG. 2 (c) is a cutaway view showing the folded state, and FIG.
It is a sectional view showing the state where it was cut by the B 'line. The structure of the SOI-MOSFET of this embodiment is shown in FIG.
As in the structure shown in FIG.
An insulating film on a semiconductor substrate 5 having a fset gate structure
6, a p-type channel diffusion region 7 formed on
Formed on the tunnel diffusion region 7 with the gate insulating film 10 interposed therebetween.
Gate electrode 11 with a field plate
Formed on one end side of the gate electrode 11 in the gate diffusion region 7.
N⁺Source region 8 and the other end of gate electrode 11
N formed at a position apart from⁺Drain region 9
And drain drift extending between drain and gate
Region 190 and on the drain drift region 190
And a thick insulating film 12 formed. The drain drift region 19 in this embodiment
0 indicates a strip-shaped n-type divided drift path region 1 and a strip-shaped p
A pattern in which the mold partition areas 2 are alternately and repeatedly arranged on a plane.
It has a tripe parallel structure. Multiple n-type split drills
One end of the shift path region 1 is connected to the p-type channel diffusion region 7 by p.
n junctions and their other ends are n⁺Type drain region 9
Connected, n⁺Branch from the side of the drain region 9 of the mold
Thus, a drift path group 100 connected in parallel is formed. common
Split drift path area at the outermost end of row drift path group 100
1, a striped p-type side end region 2a is provided.
All split drift path areas 1
Between the p-type semiconductor regions 2 (2a). Also,
One end of each of the p-type partition regions 2 is a p-type channel diffusion region.
7 and their other ends are n⁺Drain region 9
From the p-type channel diffusion region 7 side.
It branches and is connected in parallel. When the MOSFET is on, the gate
N via the channel inversion layer 13 immediately below the insulating film 10⁺Type
From the source region 8 to the plurality of n-type divided drift path regions 1
Carriers (electrons) flow in, drain-source voltage
Drift current flows in the electric field due to On the other hand,
At this time, the channel inversion layer 13 immediately below the gate insulating film 10 is turned off.
And the drain-source voltage causes the n-type split drift
Junction J between the channel region 1 and the p-type channel diffusion region 7
a, n-type drift path region 1 and p-type partition region 2
The depletion layer is an n-type split drift path from the n-junction Jb
This spreads into zone 1 and is depleted. pn junction Ja
These depletion ends are determined by the path length in the n-type split drift path region 1.
The depletion end e from the pn junction Jb is divided into n-type
Spreads in the width direction of the drift within the drift path area 1, and on both sides
Since the depletion edge extends from the surface, depletion is greatly accelerated. Also
The p-type partition region 2 is also depleted at the same time. Therefore, the electric field
The strength is reduced and the breakdown voltage is increased, and the n-type split
It is possible to increase the impurity concentration in the
Thus, the on-resistance is reduced. In particular, in this example, the p-type partition
N-type split drift path areas 1 and 2 adjoining from both sides of area 2
Since the depletion end e enters both sides of 1
The total occupation width of the p-type partition region 2 for forming the depletion layer can be reduced by half.
The sectional area of the n-type split drift path region 1 is increased accordingly.
, And the on-resistance is reduced as compared with before.
Number of the n-type divided drift path regions 1 per unit area (min.
Trade-off between on-resistance and breakdown voltage as N increases
Off relationship can be greatly eased. 3 or more than 2
Will be noticeable. The occupied width of the p-type partition region 2 is very small.
Preferably. Here, the ideal withstand voltage BV is, for example, 100V.
Assuming that the impurity concentration N in the n-type split drift path region 1_D
= 3 × 10^Fifteen(Cm^-3) 、 Maximum electric field strength of silicon
E_c = 3 × 10⁵(V / cm), electron mobility μ = 1
000 (cm²/ V · sec), dielectric constant ε in vacuum₀
= 8.8 × 10^-12(C / V · m), ratio of silicon
Dielectric constant ε_Si= 12, unit charge q = 1.6 × 10
^-19(C). Low concentration drain region shown in FIG.
In the region 90, when the length is 6.6 μm and the thickness is 1 μm, the ideal
The on-resistance R is 9.1 (m ohm-cm)²). This
In contrast, in this example, the n-type split drift path region 1 and the p-type
The width of the partition area 2 is, for example, 10 μm, 1 μm, 0.1 μm
When the ideal on-resistance R is calculated as the value of (β = 2/3,
The length of the n-type divided drift path region 1 and the p-type partition region is 5 μm.
m), When the width is 10 μm, 7.9 (m ohm-cm²) 0.8 (m ohm · cm) when the width is 1 μm²) When the width is 0.1 μm, 0.08 (m ohm-c
m²) Dramatically lower on-resistance when width is 1μm or less
Noh. n-type divided drift path
If the width is smaller than the width of region 1, the effect is still remarkable.
You. The width of the n-type divided drift path region 1 and the p-type partition region is
Currently about 0.5μm by photolithography and ion implantation
Temperature is the limit of the mass production level,
Substantial progress will enable further width reductions in the future
Therefore, the on-resistance can be significantly reduced. In particular, the structure of the drift region of this embodiment is
Since it has a repeating structure of the upper stripe-shaped pn, 1
Manufacturing because it can be formed by multiple photolithography
Device simplification can also reduce the cost of the device
it can. [Embodiment 2] FIG. 3A shows an embodiment of the present invention.
14 shows a double diffusion type n-channel MOSFET according to a second embodiment.
FIG. 3B is a plan view, and is cut along the line AA ′ in FIG.
FIG. 3 (c) is a cutaway view showing the state of
It is a sectional view showing the state where it was cut by the -B 'line. The double diffusion type n-channel MOSFET of this embodiment
Is an improvement of the structure shown in FIG.
, P⁻Type or n⁻Formed on the semiconductor layer 4 of the mold
Drain drift region 122 and drain drift
Formed over region 122 with gate insulating film 10 interposed
A gate electrode 11 with a field plate,
Formed on one end side of the gate electrode 11 in the drift region 122
A well-shaped p-type channel diffusion region 17 thus formed;
N formed in a well shape in the channel diffusion region 17⁺
Type source region 8 and n spaced apart from gate electrode 11.⁺
On the drain region 9 and the drain drift region 122
And a thick insulating film 12 formed on the substrate. The drain drift region 12 in this embodiment
2 is a strip-shaped n-type division, similarly to the first embodiment shown in FIG.
Drift path region 1 and strip-shaped p-type partition region 2 are on a plane
And a striped parallel structure alternately and repeatedly arranged with
Has become. And a plurality of n-type split drift path regions 1
Has a pn junction with a p-type channel diffusion region 17,
Their other ends are n⁺Connected to the drain region 9 of the mold.
, N⁺From the drain 9 side of the mold
A row drift path group 100 is formed. Parallel drift
Outside the outermost divided drift path area 1 of the path group 100
Is provided with a p-type side end region 2a for sandwiching the
And all the split drift path regions 1 have p along the sides
It is sandwiched between the mold regions 2 (2a). In addition, a plurality of p-type specifications
One end of the cut region 2 is connected to the p-type channel diffusion region 7
And their other ends are n⁺Pn contact with the drain region 9
And branch off from the p-type channel diffusion region 7 side.
They are connected in parallel. Also in this example, when in the off state, pn
The depletion end from the junction Jb is within the n-type split drift path region 1
Spreads in the width direction of the path, and the depletion ends spread from both sides
So depletion is very fast. At the same time, the p-type partition region 2
Is also depleted. Therefore, similarly to the first embodiment, a high withstand voltage
And the impurity concentration in the n-type split drift path region 1 is increased.
On-resistance can be reduced.
You. Here, the conventional structure shown in FIG.
FIG. 11 (b) shows a comparison at an assumed breakdown voltage of 100V.
With the conventional structure, the on-resistance is about 0.5 (m ohm-c
m²On the other hand, in the structure of the present example,
Similarly, the thicknesses of the divided drift path region 1 and the p-type partition region 2 are
When the width is 1 μm and the width is 0.5 μm, the on-resistance is 0.4
(M ohm-cm²). Split drift path area 1
And by reducing the width of the p-type partition region 2 further
Significant reduction in resistance is possible. Note that the split drift path
By increasing the thickness of the region 1 and the p-type partition region 2,
On-resistance is reduced by increasing the resistance cross section of the lift path 1
Can be achieved. For example, if it is 10 μm, the on-resistance
Is 1/10 or 100 μm, the on-resistance is 1/100
Can be Doping such thick regions
For the same part, multiple (or successively different
Impurity ions may be implanted with energy. [Embodiment 3] FIG. 4A shows an embodiment of the present invention.
FIG. 9 shows a horizontal SOI-MOSFET according to a third embodiment.
4 (b) is cut along the line AA 'in FIG. 4 (a).
FIG. 4 (c) is a cutaway view showing the folded state, and FIG.
It is a sectional view showing the state where it was cut by the B 'line. The structure of the SOI-MOSFET of this example is half
P-type channel formed on insulating film 6 on conductor substrate 5
Diffusion layer 77 and a gate on the side wall of the channel diffusion layer 77.
Trench gate electrode 11 formed via insulating film 10
1 and formed along the upper edge of the trench gate electrode 111.
N⁺Source region 88 and a trench gate electrode
N formed at a position away from 111⁺Mold dray
Region 99 and the drain extending between the drain and the gate
Drift region 290 and this drain drift region
290 formed on the insulating film 12. The drain drift region 29 in this embodiment
0 is different from the case of Embodiment 1 and is a plate-shaped n-type.
Divided drift path region 1 and plate-shaped p-type partition region 2
Are stacked alternately and repeatedly.
Has become. Immediately below the lowest n-type split drift path area 1
Is formed with a p-type side end region 2a.
The p-type side end region 2a is also on the n-type split drift path region 1.
Is formed. Net dope of this p-type side end region 2a
2 × 10¹²/ Cm²The following is assumed. Multiple n
One end of the mold-dividing drift path region 1 has a p-type channel diffusion.
A pn junction to layer 77, the other end of which is n⁺Mold dray
N region 99⁺Mold drain 99 side
To form parallel drift paths 100 connected in parallel.
Has formed. One end of each of the plurality of p-type partition regions 2 is p-type.
Type channel diffusion layer 77, the other end of which is n
⁺Pn junction with the drain region 99 of the p-type,
It is branched from the channel diffusion layer 77 side and connected in parallel.
You. Even in this layered structure, the ideal on-resistance is
N is given by the aforementioned equation (11), and N is an n-type split drift
This is the number of stacked road areas 1. Ideal withstand voltage 100V
At the time, in the conventional structure (N = 1), the ideal on-resistance R = 0.
5 (m ohm-cm²), But in this example, N = 10
In the case of R = 0.05 (m ohm · cm²),
The on-resistance drastically decreases in inverse proportion to the division number N. By the way, in the embodiment shown in FIGS.
Key technologies are photolithography and ion implantation
In contrast, the key technology of this example shown in FIG.
Indicates a plate-shaped n-type split drift path region 1 and a plate
For alternately and repeatedly laminating p-shaped partition regions 2
This is a crystal growth method. The total thickness increases as the number of layers increases
And increase the time required for crystal growth,
Disturbance in impurity distribution due to diffusion of substances cannot be ignored.
Ideally, the n-type split drift path region 1 and the p-type partition region
2 as thin as possible, ignoring disorder in impurity distribution
It is preferable to grow the crystal at a low temperature. That
In order to achieve this, the epitaxial technology often used in silicon technology
Used for compound semiconductor such as gallium-arsenic rather than growth method
MOCVD (metal organic chemical vapor deposition crystal growth method)
BE (molecular beam crystal growth method) is suitable. This
For example, a layered n-type divided drift path region 1 and a layered p-type partition
The thickness of the area 2 can be made finer, and the on-resistance can be greatly reduced.
Becomes In the case of this example, the n-type split drift path
Region 1 and p-type partition region 2 are formed thin to increase impurity concentration
Then, it becomes difficult to form the channel inversion layer 13 and the channel
The resistance is hard to lower, and as a result, the on-resistance is hard to lower. this
In order to improve the n-type split drift path region 1 and the p-type
A portion of the partition region 2 which is in contact with the gate insulating film 10 is locally
It is effective to set the low concentration region in a suitable manner. [Embodiment 4] FIG. 5A shows an embodiment of the present invention.
FIG. 14 is a plan view and a diagram showing a lateral-structure MOSFET according to a fourth embodiment.
5 (b) shows a state cut along the line AA 'in FIG. 5 (a).
FIG. 5C is a sectional view taken along line BB ′ in FIG.
FIG. 4 is a cutaway view showing a cut state. The structure of the MOSFET of this example is p⁻Pattern
Is n⁻Channel formed on semiconductor layer 4 of p-type
A gate insulating layer is formed on the side wall of the diffusion layer 77 and the channel diffusion layer 77.
Trench gate electrode 111 formed via edge film 10
And formed along the upper edge of the trench gate electrode 111.
N⁺Source region 88 and trench gate electrode 1
N formed at a position away from 11⁺Mold drain
The region 99 and the drain extending between the drain and the gate
Drift region 290 and drain / drift region 2
90 and a thick insulating film 12 formed thereon. The drain drift region 29 in this embodiment
0 is the same as that of the third embodiment, and the plate-like n
Drift path region 1 and plate-shaped p-type partition region 2
Are alternately and repeatedly laminated.
Immediately below the lowest n-type split drift path region 1, the p-type side end
Region 2a is formed, and the uppermost n-type divided
The p-type side end region 2a is also formed on the drift path region 1.
You. The net doping amount of this p-type side end region 2a is 2 ×
10¹²/ Cm²The following is assumed. Multiple n-type split drifts
One end of the channel region 1 is connected to the p-type channel diffusion layer 77 by pn.
Joined and their other ends n⁺Type drain region 99
Connected, n⁺Branch from the mold drain 99 side
A parallel drift path group 100 connected in parallel is formed.
One end of each of the plurality of p-type partition regions 2 is a p-type channel.
Connected to the diffusion layer 77, the other ends of which are n⁺Mold dray
P-type channel diffusion layer
It branches from the 77 side and is connected in parallel. In this embodiment, the on-resistance is reduced as in the third embodiment.
And high withstand voltage can be achieved. Note that this example and FIG.
The relationship between the second embodiment shown in FIG.
Corresponds to the first embodiment shown in FIG. Implementation of FIG.
As in the embodiment of FIG.
Therefore, cost can be reduced. [Embodiment 5] FIG. 6A shows an embodiment of the present invention.
15 shows a p-channel MOSFET having a horizontal structure according to a fifth embodiment.
It is sectional drawing and corresponds to the improvement example of FIG.11 (a). The structure of this example is represented by p⁻Form on the mold semiconductor layer 4
The formed n-type channel diffusion layer 3 and the channel diffusion layer 3
Field field formed over the gate insulating film 10
Rated gate electrode 11 and channel diffusion layer 3
P formed on one end of the gate electrode 11⁺Type Source
A well end is formed just below the other end side of the region 18 and the gate electrode 11.
The located p-type drain drift region 14 and the p-type
N-type side formed on the surface layer of drain drift region 14
End region 2b and a position separated from the other end of gate electrode 11
Formed in⁺Type drain region 19 and p⁺Type
N adjacent to the source region 18⁺Mold contact area
71 and the thickness formed on the p-type drain drift 14
Insulating film 12. In the case of this example, the number of divisions of the drain region is one.
Thus, the p-type drain drift region 14 has a straight line on the cross section.
Of the drain path region 1 of FIG. This p-type dress
Thickness of n-type end region 2b on in-drift region 14
Is formed thin to accelerate depletion. FIG.
Compared with the structure of FIG. 7A, in this example, the n-type side end region 2b is
Formed under the p-type drain drift region 14.
Layer from the side channel diffusion layer 3 and the upper n-type side region
The depletion layer from region 2a promotes depletion
You. The net of the drain drift region 14 in FIG.
Doping amount is 1 × 10¹²/ Cm²Is about
On the other hand, in this example, about 2 × 10¹²/ Cm²About twice
It has become. Therefore, the drain voltage can be increased to achieve the high withstand voltage.
The impurity concentration of the in-drift region 14 can be increased.
Lower on-resistance can be achieved. [Embodiment 6] FIG. 6B shows an embodiment of the present invention.
15 shows an n-channel MOSFET having a horizontal structure according to a sixth embodiment.
It is sectional drawing and corresponds to the improvement example of FIG.11 (b). This example is a double diffusion type n-channel MOSFET.
And p⁻Type semiconductor layer 4 (p-type side end region 2a)
The formed drain drift region 22 (for the first n-type
Split drift path region 1) and a gate insulating film 10
The gate electrode 11 with the field plate formed and the gate
One end of the gate electrode 11 in the rain drift region 22
Well-type p-type channel diffusion region 17 formed on the side
And a well formed in the p-type channel diffusion region 17.
N⁺Type source region 8, gate electrode 11 and
Separated n⁺Formed in the surface layer between the drain region 9
P-type top layer 24 (p-type partition region 2) and p-type partition
The second n-type split drift formed on the surface layer of the cut region 2
Road area 1 and n⁺P adjacent to the source region 8⁺Type
Formed on the contact region 72 and the p-type partition region 2.
Thick insulating film 12. Lower Drain Drift Region 22 and Upper Layer
Divided drift path areas 1 are parallel with a p-type partition area 2 interposed therebetween.
Connected. Compared to the structure of FIG.
Has divided drift path regions 1 juxtaposed on p-type partition regions 2.
It is in the point. As described above, the lower layer from the p-type partition region 2
Of the drain drift region 22 and the upper layer
Because the depletion layer spreads on both sides of Road 1,
High breakdown voltage can be achieved, and on-resistance is reduced accordingly.
Can be made. The drift region 22 shown in FIG.
Net doping amount is 2 × 10¹²/ Cm²About
On the other hand, in this embodiment, the lower drain drift region 2
2 and the upper divided drift path region 1
About 3 × 10¹²/ Cm²About 1.5 times
Can be According to the structure of this example,
The trade-off relationship between ideal breakdown voltage and ideal on-resistance
Can be Clearly, the ideal withstand voltage compared to the conventional structure
Can relax the trade-off relationship between
found. Note that, in order to obtain the structures of Embodiments 5 and 6,
As a manufacturing method, first, p⁻To the semiconductor layer 4
Implantation and heat treatment (thermal diffusion) of n-type semiconductor layer 3
After forming (22), the n-type semiconductor layer 3 (22)
For selective boron ion implantation and heat treatment (thermal diffusion) on the surface
Therefore, a p-type region 14 (24) is formed, and thereafter, a thermal acid
High concentration due to segregation of phosphorus on the silicon surface
Of low concentration by concentration and boron segregation into oxide film
N-type end region 2b (n-type split drift path)
Region 1) is formed. n-type end region 2b or n-type split drift
There is no reverse conductivity type layer adjacent to the upper layer of
Therefore, in order to facilitate depletion, the thinner the layer, the better. Obedience
Therefore, the n-type side end region 2b (n-type
The advantage of forming the split drift path 1) is that the number of processes is reduced.
To enable mass production. In the fifth embodiment, the n-type side end region 2b
Is separated from the gate insulating film 10 and the drain drift region 14.
However, since this uses the above manufacturing method,
An n-type end region 2b is formed entirely on the silicon surface layer.
It is because. However, the n-type side end region 2b becomes thin.
For example, the channel inversion layer formed immediately below the gate 10
This causes a problem because the drain drift region 14 is conducting.
I won't. [Embodiment 7] FIG. 7A shows an embodiment of the present invention.
Vertical trench type n-channel according to mode 7
FIG. 7B is a plan view showing the MOSFET, and FIG.
FIG. 8 is a sectional view showing a state cut along the line AA ′ of FIG.
FIG. 7A is a sectional view taken along the line BB ′ in FIG.
FIG. 8B is a cutaway view showing the state, and FIG.
FIG. 9A is a sectional view showing a state of cutting along a line.
7 (a) is a cut showing a state cut along the line DD '.
FIG. 9B is a sectional view taken along line EE ′ in FIG.
FIG. 4 is a cutaway view showing a cut state. In the structure of this embodiment, the back electrode (not shown)
Electrically contacted n⁺Type drain layer 29 and a layer formed thereon.
Drain drift layer 139 and the drain drift
In the trench formed in the surface of the
Gate electrode buried through the gate insulating film 10
21 and a trench in the surface layer of the drain drift layer 139
A p-type channel formed as shallow as the depth of the gate electrode 21
Along the upper layer 27 and the trench gate electrode 21.
N⁺Type source region 18 and gate electrode 21
And a thick insulating film 12 covering the same. Note that a single layer n⁺Type
Instead of the drain layer 29, n⁺Mold upper layer and p⁺Mold lower layer
When a two-layered structure or a p-type layer is formed, an n-type IGBT
Structure can be obtained. The drain drift layer 139 in this embodiment
As shown in FIG. 8 (b) and FIG.
N-type split drift path region 1 and plate-like
Side-by-side parallel with p-type partition areas 2 alternately repeated adjacently
It has a structure. A plurality of n-type split drift path regions 1
Has a pn junction with a p-type channel diffusion layer 27,
Their lower end is n⁺Type drain layer 29,
n⁺Branch from the side of the drain layer 29 of the
A row drift path group 100 is formed. Illustrated
There is no split drift at the outermost end of the parallel drift path group 100
A p-type side end region is provided outside the
All divided drift path areas 1 are p-type along the side
It is sandwiched by the partition region 2 or the p-type side end region. Also,
The upper ends of the p-type partition regions 2 are p-type channel diffusion layers 2.
7 and their lower ends are n⁺Type drain layer 29
A pn junction is formed from the p-type channel diffusion layer 27 side.
They are connected in parallel. When in the off state, the gate insulating film 10
The channel inversion layer 13 disappears, and the drain-source voltage
As a result, the n-type split drift path region 1 and the p-type channel expansion
Pn junction Ja with the diffused layer 27, n-type split drift path region 1
Depletion layers from the pn junction Jb of the
Spreads into the n-type split drift path region 1 and this is depleted.
Is done. Depletion end from pn junction Ja is n-type split drift
Spreads in the length direction of the path in the path area 1, but the pn junction Jb
These depletion ends are in the path width direction within the n-type split drift path region 1.
Depletion due to the depletion edge spreading from both sides
Very quickly. Also, the p-type partition region 2 is simultaneously depleted.
It is. In particular, the n-type region adjacent from both sides of the p-type partition region 2
Make sure that the depletion end enters both split drift paths 1 and 1.
, The p-type partition region 2 for forming the depletion layer
And the total occupation width of the n-type split drift path can be reduced by half.
The cross-sectional area of region 1 can be increased, and
Resistance is reduced. Unit area of n-type split drift path 1
As the number of pieces per unit (number of divisions) increases,
The trade-off relationship with pressure can be greatly reduced. An n-channel MOSFE having an ideal withstand voltage of 100 V
T (conventional structure shown in FIG. 12).
Then, in the case of the conventional structure, as shown in FIG.
Anti-R = about 0.6 (m ohm-cm²), But in this example
, The n-type split drift path region 1 and the p-type partition region 2
Is assumed to be about 5 μm and β = ２, and n
In the stacking direction of the mold split drift path region 1 and the p-type partition region 2
Let the thickness be, for example, 10 μm, 1 μm, 0.1 μm
When calculating, 1.6 (m ohm-cm) when the thickness is 10 μm²) 0.16 (m ohm-cm) when the thickness is 1 μm²) When the thickness is 0.1 μm, 0.016 (m ohm · cm
²) And a dramatic reduction in on-resistance is possible even on the order of μm.
You. The width of the p-type partition region 2 is
If the width is smaller than the width, the effect is still remarkable. n
The width of the mold split drift path region 1 and the p-type partition region is
Currently about 0.5 μm by lithography and ion implantation
Is the limit of mass production level, but steady
With the progress, it is possible to further reduce the width dimension in the future
Thus, the on-resistance can be significantly reduced. As in this example, n-type divisions arranged in the vertical direction
The repeating structure of the drift path region 1 and the p-type partition region 2 is as follows:
There are also some difficulties in the manufacturing method compared to the case of the horizontal semiconductor structure
Is, for example, epitaxially grown on the drain layer 29.
After forming an n-type layer, the n-type layer is striped.
Etching away at intervals
Filling by p-type epitaxial growth, polishing unnecessary parts
A removal method can be employed. Neutron beam
Injection of high energy particles with large range and
Selectively deepen the reverse conductivity type region by using nuclear transmutation
A forming method is also conceivable. The structure according to the present invention is a MOSFET
Drift when ON
Region, which is suitable for a semiconductor region that is depleted when turned off.
IGBT, bipolar transistor, diode
, JFET, thyristor, MESFET, HEMT
And so on can be applied to almost all semiconductor devices. In addition,
The electric type can be appropriately changed to a reverse conductivity type. Also, in FIG.
Layered, fibrous, reticulated or honeycomb-shaped as drift groups
However, the present invention is not limited to this.
Is available. [0059] As described above, the MO according to the present invention is
The drain drift region in the SFET is the substrate plate
A plurality of first conductivity type divisions connected in parallel stacked in the thickness direction
A group of parallel drift paths having a drift path region and a first conductive path;
The second interposed between adjacent ones of the mold splitting drift path area
A conductive type partition region, and the highest level of the parallel drift path group
And outside the lowermost first conductivity type split drift path region.
The second conductive type side end region,
The net doping amount in the mold side end region is 2 × 10¹²cm²
And the first conductivity type divided drift path region and the second
The lengths of the conductive type partition region and the second conductive type side end region are substantially equal.
It is characterized by that. With such a configuration, the first conductivity type component
Depletion is accelerated even if the impurity concentration in the crack drift path region is increased
To reduce the on-resistance and increase the withstand voltage.
An implemented MOSFET can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1C are schematic views showing the structure of a drift region in a semiconductor device according to the present invention. FIG. 2A is a plan view showing an SOI-MOSFET having a lateral structure according to the first embodiment of the present invention, FIG. 2B is a cutaway view showing a state cut along a line AA ′ in FIG. (C) is a cut-away view showing a state cut along the line BB 'in (a). FIG. 3A is a plan view showing a double diffusion type n-channel MOSFET according to a second embodiment of the present invention, and FIG.
FIG. 3C is a sectional view showing a state cut along a line AA ′ in FIG. 4C, and FIG. 4C is a sectional view showing a state cut along a line BB ′ in FIG. FIG. 4A is a plan view showing an SOI-MOSFET having a horizontal structure according to a third embodiment of the present invention, FIG. 4B is a sectional view showing a state cut along line AA ′ in FIG. (C) is a cut-away view showing a state cut along the line BB 'in (a). FIG. 5A is a plan view showing a lateral-structure MOSFET according to a fourth embodiment of the present invention, and FIG.
FIG. 3 is a cutaway view showing a state cut along line A ′, and FIG. 3 (c) is a cutaway view showing a state cut along line BB ′ in FIG. FIG. 6A is a cross-sectional view illustrating a lateral p-channel MOSFET according to a fifth embodiment of the present invention, and FIG. 6B is a lateral n-channel MOSFET according to a sixth embodiment of the present invention;
FIG. FIG. 7A is a plan view illustrating a trench gate type n-channel MOSFET having a vertical structure according to a seventh embodiment of the present invention, and FIG. 7B is a view taken along line AA ′ in FIG. FIG. 4 is a cutaway view showing a cut state. 8A is a sectional view showing a state cut along the line BB 'in FIG. 7A, and FIG. 8B is a sectional view taken along line C-B in FIG. 7B.
It is a sectional view showing the state where it was cut along line C '. 9 (a) is a cross-sectional view showing a state cut along the line DD ′ in FIG. 7 (a), and FIG. 9 (b) is a cross-sectional view taken along line E-
It is a sectional view showing the state where it was cut along the E 'line. FIG. 10 (a) is a conventional horizontal SOI-MOSF structure;
FIG. 2B is a plan view showing ET, and FIG. 11A is a cross-sectional view showing another structure of a conventional MOSFET having a lateral structure, and FIG. 11B is a cross-sectional view showing the structure of a conventional double-diffusion n-channel MOSFET. FIG. 12 shows a conventional trench gate type n-channel MOS.
FIG. 3 is a cross-sectional view showing an FET. FIG. 13 is a graph showing a trade-off relationship between ideal withstand voltage and ideal on-resistance of various silicon n-channel MOSFETs. [Description of Reference Numerals] 1 ... n-type drift regions 1a ... connecting portion 2 ... p-type partition regions 2a ... p-type-side end region 3 ... n-type channel diffusion layer 4 ... p ^- -type semiconductor layer 5 ... semiconductor substrate 6 ... Insulating film 7 p-type channel diffusion layer 8 n ⁺ type source region 9 n ⁺ type drain region 10 gate insulating film 11 gate electrode with field plate 12 thick insulating film 13 channel inversion layer 14 p-type low Concentration region 17 p-type channel diffusion regions 18 and 28 p ⁺ -type source region 19 p ⁺ -type drain region 21 trench gate electrode 22 n-type low-concentration drain layer 24 p-type top layer 27 p-type channel layer 29 n ⁺ type drain layer 39 n type low concentration drain layer 71 n ⁺ type contact region 72 p ⁺ type contact region 77 p type channel diffusion layer 88 n ⁺ type source region 90 n type low concentration drain In region (drain / drift region) 99 p-type drain region 100 parallel drift path group 111 trench gate electrodes 90, 122, 139, 290 drain drift region e depletion end Ja, Jb pn junction.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI H01L 21/338 H01L 29/78 622 29/73 29/72 Z 29/786 29/91 D 29/812 29/80 B 29 / 861 29/78 301V (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 29/78 H01L 21/336

Claims (1)

(57) [Claim 1] A first conductive type channel region formed in a channel region.
A conductive type source region and a gate electrode formed on a side wall of the second conductive type channel region with a gate insulating film interposed therebetween, and between the second conductive type channel region and the first conductive type drain region. In a MOSFET having a drain drift region that extends and causes a drift current to flow in an on state and depletes in an off state, the drain drift region is formed by a plurality of first connected first layers stacked in the thickness direction of the substrate. A parallel drift path group having a conductivity type divided drift path area; and a second conductivity type partition area interposed between adjacent ones of the first conductivity type divided drift path area. made has a second-conductivity-type-side end region outside the first conductivity type drift regions of the uppermost and lowermost, respectively, the net doping amount of the second-conductivity-type-side end region of 2 × 10 ² cm ² or less, and MOS the length of the first conductivity type drift regions and the second conductivity type partition region and the second-conductivity-type-side end region is equal to or substantially equal to
FET.