JP2003332574A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device whose on-resistance is reduced with high breakdown strength by improving the structure of a drift region which is depleted in an OFF mode. <P>SOLUTION: A drain/drift region 190 is configured as a stripe-shaped parallel structure where stripe-shaped n-type divided drift path regions 1 and stripe- shaped p-type compartment regions 2 are alternately arrayed on a plane. One- side edges of a plurality of n-type divided drift path regions 1 are pn-joined to a p-type channel diffusion region 7, and the other edges are connected to an n<SP>+</SP>-type drain region 9 so that a drift path group 100 connected in parallel can be formed so as to be branched from the n<SP>+</SP>-type drain region 9 side. When widths of the n-type divided drift path region 1 and the p-type compartment region 2 are turned to be 1 μm or less respectively, drastic low on-resistance can be obtained. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a high breakdown voltage and a large current capacity, which is applicable to MOSFET (insulated gate type field effect transistor), IGBT (conductivity modulation type transistor), bipolar transistor, diode and the like.

[0002]

2. Description of the Related Art Generally, semiconductor devices can be roughly classified into a horizontal structure having an electrode portion on one surface and a vertical structure having an electrode portion on both surfaces.
For example, FIG. 10 shows an SOI (silicon) having a horizontal structure.
oninsulator) -MOSFET. The structure of this SOI-MOSFET is an n-channel MOSFET
P type channel diffusion layer 7 formed on the insulating film 6 on the semiconductor substrate 5, and a field plate formed on the channel diffusion layer 7 with the gate insulating film 10 interposed therebetween. Gate electrode 11, an n ⁺ type source region 8 formed on one end side of the gate electrode 11 in the channel diffusion layer 7, and an n ⁺ type drain formed at a position separated from the other end of the gate electrode 11. It has a region 9, an n-type low concentration drain region (drain drift region) 90 extending between the drain and the gate, and a thick insulating film 12 formed on the low concentration drain region 90.

The lightly doped drain region 90 is a MOS
When the FET is in the ON state, it functions as a drift region in which carriers are caused to flow by an electric field, and when it is in the OFF state, it is depleted to relax the electric field strength and increase the breakdown voltage. Low concentration drain region 9
Increasing the impurity concentration of 0 and shortening the current path length of the region 90 lead to the effect of lowering the substantial on-resistance (drain-source resistance) of the MOSFET because the drift resistance becomes low, but In addition, since the drain-channel depletion layer that progresses from the pn junction Ja of the p-type channel diffusion layer 7 and the n-type low-concentration drain region 90 is difficult to spread and the maximum (critical) electric field strength of silicon is reached quickly, the breakdown voltage ( The drain-source voltage) will decrease.
That is, there is a trade-off relationship between on-resistance (current capacity) and breakdown voltage. It is known that this trade-off relationship is similarly established in semiconductor devices such as IGBTs, bipolar transistors, and diodes.

FIG. 11 shows another structure of a lateral MOSFET. FIG. 11A shows a p-channel MOSFET, which includes an n-type channel diffusion layer 3 formed on a p ⁻ type semiconductor layer 4 and a field plate formed on the channel diffusion layer 3 with a gate insulating film 10 interposed therebetween. With gate electrode 11
A p ⁺ type source region 18 formed on one end side of the gate electrode 11 in the channel diffusion layer 3, and the gate electrode 11
Of the p-type low-concentration drain region (drain / drift region) 14 whose well end is located directly below the other end side of the gate electrode 1 and
N ⁺ adjacent to the p ⁺ type drain region 19 and the p ⁺ type source region 18 formed at a position separated from the other end of
Type contact region 71 and the thick insulating film 12 formed on the p-type low concentration drain 14. Even in such a structure, the on-resistance and the breakdown voltage are determined in a trade-off relationship by the current path length and the impurity concentration of the well-type p-type low-concentration drain region 14.

FIG. 11B shows a double diffusion type n channel MO.
An SFET, which is an n-type low-concentration drain layer (drain / drift layer) 22 formed on the p ⁻ -type semiconductor layer 4, and a field plate formed on the low-concentration drain layer 22 via the gate insulating film 10. Gate electrode 11, a well-shaped p-type channel diffusion region 17 formed at one end side of the gate electrode 11 in the low-concentration drain layer 22, and an n ⁺ type well formed in the p-type channel diffusion region 17. -Type source region 8 and gate electrode 11 and n spaced apart therefrom
Well-shaped p-type top layer 24 formed in the surface layer between ⁺ type drain region 9, p ⁺ type contact region 72 adjacent to n ⁺ type source region 8, and p type top layer 24.
And a thick insulating film 12 formed thereover. Even in such a structure, the on-resistance and the breakdown voltage are determined by a trade-off relationship depending on the current path length of the n-type low-concentration drain layer region 22 and the impurity concentration.

However, in the structure of FIG. 11B, the n-type low-concentration drain layer 22 is sandwiched between the p ⁻ -type semiconductor layer 4 on the lower side and the p-type top layer 24 on the upper side.
Is off, p with the p-type channel diffusion region 17
Not only from the n-junction Ja but also from the n-type low concentration drain layer 2
The depletion layer also extends from the pn junctions Jb and Jb above and below 2.
Therefore, the low-concentration drain layer 22 is depleted quickly, so that the structure has a high breakdown voltage. As a result, the impurity concentration of the low-concentration drain layer 22 can be increased and the on-resistance can be reduced to increase the current capacity.

On the other hand, as a vertical type semiconductor element, for example, a trench gate type n-channel MOS shown in FIG.
FETs are known. This structure has an n-type low-concentration drain layer 39 formed on an n ⁺ -type drain layer 29 in conductive contact with a back surface electrode (not shown), and a low-concentration drain layer 3.
A trench gate electrode 21 buried in a trench groove dug in the surface side of the semiconductor layer 9 via a gate insulating film 10;
The trench gate electrode 21 is formed on the surface layer of the low-concentration drain layer 39.
P-type channel diffusion layer 27 formed as shallow as the depth of
And an n ⁺ type source region 18 formed along the upper edge of the trench gate electrode 21, and a thick insulating film 12 covering the gate electrode 21. The single layer n ⁺ type drain layer 2
If a two-layer structure including an n ⁺ type upper layer and ap ⁺ type lower layer is used instead of 9, an n type IGBT structure can be obtained. Also in such a vertical structure, the portion of the low-concentration drain layer 39 functions as a drift region that forms a drift current in the vertical direction when the MOSFET is on, and depletes to increase the breakdown voltage when the MOSFET is off. Again, the on-resistance and the breakdown voltage are governed by the thickness of the low-concentration drain layer 39 and the impurity concentration, and there is a trade-off relationship between the two.

[0008]

FIG. 13 shows n of silicon.
7 is a graph showing the relationship between the ideal breakdown voltage and the ideal on-resistance of a channel MOSFET. The ideal breakdown voltage is pn due to the shape effect
It was assumed that the junction breakdown voltage did not decrease. It is assumed that the ideal on-resistance is so small that the resistance of the portion other than the low-concentration drain region can be ignored. 13 shows the relationship between the ideal breakdown voltage and the ideal on-resistance of the vertical n-channel MOSFET shown in FIG. The vertical element has the same direction in which a drift current flows when turned on and the direction in which a depletion layer extends and spreads due to reverse bias when turned off. Focusing only on the low-concentration drain layer 39 of FIG. 12, the ideal breakdown voltage BV at the time of OFF is approximately obtained by the following equation. BV = E _c ² ε ₀ ε _Si α (2-α) / 2qN _D (1) E _c : E _c (N _D ), maximum electric field strength ε ₀ of silicon at impurity concentration N _D : vacuum permittivity ε _Si : relative permittivity of silicon q: unit charge N _D : impurity concentration of low concentration drain region α: coefficient (0 <α <1) Further, the ideal ON resistance per unit area at the time of ON is approximately calculated by the following equation. I want it. R = αW / μqN _D μ: μ (N _D ), mobility of electrons at impurity concentration N _D Here, W = E _c ε ₀ ε _Si / qN _D , so R is R = E _c ε ₀ ε _Si α / μq ² N _D ² (2) (1) is obtained (2) erases the qN _D from equation, using the optimal value as for example 2/3 of the ^{α, R = BV 2 (27} / 8E c 3 ε 0 ε Si μ) (3) . Here, the on-resistance R seems to be proportional to the square of the withstand voltage BV, but since E _c and μ depend on N _D , the value of FIG. 13 is actually the 2.4-2.6 power of BV. It is proportional to the degree.

FIG. 13 shows a horizontal M shown in FIG. 11 (a).
MOSF with OSFET structure replaced with n-channel type
The relationship between the ideal breakdown voltage of ET and the ideal on-resistance is shown. This n
In a channel-type MOSFET, a drift current flows in a lateral direction when turned on, whereas a depletion layer extends in a turned-off direction not substantially from a well end but in a vertical direction (upward direction) from a well bottom. It's faster. In order to obtain a high breakdown voltage in the depletion layer extending in the vertical direction, the depletion layer must be depleted from the pn junction surface (well bottom) between the low concentration drain region 14 and the channel diffusion layer 3 to the surface of the low concentration drain layer 14 (well surface). I have to. Therefore, the maximum value of the net doping amount of the lightly doped drain region 14 is limited to S _D = E _c ε ₀ ε _Si / q (4). When the horizontal length of the low concentration drain region 14 is L, the ideal breakdown voltage BV is BV = E _c Lβ (5). However, β is an unknown coefficient (0 <β <1). Further, the ideal on-resistance R per unit area is approximately obtained by R = L ² / μqS _D (6). Therefore, when L is deleted from the equations (5) and (6) and the equation (4) is substituted, R = BV ² / β ² E _c ³ ε ₀ ε _Si μ (7)

FIG. 13 shows a horizontal type 2 shown in FIG. 11 (b).
The relationship between the ideal breakdown voltage and the ideal ON resistance of the structure of a heavy diffusion type n-channel MOSFET is shown. In the structure of FIG. 11B, the p-type top layer 24 is provided in the structure of FIG. 11A, and the low-concentration drain layer 22 is pinched and early depleted by the depletion layers extending from both upper and lower sides. The net doping amount S _D of the low concentration drain region 22 is shown in FIG.
It is possible to increase it up to about twice as much as that. S _D = 2E _c ε ₀ ε _Si / q (8) In this case, the relationship between the ideal on-resistance R and the ideal breakdown voltage BV is R = BV ² / 2β ² E _c ³ ε ₀ ε _Si μ (9) .

Although the trade-off relationship between the on-state resistance and the withstand voltage is slightly improved as compared with the case of FIG. 13, it is possible to set the concentration to only twice as high as possible, and it is possible to freely design the current capacity and the withstand voltage of the semiconductor element. The degree is still low.

In view of the above problems, an object of the present invention is to improve the structure of the drift region, thereby greatly relaxing the trade-off relationship between the on-resistance and the withstand voltage, so that the on-state is maintained even though the withstand voltage is high. An object of the present invention is to provide a semiconductor device capable of increasing a current capacity by reducing resistance.

[0013]

In order to solve the above-mentioned problems, the means taken by the present invention is, for example, a low-concentration drain region of a MOSFET, in which a drift current flows in an on state and is depleted in an off state. In the semiconductor device having the above, the drift region thereof has a parallel division structure such as a layered structure, a fibrous structure or a honeycomb structure as shown schematically in FIG. 1, and is adjacent to the first conductivity type division drift path region 1. The second conductivity type partition region 2 is provided between the side surfaces (borders) of the two to separate the pn junction.

That is, as shown in FIG. 1A, the drift region is a layered structure having two or more plate-shaped first-conductivity-type (for example, n-type) divided drift route regions 1 which are connected in parallel to each other at least at their ends. A parallel drift path group (divided drift path assembly) 100 having a structure and a plate-shaped second intervening between the divided drift path regions 1 and 1 for separating a pn junction.
And a conductive type (for example, p type) partition region 2. The plurality of second-conductivity-type partition regions 2 are connected in parallel to each other at least at their ends.

The structure of the drift region shown in FIG. 1 (b) is a fibrous structure, and has a stripe-shaped first conductivity type (n-type) divided drift path region 1 and a stripe-shaped second conductivity type (p). The (type) partition area 2 is arranged in a checkered pattern in the cross section of the assembly.

Further, as shown in FIG. 1C, the first conductivity type (n
The (type) divided drift path region 1 has connecting portions 1a at four corners.

As can be seen clearly in FIG. 1A, a pn junction is separated along the outside of the first conductivity type split drift path region 1 at the outermost end (top end or bottom end) of the parallel drift path group 100. The two conductivity type side end region 2a may be provided.

When the semiconductor device is in the ON state, the drift current flows through the plurality of divided drift path regions 1 and 1 connected in parallel, while when the semiconductor device is in the OFF state, the drift current flows through the first conductivity type divided drift path region 1. From the pn junction with the second conductivity type partition region 2, the depletion layer is formed as the first conductivity type divided drift path 1 respectively.
It spreads inside and is depleted. Since the depletion edge spreads laterally from both side surfaces of the linear second-conductivity-type partition region 2, depletion becomes very fast. The second conductivity type partition region 2 is also depleted at the same time. Therefore, the semiconductor device has a high breakdown voltage, and n
Since it is possible to increase the impurity concentration in the mold division drift path region 1, it is possible to reduce the on-resistance. In particular, in the present invention, the depletion end is adapted to enter both of the adjacent first conductivity type divided drift path regions 1, 1 from both side surfaces of the second conductivity type partition region 2, and the depletion that spreads to both sides. Since the end effectively acts on the divided drift route regions 1 and 1, the total occupied width of the second conductivity type partition region 2 for forming the depletion layer can be halved, and the first conductivity type divided drift route can be reduced accordingly. The cross-sectional area of the area 1 can be increased, and the on-resistance can be significantly reduced compared to before. The occupying width of the second conductivity type partition region 2 is preferably small. Further, it is desirable that the impurity concentration of the second conductivity type partition region 2 is low. As the number of the first conductivity type divided drift path regions 1 per unit area (the number of divisions) is increased, the trade-off relationship between the on-resistance and the breakdown voltage can be significantly eased.

In the present invention, the trade-off relational expression between the ideal on-resistance r and the ideal breakdown voltage BV for the straight line type first-conductivity-type divided drift path region 1 is that the width of the second-conductivity-type partition region 2 is infinitely small. Since the ideal on-resistance r of one line corresponds to N times the ideal on-resistance R of the equation (9), r = NR = BV ² / 2β ² E _c ³ ε ₀ ε _Si μ (10) relationship of the ideal on the whole parallel drift path group resistor R and the ideal breakdown voltage BV becomes ^{R = BV 2 / 2Nβ 2 E} c 3 ε 0 ε Si μ (11). Therefore, it is understood that the larger the number of divisions N of the drift region, the more it is possible to realize a semiconductor device with significantly reduced on-resistance.

That is, according to the present invention, in a semiconductor device having a drift region in which a drift current flows in a plane direction of a semiconductor substrate in an on state and is depleted in an off state, the drift region is composed of a plurality of first conductivity types connected in parallel. A structure having a parallel drift route group having a divided drift route region and a second conductivity type partition region interposed between adjacent ones of the first conductivity type divided drift route region, wherein the parallel drift route group is It is characterized in that the structure is alternately repeated in the plane direction of the semiconductor substrate different from the plane direction in which the drift current flows and each width is 1 μm or less. With such a configuration, it is possible to reduce the on-resistance and increase the breakdown voltage.

Further, according to the present invention, a first conductivity type source region formed in the second conductivity type channel region on the surface of the semiconductor substrate and a gate electrode formed on the second conductivity type channel region via a gate insulating film. And the second conductive type channel region and the first conductive type drain region on the surface of the semiconductor substrate are in a plane direction in which a drift current flows. With such a configuration, it is possible to reduce the on-resistance and increase the breakdown voltage.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the accompanying drawings.

[Embodiment 1] FIG. 2A is a plan view showing an SOI-MOSFET having a lateral structure according to Embodiment 1 of the present invention, and FIG. 2B is AA 'in FIG. 2A. 2C is a sectional view showing a state of being cut by a line, and FIG. 2C is B- in FIG.
It is a cutting diagram which shows the state cut | disconnected by the B'line.

Similar to the structure shown in FIG. 10, the structure of the SOI-MOSFET of this example is an offset gate structure of an n-channel MOSFET, and is of a p-type formed on the insulating film 6 on the semiconductor substrate 5. A channel diffusion region 7, a gate electrode 11 with a field plate formed on the channel diffusion region 7 via a gate insulating film 10, and an n ⁺ type formed on one end side of the gate electrode 11 in the channel diffusion region 7. Source region 8 and an n ⁺ -type drain region 9 formed at a position separated from the other end of the gate electrode 11,
It has a drain drift region 190 extending between the drain and the gate, and a thick insulating film 12 formed on the drain drift region 190.

The drain / drift region 19 in this example
0 is a strip-shaped n-type split drift path region 1 and a strip-shaped p.
It has a stripe-shaped parallel structure in which the mold partition regions 2 are alternately and repeatedly arranged on a plane. One end of each of the plurality of n-type divided drift path regions 1 is provided in the p-type channel diffusion region 7 with p.
and n junction, the other ends thereof are formed an n ⁺ -type are connected to the drain region 9 of, n ⁺ -type drift path group 100 connected in parallel branched from the drain region 9 side. A stripe-shaped p-type side end region 2a is provided outside the divided drift route region 1 at the outermost end of the parallel drift route group 100, and all the divided drift route regions 1 are p along the side surface.
It is sandwiched between the type semiconductor regions 2 (2a). One end of each of the plurality of p-type partition regions 2 is connected to the p-type channel diffusion region 7, and the other end thereof is connected to the n ⁺ -type drain region 9 by pn.
They are joined and branched in parallel from the p-type channel diffusion region 7 side.

When the MOSFET is on, carriers (electrons) flow from the n ⁺ type source region 8 into the plurality of n type divided drift route regions 1 through the channel inversion layer 13 immediately below the gate insulating film 10 and the drain.・ Drift current flows due to the electric field due to the voltage between the sources. On the other hand, in the off state, the channel inversion layer 13 immediately below the gate insulating film 10 disappears, and the pn junction J between the n-type split drift route region 1 and the p-type channel diffusion region 7 is caused by the drain-source voltage.
p of a, n-type divided drift path region 1 and p-type partition region 2
A depletion layer spreads from the n-junction Jb into the n-type split drift path region 1 and is depleted. The depletion edge from the pn junction Ja spreads in the path length direction in the n-type split drift path area 1, whereas the depletion edge e from the pn junction Jb spreads in the path width direction in the n-type split drift path area 1. Since the depletion edge spreads from both sides, depletion becomes very fast. The p-type partition region 2 is also depleted at the same time. Therefore, the electric field strength is relaxed and the breakdown voltage becomes high, and the impurity concentration in the n-type split drift path region 1 can be increased correspondingly, so that the on-resistance is reduced. In particular, in this example, the n-type divided drift path regions 1, which are adjacent from both side surfaces of the p-type partition region 2,
Since the depletion edge e enters into both of 1,
The total occupied width of the p-type partition region 2 for forming the depletion layer can be halved, and the cross-sectional area of the n-type divided drift route region 1 can be increased by that amount, and the on-resistance is reduced as compared with the conventional case. .
As the number N (division number) per unit area of the n-type divided drift route region 1 is increased, the trade-off relationship between the on-resistance and the breakdown voltage can be significantly eased. Three or more are more prominent than two. The occupied width of the p-type partition region 2 is preferably small.

Here, assuming that the ideal breakdown voltage BV is 100 V, for example, the impurity concentration N _{D of the} n-type split drift path region 1 is N _D =
3 × 10 ¹⁵ (cm ⁻³ ), the maximum electric field strength of silicon E _c =
3 × 10 ⁵ (V / cm), electron mobility μ = 1000
(Cm ² / V · sec), vacuum permittivity ε ₀ = 8.8 ×
10 ⁻¹² (C / V · m), relative permittivity of silicon ε _Si = 1
2, unit charge q = 1.6 × 10 ⁻¹⁹ (C). Figure 1
In the low-concentration drain region 90 shown in 0, the length is 6.6 μm.
When the thickness is m and the thickness is 1 μm, the ideal on-resistance R is 9.1 (m ohm · cm ² ). On the other hand, in this example, the widths of the n-type divided drift path region 1 and the p-type partition region 2 are set to, for example, 10
When the ideal on-resistance R is calculated as values of μm, 1 μm, and 0.1 μm (β = 2/3, assuming that the length of the n-type split drift path region 1 and the p-type partition region is 5 μm), the width is 10 μm , 7.9 (m ohm · cm ² ) width 1 μm,
When 0.8 (m ohm · cm ² ) width 0.1 μm,
It becomes 0.08 (m ohm · cm ² ), and when the width becomes 1 μm or less, a dramatic reduction in on-resistance can be achieved. If the width of the p-type partition region 2 is made smaller than the width of the n-type divided drift path region 1, the effect becomes more remarkable. The width of the n-type split drift path region 1 and the p-type partition region is currently limited to about 0.5 μm due to photolithography and ion implantation at the mass production level limit, but due to steady progress in microfabrication technology, further width dimension will be increased in the future. Since the size can be reduced, the on-resistance can be significantly reduced.

In particular, the structure of the drift region of this example is a repeating structure of pn stripes on a plane, and therefore 1
Since it can be formed by one-time photolithography, the cost of the device can be reduced by simplifying the manufacturing process.

[Embodiment 2] FIG. 3A is a plan view showing a double diffusion type n-channel MOSFET according to Embodiment 2 of the present invention, and FIG. 3B is an AA line in FIG. 3A. A cutaway view showing a state cut along the line ', FIG. 3C shows B in FIG. 3A.
It is a sectional view showing a state of being cut along line -B '.

Double-diffused n-channel MOSFET of this example
11B is an improvement of the structure shown in FIG. 11B, and includes a drain / drift region 122 formed on the p ⁻ type or n ⁻ type semiconductor layer 4 and a gate on the drain / drift region 122. A gate electrode 11 with a field plate formed via an insulating film 10, a well-shaped p-type channel diffusion region 17 formed on one end side of the gate electrode 11 in the drain / drift region 122, and a p-type channel diffusion region. An n ⁺ type source region 8 formed in a well shape in 17; an n ⁺ type drain region 9 separated from the gate electrode 11; and a thick insulating film 12 formed on the drain / drift region 122.

The drain / drift region 12 in this example
2 also has a striped parallel structure in which strip-shaped n-type divided drift path regions 1 and strip-shaped p-type partition regions 2 are alternately and repeatedly arranged on a plane, as in Example 1 shown in FIG. Has become. And a plurality of n-type split drift path regions 1
One end is pn-junctioned to the p-type channel diffusion region 17,
The other ends thereof are connected to the n ⁺ type drain region 9, and branch from the n ⁺ type drain 9 side to form a parallel drift path group 100 connected in parallel. A p-type side end region 2a for sandwiching the divided drift route region 1 at the outermost end of the parallel drift route group 100 is provided, and all the divided drift route regions 1 are p-type along the side surface. It is sandwiched between regions 2 (2a). Further, one end of the plurality of p-type partition regions 2 is connected to the p-type channel diffusion region 7,
The other ends thereof are pn-junctioned with the n ⁺ type drain region 9 and branched from the side of the p type channel diffusion region 7 to be connected in parallel.

Also in the present example, when in the off state, pn
The depletion end from the junction Jb spreads in the path width direction in the n-type split drift path region 1, and further, the depletion ends spread from both side surfaces, so that depletion becomes very fast. At the same time, the p-type partition area 2
Is also depleted. Therefore, similarly to the first embodiment, the breakdown voltage is high and the impurity concentration in the n-type divided drift path region 1 can be increased, so that the on-resistance can be reduced.

Here, comparing the conventional structure shown in FIG. 11B with an ideal withstand voltage of 100 V, the ON resistance of the conventional structure shown in FIG. 11B is about 0.5 (m ohm · cm ² ).
On the other hand, in the structure of this example, the thickness of the split drift path region 1 and the p-type partition region 2 is 1 μm, as in the first embodiment.
When the width is 0.5 μm, the on-resistance is 0.4 (m ohm · cm ² ). By further reducing the widths of the divided drift path region 1 and the p-type partition region 2, it is possible to greatly reduce the on-resistance. By increasing the thickness of the divided drift route region 1 and the p-type partition region 2, it is possible to increase the resistance cross-sectional area of the divided drift route 1 and reduce the on-resistance. For example, if it is 10 μm, the on-resistance is 1/1
The on-resistance can be reduced to 1/100 by setting the thickness to 0 or 100 μm. In order to dope such a thick region, impurity ion implantation may be performed at the same site with a plurality of (or continuously different) energies.

[Third Embodiment] FIG. 4A is a plan view showing a lateral structure SOI-MOSFET according to a third embodiment of the present invention, and FIG. 4B is a sectional view taken along line AA ′ in FIG. 4A. FIG. 4C is a cross-sectional view showing a state of being cut by a line, and B- in FIG.
It is a cutting diagram which shows the state cut | disconnected by the B'line.

In the structure of the SOI-MOSFET of this example, the p-type channel diffusion layer 77 formed on the insulating film 6 on the semiconductor substrate 5 and the gate insulating film 10 on the side wall of the channel diffusion layer 77 are interposed. Formed trench gate electrode 11
1, an n ⁺ type source region 88 formed along the upper edge of the trench gate electrode 111, and the trench gate electrode 1
11, an n ⁺ type drain region 99 formed at a position separated from 11, a drain drift region 290 extending between the drain and the gate, and the drain drift region 29.
0, and a thick insulating film 12 formed on the surface.

Drain / drift region 29 in this example
Different from the case of the first embodiment, 0 has a superposition parallel structure in which a plate-shaped n-type divided drift path region 1 and a plate-shaped p-type partition region 2 are alternately repeatedly stacked and laminated. A p-type side end region 2a is formed immediately below the lowest n-type split drift route region 1, and a p-type side end region 2a is also formed on the highest n-type split drift route region 1. ing. The net doping amount of the p-type side end region 2a is set to 2 × 10 ¹² / cm ² or less. One end of each of the plurality of n-type divided drift path regions 1 is a p-type channel diffusion layer 7
7 are pn-junctioned, the other ends of which are connected to the n ⁺ -type drain region 99, and branch from the n ⁺ -type drain 99 side to form a parallel-connected parallel drift path group 100. One end of each of the plurality of p-type partition regions 2 is connected to the p-type channel diffusion layer 77, and the other end thereof is pn-junctioned to the n ⁺ -type drain region 99. It is branched from the side and connected in parallel.

Also in this layered structure, the ideal on-resistance is given by the above equation (11), and N is the number of stacked n-type divided drift path regions 1. When the ideal breakdown voltage is 100 V, in the conventional structure (N = 1), the ideal on-resistance R = 0.
Although it is 5 (m ohm · cm ² ), in this example, when N = 10, R = 0.05 (m ohm · cm ² ), and the on-resistance is drastically reduced in inverse proportion to the division number N.

By the way, while the key technologies of the embodiments shown in FIGS. 2 and 3 are photolithography and ion implantation, the key technology of the present embodiment shown in FIG. 4 is a plate-shaped n-type divided drift path region. 1 and a plate-like p-type partition region 2 are alternately and repeatedly laminated. As the number of stacked layers is increased, the total thickness becomes thicker and the time required for crystal growth becomes longer, so that the disorder of the impurity distribution due to the diffusion of impurities cannot be ignored.
Ideally, it is preferable that the n-type split drift path region 1 and the p-type partition region 2 are formed as thin as possible, and the crystal is grown at a low temperature at which the disorder of the impurity distribution can be ignored. For that purpose, MOCVD (Metal Organic Chemical Vapor Decomposition Crystal Growth Method) and M used in compound semiconductors such as gallium-arsenic are used rather than the epitaxial growth method which is widely used in silicon technology.
BE (molecular beam crystal growth method) is suitable. According to this, the layer thickness of the layered n-type divided drift path region 1 and the layered p-type partition region 2 can be made fine, and the on-resistance can be significantly reduced.

In this example, if the n-type split drift path region 1 and the p-type partition region 2 are thinly formed to increase the impurity concentration, it becomes difficult to form the channel inversion layer 13 and it is difficult to lower the channel resistance. As a result, it is difficult to reduce the on-resistance. In order to improve this, it is effective to locally make a portion of the n-type divided drift route region 1 and the p-type partition region 2 in contact with the gate insulating film 10 into a low concentration region.

[Fourth Embodiment] FIG. 5A is a plan view showing a lateral structure MOSFET according to a fourth embodiment of the present invention, and FIG. 5B is a line AA ′ in FIG. 5A. FIG. 5C is a sectional view showing a state of being cut, and FIG. 5C is a sectional view showing a state of being cut along the line BB ′ in FIG.

In the structure of the MOSFET of this example, the p-type channel diffusion layer 77 formed on the p ^- type or n ^- type semiconductor layer 4 and the gate insulating film 10 on the side wall of the channel diffusion layer 77 are interposed. A trench gate electrode 111 formed by
N formed along the upper edge of the trench gate electrode 111
^{A +} type source region 88 and an n ⁺ type drain region 99 formed at a position separated from the trench gate electrode 111.
A drain drift region 290 extending between the drain and the gate, and the thick insulating film 12 formed on the drain drift region 290.

Drain / drift region 29 in this example
0 is the same as in the third embodiment, and the plate-shaped n
Mold division drift path area 1 and plate-shaped p-type partition area 2
It has a parallel structure in which and are repeatedly stacked alternately.
A p-type side end region 2a is formed immediately below the lowest n-type split drift route region 1, and a p-type side end region 2a is also formed on the highest n-type split drift route region 1. ing. The net doping amount of the p-type side end region 2a is 2 ×
It is 10 ¹² / cm ² or less. One end of each of the plurality of n-type divided drift path regions 1 is pn-junctioned with the p-type channel diffusion layer 77, and the other end thereof is connected to the n ⁺ -type drain region 99, and the n ⁺ -type drain 99 side To form a parallel drift path group 100 connected in parallel. Further, one end of each of the plurality of p-type partition regions 2 has a p-type channel diffusion layer 7
7 and the other ends thereof are n ⁺ type drain regions 99.
And a pn junction is formed, and branches from the side of the p-type channel diffusion layer 77 are connected in parallel.

As in the third embodiment, this example can reduce the on-resistance and increase the breakdown voltage. The relationship between this example and the third embodiment shown in FIG. 4 is the same as that of the second embodiment shown in FIG.
This corresponds to the relationship with the first embodiment shown in FIG. Similar to the embodiment of FIG. 3 with respect to the embodiment of FIG. 2, the cost can be reduced in this example because it is not SOI.

[Fifth Embodiment] FIG. 6A is a cross-sectional view showing a p-channel MOSFET having a lateral structure according to a fifth embodiment of the present invention, and corresponds to an improved example of FIG. 11A.

The structure of this example is such that the n-type channel diffusion layer 3 formed on the p ⁻ type semiconductor layer 4 and the gate electrode with the field plate formed on the channel diffusion layer 3 via the gate insulating film 10. 11, a p ⁺ type source region 18 formed on one end side of the gate electrode 11 in the channel diffusion layer 3, and a p-type drain drift region 14 whose well end is located directly below the other end side of the gate electrode 11. an n-type-side end region 2b formed on the surface layer of the p-type drain drift region 14, and p ⁺ -type drain region 19 formed at a position spaced from the other end of the gate electrode 11, p ⁺ -type An n ⁺ type contact region 71 adjacent to the source region 18 and p
Thick insulating film 1 formed on the mold drain drift 14
2 and.

In this example, the number of divisions of the drain region is 1.
Thus, the p-type drain / drift region 14 corresponds to a linear divided drain path region 1 in cross section. The thickness of the n-type side end region 2b above the p-type drain / drift region 14 is formed thin in order to accelerate depletion. Figure 11
Compared to the structure of (a), in this example, the n-type side end region 2b is formed, and the depletion layer from the channel diffusion layer 3 below the p-type drain / drift region 14 and the upper n-type side end are formed. The depletion layer from the region 2a promotes depletion. The net doping amount of the drain / drift region 14 in FIG. 11A is about 1 × 10 ¹² / cm ² , whereas it is about 2 × 10 ¹² / cm ² in this example, which is double. Therefore, the impurity concentration of the drain / drift region 14 can be increased as much as the high breakdown voltage can be realized, and the low on-resistance can be achieved.

[Sixth Embodiment] FIG. 6B is a sectional view showing an n-channel MOSFET having a lateral structure according to a sixth embodiment of the present invention, and corresponds to an improved example of FIG. 11B.

This example is a double diffusion type n-channel MOSFET.
And the drain / drift region 22 (first n-type divided drift route region 1) formed on the p ⁻ type semiconductor layer 4 (p-type side end region 2 a) and the gate insulating film 10. A gate electrode 11 with a field plate, a well-shaped p-type channel diffusion region 17 formed on one end side of the gate electrode 11 in the drain / drift region 22,
n formed in a well shape in the p-type channel diffusion region 17
P formed on the surface layer between the ⁺ type source region 8 and the gate electrode 11 and the n ⁺ type drain region 9 separated from the gate electrode 11.
Mold top layer 24 (p-type partition region 2) and p-type partition region 2
Second n-type split drift path region 1 formed on the surface layer of
And a p ⁺ type contact region 72 adjacent to the n ⁺ type source region 8 and a thick insulating film 12 formed on the p type partition region 2.

The lower drain / drift region 22 and the upper divided drift route region 1 are connected in parallel with the p-type partition region 2 interposed therebetween. Compared to the structure of FIG. 11B, in this example, the divided drift path region 1 is provided in parallel on the p-type partition region 2. As described above, since the depletion layer spreads from the p-type partition region 2 to both the drain / drift region 22 in the lower layer and the divided drift path region 1 in the upper layer,
A high breakdown voltage can be achieved, and the ON resistance can be reduced accordingly. While the net doping amount of the drift region 22 in FIG. 11B is about 2 × 10 ¹² / cm ^{2, the} doping amount of the drain / drift region 22 in the lower layer and the divided drift path region 1 in the upper layer in this example. Can be multiplied by 1.5, which is about 3 × 10 ¹² / cm ² . According to the structure of this example, it is possible to obtain the trade-off relationship between the ideal breakdown voltage and the ideal on-resistance shown in FIG. Obviously, it was found that the trade-off relationship between the ideal breakdown voltage and the ideal on-resistance can be relaxed compared to the conventional structure.

As a manufacturing method for obtaining the structures of the fifth and sixth embodiments, first, the n type semiconductor layer 3 is formed by ion implantation of phosphorus into the p ⁻ type semiconductor layer 4 and heat treatment (thermal diffusion).
After forming (22), a p-type region 14 (24) is formed by selective ion implantation of boron and heat treatment (thermal diffusion) on the surface of the n-type semiconductor layer 3 (22), and then thermal oxidation is performed. A thin n-type side edge region 2b (n-type split drift path region 1) is formed on the surface layer by applying a high concentration by segregation of phosphorus on the silicon surface and a low concentration by boron segregation in the oxide film after the treatment. To form. Since the opposite conductivity type layer is not adjacent to the upper layer of the n-type side end region 2b or the n-type split drift path region 1, a thin layer is preferable to facilitate depletion. Therefore, the advantage that the n-type side end region 2b (n-type divided drift path 1) can be formed only by the thermal oxidation treatment step contributes to the reduction of the number of steps and enables mass production.

In the fifth embodiment, the n-type side end region 2b is formed.
Is separated from the gate insulating film 10 and the drain / drift region 14 by using the above manufacturing method.
This is because the n-type side end region 2b is entirely formed on the silicon surface layer. However, if the n-type side end region 2b is thin, no problem occurs because the drain / drift region 14 becomes conductive due to the channel inversion layer formed immediately below the gate 10.

[Seventh Embodiment] FIG. 7A is a plan view showing a trench gate type n-channel MOSFET having a vertical structure according to a seventh embodiment of the present invention. FIG. 7B is a plan view of FIG. 7A. 8 is a sectional view showing a state of being cut along the line AA ′ in FIG.
7A is a sectional view showing a state of being cut along the line BB ′ in FIG. 7A, and FIG. 8B is CC ′ in FIG. 7B.
9A is a sectional view showing a state of being cut along the line, FIG. 9A is a sectional view showing a state of being cut along the line D-D ′ in FIG. 7A, and FIG. It is a cutting diagram which shows the state cut | disconnected along the EE 'line in a).

In the structure of this example, an n ⁺ type drain layer 29 having a back surface electrode (not shown) in conductive contact, a drain / drift layer 139 formed thereon, and a surface side of the drain / drift layer 139 are provided. Trench gate electrode 2 embedded in a trench groove dug in via a gate insulating film 10.
1, the p-type channel layer 27 formed shallowly to the surface of the drain / drift layer 139 to the depth of the trench gate electrode 21, and the n ⁺ type source region 18 formed along the upper edge of the trench gate electrode 21. And a thick insulating film 12 that covers the gate electrode 21. Instead of the single-layer n ⁺ -type drain layer 29, an n ⁺ -type upper layer and a p ⁺ -type lower layer 2
With a layered structure or a p-type layer, an n-type IGBT structure can be obtained.

Drain / drift layer 139 in this example
As shown in FIGS. 8B and 9, is a horizontal side-by-side parallel structure in which plate-shaped n-type divided drift path regions 1 in the vertical direction and plate-shaped p-type partition regions 2 in the vertical direction are alternately and repeatedly adjacent to each other. Has become. Multiple n-type split drift path regions 1
Has a pn-junction with the p-type channel diffusion layer 27, and their lower ends are connected with the n ⁺ -type drain layer 29.
A parallel drift path group 100 of parallel connection is formed by branching from the ⁺ type drain layer 29 side. Although not shown, a p-type side end region is provided outside the divided drift route region 1 at the outermost end of the parallel drift route group 100, and all the divided drift route regions 1 are p-type along the side surface. It is sandwiched between the partition region 2 or the p-type side end region. Also, multiple p
The upper end of the mold partition region 2 is connected to the p-type channel diffusion layer 27, and the lower end thereof is pn-junctioned to the n ⁺ -type drain layer 29. It is connected.

In the off state, the channel inversion layer 13 immediately below the gate insulating film 10 disappears, and the pn junction Ja between the n-type split drift path region 1 and the p-type channel diffusion layer 27 is caused by the drain-source voltage. n-type split drift path region 1
A depletion layer spreads from the pn junction Jb between the p-type partition region 2 and the p-type partition region 2 into the n-type split drift path region 1 and is depleted. The depletion edge from the pn junction Ja spreads in the path length direction in the n-type split drift path area 1, while the depletion edge from the pn junction Jb spreads in the path width direction in the n-type split drift path area 1 and on both sides. Since the depletion edge spreads from the surface, depletion becomes very fast. The p-type partition region 2 is also depleted at the same time. In particular, since the depletion edge enters from both side surfaces of the p-type partition region 2 to both of the adjacent n-type split drift paths 1 and 1, the p-type partition region 2 for forming the depletion layer is formed.
Can be halved, and the cross-sectional area of the n-type divided drift route region 1 can be increased correspondingly, and the on-resistance is reduced as compared with the conventional case. As the number of n-type divided drift paths 1 per unit area (the number of divisions) is increased, the trade-off relationship between the on-resistance and the breakdown voltage can be significantly eased.

N-channel MOSFET with ideal withstand voltage of 100V
Compared with the ideal on-resistance in T (conventional structure shown in FIG. 12), in the case of the conventional structure, the ideal on-resistance R = about 0.6 (m ohm · cm ² ) is obtained according to FIG. In this case, assuming that the depth (path length) of the n-type split drift route region 1 and the p-type partition region 2 is about 5 μm and β = 2/3, the n-type split drift route region 1 and the p-type partition region 2 are assumed. When the thickness in the stacking direction is calculated as values of 10 μm, 1 μm, and 0.1 μm, for example, when the thickness is 10 μm, 1.6 (m ohm · cm ² ) and when the thickness is 1 μm, 0.16 (m Ohm · cm ² ) 0.016 (m ohm · cm) when the thickness is 0.1 μm
² ), and it is possible to dramatically reduce the on-resistance even in the μm order. If the width of the p-type partition region 2 is made smaller than the width of the n-type divided drift path region 1, the effect becomes more remarkable. n
The width of the mold division drift path region 1 and the p-type partition region is currently limited to about 0.5 μm due to photolithography and ion implantation at the mass production level limit, but due to steady progress in microfabrication technology, the width will be further reduced in the future. Therefore, the on-resistance can be significantly reduced.

As in this example, the repeating structure of the n-type divided drift path region 1 and the p-type partition region 2 arranged vertically is
Although it is difficult in terms of manufacturing method compared to the case of a lateral semiconductor structure, for example, after forming an n-type layer by epitaxial growth on the drain layer 29, the n-type layer is removed by etching in stripes. It is possible to adopt a method of filling the etching groove with p-type epitaxial growth and polishing and removing an unnecessary portion. Further, a method of selectively forming a deep region of the opposite conductivity type by selectively implanting neutron rays or high-energy particles with a large range and transmutation resulting therefrom is also conceivable.

The structure according to the present invention is a MOSFET.
Can be applied to not only the drain / drift region but also a semiconductor region that becomes a depletion region when turned on and becomes a depletion region when turned off, and almost all semiconductor devices such as IGBT, bipolar transistor, diode, JFET, thyristor, MESFET, HEMT. Is applicable to. Further, the conductivity type can be appropriately changed to the opposite conductivity type. Further, in FIG. 1, a layered shape, a fibrous shape, a net shape, or a honeycomb shape is shown as the parallel division drift group, but the present invention is not limited to this, and other repeating shapes can be adopted.

[0059]

As described above, the drift region in the present invention includes the parallel drift route group having a plurality of first conductivity type divided drift route regions connected in parallel and the first conductivity type divided drift route region adjacent to each other. And a second conductivity type partition region interposed between the parallel drift paths, and the parallel drift path groups are alternately repeated in the plane direction of the semiconductor substrate different from the plane direction in which the drift current flows, and each width is 1 μm. It is characterized by the following. With such a configuration, it is possible to reduce the on-resistance and increase the breakdown voltage.

[Brief description of drawings]

1A to 1C are schematic views showing the structure of a drift region in a semiconductor device according to the present invention.

2A is a plan view showing an SOI-MOSFET having a lateral structure according to Embodiment 1 of the present invention, FIG. 2B is a sectional view showing a state cut along the line AA ′ in FIG. (C) is a sectional view showing a state of cutting along the line BB ′ in (a).

3A is a plan view showing a double diffusion type n-channel MOSFET according to a second embodiment of the present invention, and FIG. 3B is a plan view of FIG.
FIG. 3C is a sectional view showing a state cut along the line AA ′ in FIG. 6C, and FIG. 7C is a sectional view showing a state cut along the line BB ′ in FIG.

4A is a plan view showing an SOI-MOSFET having a lateral structure according to a third embodiment of the present invention, FIG. 4B is a sectional view showing a state cut along line AA ′ in FIG. (C) is a sectional view showing a state of cutting along the line BB ′ in (a).

5A is a plan view showing a lateral structure MOSFET according to a fourth embodiment of the present invention, and FIG. 5B is a view showing A- in FIG.
A sectional view showing a state cut along the line A ', and (c) is a sectional view showing a state cut along the line BB' in (a).

6A is a sectional view showing a p-channel MOSFET having a lateral structure according to Embodiment 5 of the present invention, and FIG. 6B is an n-channel MOSFET having a lateral structure according to Embodiment 6 of the present invention.
FIG.

7A is a plan view showing a trench gate type n-channel MOSFET having a vertical structure according to a seventh embodiment of the present invention, and FIG. 7B is a view taken along line AA ′ in FIG. It is a cutting diagram which shows the state cut.

8A is a sectional view showing a state of being cut along the line BB ′ in FIG. 7A, and FIG. 8B is a sectional view taken along line C- in FIG. 7B.
It is a cutting diagram showing the state cut along the line C '.

9A is a sectional view showing a state of being cut along the line D-D 'in FIG. 7A, and FIG. 9B is a sectional view taken along line E- in FIG. 7A.
It is a sectional view showing the state cut along line E '.

FIG. 10A is a conventional lateral structure SOI-MOSF.
The top view which shows ET, (b) is the sectional drawing.

11A is a sectional view showing another structure of a conventional lateral MOSFET, and FIG. 11B is a sectional view showing a structure of a conventional double-diffused n-channel MOSFET.

FIG. 12 is a conventional trench gate type n-channel MOS.
It is sectional drawing which shows FET.

FIG. 13 is a graph showing a trade-off relationship between ideal breakdown voltage and ideal on-resistance of various silicon n-channel MOSFETs.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... n-type division | segmentation drift path area 1a ... connection part 2 ... p-type partition area 2a ... p-type side edge area 3 ... n-type channel diffusion layer 4 ... p ^- type semiconductor layer 5 ... semiconductor base 6 ... insulating film 7 ... p type channel diffusion layer 8 ... n ⁺ -type source region 9 ... n ⁺ -type drain region 10 ... gate insulating film 11 ... field plate with gate electrode 12 ... thick insulating film 13 ... channel inversion layer 14 ... p-type low-concentration region 17 ... p Type channel diffusion regions 18, 28 ... P ⁺ type source region 19 ... p ⁺ type drain region 21 ... trench gate electrode 22 ... n type low concentration drain layer 24 ... p type top layer 27 ... p type channel layer 29 ... n ⁺ type drain layer 39 ... n-type low-concentration drain layer 71 ... n ⁺ -type contact region 72 ... p ⁺ -type contact region 77 ... p-type channel diffusion layer 88 ... n ⁺ -type source region 90 ... n-type lightly doped drain region (drain-drift Region) 99 ... p-type drain region 100 ... parallel drift path group 111 ... trench gate electrode 90,122,139,290 ... drain drift region e ... depletion end Ja, Jb ... pn junction.

Front page continuation (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/06 301 H01L 29/78 301D 29/786 301X 29/861 618E 617K 616T 29/91 DF Term (reference) 5F110 AA13 AA30 CC10 DD05 DD13 EE22 GG02 GG12 GG19 GG30 GG42 GG44 HJ04 HM02 HM12 HM14 5F140 AA25 AA30 AC01 AC21 AC36 BA01 BD18 BF01 BF42 BF43 BF44 BH12 BH13 BH14 BH18 BH30 BH41 BH47 B47

Claims (2)

[Claims] 1. A semiconductor device having a drift region in a semiconductor substrate in which a drift current flows in a plane direction of a semiconductor substrate in an on state and is depleted in an off state, wherein the drift region comprises a plurality of first conductivity types connected in parallel. A structure having a parallel drift route group having a divided drift route region and a second conductivity type partition region interposed between adjacent ones of the first conductivity type divided drift route region, wherein the parallel drift route group is provided. Is a structure in which the drift current is alternately repeated in a plane direction of the semiconductor substrate different from the plane direction in which the drift current flows, and each width is 1 μm or less. 2. A first conductivity type source region formed in a second conductivity type channel region on a surface of a semiconductor substrate, and a gate electrode formed on the second conductivity type channel region with a gate insulating film interposed therebetween. 2. The semiconductor device according to claim 1, wherein a space between the second conductivity type channel region and the first conductivity type drain region on the surface of the semiconductor substrate is a plane direction in which a drift current flows.