CN115602677A - Low-trigger high-holding-voltage bidirectional silicon controlled rectifier electrostatic protection device and manufacturing method thereof - Google Patents
Low-trigger high-holding-voltage bidirectional silicon controlled rectifier electrostatic protection device and manufacturing method thereof Download PDFInfo
- Publication number
- CN115602677A CN115602677A CN202110774825.9A CN202110774825A CN115602677A CN 115602677 A CN115602677 A CN 115602677A CN 202110774825 A CN202110774825 A CN 202110774825A CN 115602677 A CN115602677 A CN 115602677A
- Authority
- CN
- China
- Prior art keywords
- well
- injection region
- region
- type
- field oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002457 bidirectional effect Effects 0.000 title claims abstract description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 14
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 14
- 239000010703 silicon Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000002347 injection Methods 0.000 claims abstract description 214
- 239000007924 injection Substances 0.000 claims abstract description 214
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000002955 isolation Methods 0.000 claims description 98
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 18
- 229910052760 oxygen Inorganic materials 0.000 claims description 18
- 239000001301 oxygen Substances 0.000 claims description 18
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- 239000000377 silicon dioxide Substances 0.000 claims description 12
- 235000012239 silicon dioxide Nutrition 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 239000007943 implant Substances 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 4
- 238000004528 spin coating Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 230000005012 migration Effects 0.000 claims description 3
- 238000013508 migration Methods 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 description 20
- 238000002513 implantation Methods 0.000 description 12
- 230000015556 catabolic process Effects 0.000 description 11
- 238000012423 maintenance Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 230000003068 static effect Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thyristors (AREA)
Abstract
The embodiment of the invention provides a bidirectional controllable silicon electrostatic protection device with low trigger and high holding voltage and a manufacturing method thereof, wherein the bidirectional controllable silicon electrostatic protection device comprises a P-type substrate, an N-type buried layer and an N-type trap; a first P well is arranged on the left side of the N-type buried layer, and a second P well is arranged on the right side of the N-type buried layer; a first P + injection region, a first N + injection region and a first floating P + injection region are arranged in the first P well, an N-type well is arranged between the first P well and the second P well, a middle N + injection region is arranged in the middle of the N-type well, and meanwhile, a first P-type shallow well PB and a second P-type shallow well PB are respectively arranged across the middle positions of the first P well, the N-type well and the second P well; a first high-voltage N well and a second high-voltage N well are respectively arranged on the left side and the right side above the N-type buried layer; the first P + injection region and the first N + injection region are connected together and used as an anode of the device, and the second P + injection region and the second N + injection region are connected together and used as a cathode of the device, so that the device can effectively protect a core circuit of a chip and is far away from the risk of latch-up.
Description
Technical Field
The invention relates to the field of electrostatic protection, in particular to a bidirectional silicon controlled electrostatic protection device with low trigger and high maintenance voltage and a manufacturing method thereof.
Background
With the progress of semiconductor manufacturing processes, the failure of integrated circuit chips and electronic products caused by ESD is becoming more serious. ESD protection of electronic products and integrated circuit chips has become one of the major challenges facing product engineers.
Compared with other ESD devices, the traditional Silicon Controlled Rectifier (SCR) device has the advantages of double-conductance modulation mechanism, high unit area discharge efficiency, small unit parasitic capacitance, best robustness and the like. However, the traditional silicon controlled rectifier device has the defects of over-high trigger voltage, over-low maintaining voltage of the device after hysteresis and the like, the protection device cannot timely protect the kernel circuit due to the over-high trigger voltage, the latch-up effect of the device is caused due to the over-low maintaining voltage, and the integrity of signals transmitted by the I/O port cannot be ensured.
The bidirectional thyristor device is improved on the basis of the traditional thyristor, can be considered as the integration of some anti-parallel connected common thyristors, has the same working principle as the traditional unidirectional thyristor, and can clamp the voltage in positive and negative directions respectively. The cross-sectional view of the conventional triac electrostatic protection device is shown in fig. 1, and the equivalent circuit diagram thereof is shown in fig. 2. When the ESD pulse is applied to the anode of the bidirectional SCR, the N-type deep well and the third P + injection region form a reverse bias PN node. When the pulse voltage is higher than the avalanche breakdown voltage of the PN junction, a large amount of avalanche current is generated in the device, and the current circulation path flows to the other end, namely the cathode, through the second P-well parasitic resistor. When the voltage across the parasitic well resistor is higher than the forward conduction voltage of the NPN transistor, the transistor turns on. After the triode is switched on, base current is provided for the transverse PNP triode, and after the transverse PNP triode is also switched on, base current is also provided for the longitudinal NPN triode, so that a positive feedback loop is formed. Therefore, even if there is no avalanche current after the switching, the transistor can discharge static electricity. The bidirectional SCR is of a symmetrical structure, and when an ESD pulse occurs at the cathode, PN junction avalanche breakdown is generated between the N-type deep well and the second P + injection region, so that the PNP triode and the NPN triode are sequentially conducted to discharge static electricity. However, the conventional SCR has the disadvantages of high trigger voltage and low holding voltage, which may cause the device to easily exceed the design window and cause latch-up, so that the trigger voltage needs to be reduced to ensure that the device timely turns on the protection core circuit when the ESD current arrives, and the holding voltage of the triac is increased to avoid the latch-up.
Disclosure of Invention
The invention provides a bidirectional thyristor electrostatic protection device with simple structure, low triggering voltage and high maintaining voltage and a manufacturing method thereof.
In order to achieve the above purpose, the technical solution of the embodiment of the present invention is implemented as follows:
the embodiment of the invention provides a bidirectional thyristor electrostatic protection device with low trigger and high maintenance voltage, which comprises a P-type substrate;
an N-type buried layer is arranged in the P-type substrate;
an N-type trap is arranged in the middle above the N-type buried layer;
a first P well is arranged on the left side of the N-type buried layer, and a second P well is arranged on the right side of the N-type buried layer;
a first P + injection region, a first N + injection region and a first floating P + injection region are arranged in the first P well, wherein the first P + injection region is positioned on the left side of the first P well, the first N + injection region is positioned on the right side of the first P + injection region and is attached together, and the first floating P + injection region is positioned on the right side of the first N + injection region;
a second P + injection region, a second N + injection region and a second floating P + injection region are arranged in the second P well, wherein the second P + injection region is positioned on the right side of the second P well, the second N + injection region is positioned on the left side of the second P + injection region and is attached together, and the second floating P + injection region is positioned on the left side of the second N + injection region;
an N-type well is arranged between the first P-type well and the second P-type well, a middle N + injection region is arranged in the middle of the N-type well, and meanwhile, a first P-type shallow well PB and a second P-type shallow well PB are respectively arranged in the middle of the first P-type well, the N-type well and the second P-type well in a crossing mode;
a first high-voltage N well and a second high-voltage N well are respectively arranged on the left side and the right side above the N-type buried layer;
the first P + injection region and the first N + injection region are connected together and used as an anode of the device, and the second P + injection region and the second N + injection region are connected together and used as a cathode of the device.
A first field oxide isolation region is arranged between the left side of the first P + injection region and the left side edge of the P-type substrate, the right side of the first P + injection region is connected with the left side of the first N + injection region, and a second field oxide isolation region is arranged between the right side of the first N + injection region and the left side of the first floating P + injection region; the left side of the second P + injection region is connected with the right side of the second N + injection region, and a fifth field oxide isolation region is arranged between the left side of the second N + injection region and the right side of the second floating P + injection region; a third field oxide isolation region is arranged on the right side of the first floating P + injection region and the left side of the first P-type shallow well PB; a fourth field oxide isolation region is arranged on the left side of the second floating P + injection region and the right side of the second P-type shallow well PB; and a sixth field oxide isolation region is arranged between the right side of the second P + injection region and the right side edge of the P-type substrate.
The left part of the first field oxide isolation region is positioned on the surface of the P-type substrate, and the right part of the first field oxide isolation region is positioned on the surface of the first P well; the left part of the sixth field oxygen isolation region is positioned on the surface of the second P well, and the right part of the sixth field oxygen isolation region is positioned on the surface of the P-type substrate; the second field oxide isolation region and the third field oxide isolation region are located on the surface of the first P well, and the fourth field oxide isolation region and the fifth field oxide isolation region are located on the surface of the second P well.
Wherein, when the positive pole of device, when the negative pole of device connects the low potential, first N + injection region first P trap, the N type trap has constituted vertical NPN type triode, first P trap N type trap the second P trap constitutes horizontal PNP type triode structure, second N + injection region second P trap the N type trap has constituted vertical NPN type triode, first P trap the N type buried layer the second P trap constitutes horizontal PNP type triode.
When the high-voltage ESD pulse reaches the anode of the device, the cathode of the device is grounded, and ESD current flows into a forward biased diode formed by the first P well, the first P-type shallow well PB and the middle N + injection region along the P + injection region.
The embodiment of the invention also provides a manufacturing method of the bidirectional controllable silicon electrostatic protection device with low trigger and high maintenance voltage, which comprises the following steps:
the method comprises the following steps: forming an N-type buried layer in a P-type substrate;
step two: generating an N-type trap in the middle above the N-type buried layer;
step three: sequentially generating a first field oxide isolation region, a second field oxide isolation region, a third field oxide isolation region, a fourth field oxide isolation region, a fifth field oxide isolation region and a sixth field oxide isolation region from left to right in the P-type substrate;
step four: respectively generating a first high-voltage N well, a second high-voltage N well, a first P well and a second P well on two sides above the N-type buried layer;
step five: generating a first P-type shallow well and a second P-type shallow well on two sides of the N-type well;
step six: sequentially forming a first P + injection region, a first N + injection region, a first floating P + injection region and a first P-type shallow well PB from left to right in the first P well, sequentially forming a second P-type shallow well PB, a second floating P + injection region, a second N + injection region and a second P + injection region in the second P well from left to right, and simultaneously forming an N + injection region between the first P-type shallow well and the second P-type shallow well; the left side of the first field oxide isolation region is in contact with the edge of the left side of the P-type substrate, the right side of the first field oxide isolation region is in contact with the left side of the first P + injection region, the right side of the first P + injection region is connected with the left side of the first N + injection region, the right side of the first N + injection region is in contact with the left side of the second field oxide isolation region, and the right side of the second field oxide isolation region is in contact with the left side of the first floating P + injection region; the right side of the second P-type shallow well PB is in contact with the left side of the third field oxygen isolation region, the right side of the third field oxygen isolation region is in contact with the left side of the second floating P + injection region, the right side of the second floating P + injection region is in contact with the fifth field oxygen isolation region, the right side of the fifth field oxygen isolation region is in contact with the left side of the second N + injection region, the right side of the second N + injection region is in contact with the left side of the second P + injection region, the right side of the second P + injection region is in contact with the left side of the sixth field oxygen isolation region, and the right side of the sixth field oxygen isolation region is in contact with the edge of the right side of the P-type substrate;
step seven: annealing the first P + injection region, the first N + injection region, the first floating P + injection region, the N + injection region in the N-type well, the second floating P + injection region, the second N + injection region and the second P + injection region to eliminate the migration of impurities in the injection regions;
step eight: the first P + injection region and the first N + injection region are connected together and serve as an anode of the device, and the second N + injection region and the second P + injection region are connected together and serve as a cathode of the device.
Wherein, still include before the said method:
growing a silicon dioxide film on the P-type substrate, and then depositing a silicon nitride film; spin-coating a photoresist layer on the wafer, and adding a mask plate to expose and develop the wafer to form the shallow isolation trench; and etching the silicon dioxide, the silicon nitride and the isolation shallow groove, removing the photoresist layer, depositing a layer of silicon dioxide, and then performing chemical mechanical polishing until the silicon nitride layer is removed.
The embodiment of the invention provides a bidirectional thyristor electrostatic protection device with low trigger and high maintenance voltage and a manufacturing method thereof, and the bidirectional thyristor electrostatic protection device has the following beneficial effects:
1. the invention can realize the purposes of reducing the trigger voltage and improving the maintaining voltage by changing the internal structure levels of the device under the condition of not changing the layout area, the reverse PN junction breakdown voltage formed by the first P-type shallow well PB, the N + injection region in the N well TB and the second P-type shallow well PB is smaller, the trigger voltage of the device can be effectively reduced by the structure, the base region concentration of a parasitic triode of a silicon controlled rectifier path of the device can be adjusted by the first floating P + injection region and the second floating P + injection region, and the maintaining voltage of the device is further improved.
2. The size S6 of N + injection in the N-type trap is adjustable, when S6 is reduced, the breakdown surface of the electrostatic protection device can be changed into the N-type trap and the P-type shallow trap PB, but the trigger voltage is influenced by the concentration of the N + injection region and can be increased but is not obvious, so that the trigger voltage of the electrostatic protection device can be increased along with the reduction of the size S6.
3. The sizes S3 of the first P + injection region and the second P + injection region in the first P well and the second P well are adjustable, when the size S3 is increased, the concentration of the first P well and the concentration of the second P well can be influenced by the P + injection region, namely the concentration of the NPN base region of the parasitic triode is increased to influence the current gain of the triode, and finally the maintaining voltage of the device is increased, so that the maintaining voltage of the device is increased along with the increase of the size S3.
Drawings
FIG. 1 is a cross-sectional view of a conventional bidirectional SCR electrostatic protection device;
FIG. 2 is an equivalent circuit diagram of a conventional bidirectional SCR ESD protection device;
FIG. 3 is a cross-sectional view of a low trigger high holding voltage triac ESD protection device in accordance with an embodiment of the present invention;
fig. 4 is an equivalent circuit diagram of a low trigger high holding voltage triac esd protection device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
As shown in fig. 3, a low-trigger high-sustain-voltage triac electrostatic discharge protection device includes a P-type substrate 101; an N-type buried layer 201 is arranged in the substrate; an N-type trap 301 is arranged in the middle above the N-type buried layer 201; a first P well 401 is arranged on the left side of the N-type buried layer 201, and a second P well 402 is arranged on the right side of the N-type buried layer 201; a first P + injection region 701, a first N + injection region 702 and a first floating P + injection region 703 are arranged in the first P well 401, wherein the first P + injection region 701 is located on the left side of the first P well 401, the first N + injection region 702 is located on the right side of the first P + injection region 701 and is attached together, and the first floating P + injection region 703 is located on the right side of the first N + injection region 702; a second P + injection region 707, a second N + injection region 706 and a second floating P + injection region 705 are arranged in the second P well 402, wherein the second P + injection region 707 is located on the right side of the second P well 402, the second N + injection region 706 is located on the left side of the second P + injection region 707 and is attached together, and the second floating P + injection region 705 is located on the left side of the second N + injection region 706; an N-type well 301 is arranged between the first P well 401 and the second P well 402, an N + injection region 704 is arranged in the middle of the N-type well 301, and meanwhile, a first P-type shallow well PB501 and a second P-type shallow well PB502 are respectively arranged in the middle of the first P well 401, the N-type well 301 and the second P well 402 in a crossing manner; a first high-voltage N well 601 and a second high-voltage N well 602 are respectively arranged on the leftmost side and the rightmost side above the N-type buried layer 201;
the first P + implantation region 701 and the first N + implantation region 702 are connected together and serve as an anode of the device, and the second P + implantation region 707 and the second N + implantation region 706 are connected together and serve as a cathode of the device.
A first field oxygen isolation region 801 is arranged between the left side of the first P + injection region 701 and the left side edge of the P-type substrate 101 and the left side edge of the first high-voltage N well 601, the right side of the first P + injection region 7001 is connected with the left side of the first N + injection region 702, and a second field oxygen isolation region 802 is arranged between the right side of the first N + injection region 702 and the left side of the first floating P + injection region 703; the left side of the second P + implantation region 707 is connected to the right side of the second N + implantation region 706 on the right side, and a fifth field oxide isolation region 805 is arranged on the left side of the second N + implantation region 706 and the right side of the second floating P + implantation region 705; a third field oxide isolation region 803 is arranged on the right side of the first floating P + implantation region 703 and the left side of the first P-type shallow well PB 501; a fourth field oxide isolation region 804 is arranged on the left side of the second floating P + injection region 705 and the right side of the second P-type shallow well PB 502; a sixth field oxide isolation region 806 is arranged between the right side of the second P + injection region 707 and the right side edges of the P-type substrate 101 and the second high-voltage N-well 602;
the left part of the first field oxide isolation region 801 is positioned on the surface of the first high-voltage N well 601, and the right part of the first field oxide isolation region 801 is positioned on the surface of the first P well 401; the left part of the sixth field oxide isolation region 806 is located on the surface of the second P well 402, and the right part of the sixth field oxide isolation region 806 is located on the surface of the second high voltage N well 602; the second field oxide isolation region 802 and the third field oxide isolation region 803 are located on the surface of the first P-well 401, and the fourth field oxide isolation region 804 and the fifth field oxide isolation region 805 are located on the surface of the second P-well 402.
As shown in fig. 4, when the high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the first N + injection region 702, the first P well 401, and the N-type well 301 form a vertical NPN type transistor, the first P well 401, the N-type well 301, and the second P well 402 form a lateral PNP type triode structure, and the second N + injection region 706, the second P well 402, and the N-type deep well 301 form a vertical NPN type triode. The longitudinal parasitic NPN transistor in the first P well 401 and the parasitic longitudinal NPN transistor in the second P well 402 may be combined in pairs to form a bidirectional SCR structure with the lateral PNP transistor.
When the ESD high voltage pulse reaches the anode of the device, the first P + injection region 701 and the first N + injection region 702 are at a high potential, the second N + injection region 706 and the second P + injection region 707 at the other end are at a low potential cathode, the N + injection region 704 and the second P-type shallow well 502 in the N-type well 301 are reversely biased, when the pulse voltage is higher than the avalanche breakdown voltage of the reverse biased PN junction formed by the N + injection region 704 and the second P-type shallow well 502, a large amount of avalanche current is generated inside the device, the avalanche current flows through the parasitic resistance of the second P-well 402 to the cathode, as can be seen from the equivalent circuit diagram of fig. 4, when the voltage drop generated by the avalanche current on the parasitic resistance of the second P-well 402 is large enough, the parasitic triode T3 is turned on, the base of the parasitic triode T2 is provided with a current, both form a positive feedback loop, and the forward SCR structure is turned on to release static electricity. Similarly, when a positive ESD pulse occurs at the cathode, avalanche breakdown occurs at the reverse biased PN junction formed by the N + injection region 704 and the second P-type shallow well 502, and an avalanche current flows through the parasitic resistor of the first P-well 401 and flows into the anode, as can be seen from the equivalent circuit diagram of fig. 4, when a voltage drop generated by the avalanche current on the parasitic resistor of the first P-well 401 is large enough, the parasitic triode T1 is turned on, and the parasitic triode T1 provides a current for the base of the parasitic triode T2 after being turned on, so that the parasitic triode T1 and the parasitic triode T2 form a positive feedback loop, and the reverse SCR structure is turned on to discharge static electricity.
Compared with the traditional bidirectional silicon controlled rectifier electrostatic protection device, the device changes the structure of an avalanche breakdown surface of the traditional silicon controlled rectifier, the reverse bias PN junction formed by the N + injection region 704, the first P-type shallow well 501 and the second P-type shallow well 502 enables the device to have lower trigger voltage, and meanwhile, the floating P + injection regions in the first P well 401 and the second P well 402 can improve the base region concentration of a longitudinal parasitic triode PNP, so that the maintaining voltage of the device is improved.
The device can adjust the trigger voltage of the device by controlling the size of S6 according to the requirements of an ESD design window under different application scenes, the size S6 of N + injection in the N-type trap can be adjusted, when S6 is reduced, the breakdown surface of the electrostatic protection device can be changed and changed into the N-type trap and the P-type shallow trap PB, but the trigger voltage can rise but is not obvious under the influence of the concentration of the N + injection region, and therefore the trigger voltage of the electrostatic protection device can be increased along with the reduction of the size S6.
Similarly, the sizes S3 of the first P + injection region and the second P + injection region in the first P well and the second P well are adjustable, and when S3 is increased, the P + injection region affects the concentrations of the first P well and the second P well, that is, the base region concentration of the parasitic triode NPN is increased to affect the current gain of the triode, and finally the sustain voltage of the device is increased, so that the sustain voltage of the electrostatic protection device is increased along with the increase of the size S3.
The embodiment of the invention also provides a manufacturing method of the bidirectional controllable silicon electrostatic protection device with low trigger and high maintenance voltage, which comprises the following steps:
the method comprises the following steps: growing a silicon dioxide film on a P-type substrate 101, and then depositing a silicon nitride film; spin-coating a photoresist layer on a wafer, and adding a mask plate to expose and develop the wafer to form an isolation shallow slot; etching silicon dioxide, silicon nitride and isolation shallow slot, removing photoresist layer, depositing a layer of silicon dioxide, and chemical mechanical polishing until the silicon nitride layer is removed
Step two: determining the size S6 of the N + implantation region 704 and the sizes S3 of the first floating P + implantation region 703 and the second floating P + implantation region 705 according to the specific protection window;
step three: a first field oxide isolation region 801, a second field oxide isolation region 802, a third field oxide isolation region 803, a fourth field oxide isolation region 804, a fifth field oxide isolation region 805 and a sixth field oxide isolation region 806 are sequentially formed in the P-type substrate from left to right;
step four: forming an N-type buried layer 201 in a P-type substrate 101;
step five: an N-type well 301 is generated in the middle above an N-type buried layer 201, and a first high-voltage N-well 601, a first P-well 401, a second P-well 402 and a second high-voltage N-well 602 are generated on two sides;
step six: generating a first P-type shallow well 501 and a second P-type shallow well 502 on two sides of the N-type well 301;
step seven: a first P + injection region 701, a first N + injection region 702, a first floating P + injection region 703 and a first P-type shallow well PB501 are sequentially formed in the first P well 401 from left to right, a second P-type shallow well PB502, a second floating P + injection region 705, a second N + injection region 706 and a second P + injection region 707 are sequentially formed in the second P well 402 from left to right, and an N + injection region 704 is formed between the first P-type shallow well 501 and the second P-type shallow well 502; the left side of the first field oxide isolation region 801 is in contact with the edge of the left side of the P-type substrate 101, the right side of the first field oxide isolation region 801 is in contact with the left side of the first P + injection region 701, the right side of the first P + injection region 701 is connected with the left side of the first N + injection region 702, the right side of the first N + injection region 702 is in contact with the left side of the second field oxide isolation region 802, and the right side of the second field oxide isolation region 802 is in contact with the left side of the first floating P + injection region 703; the right side of the second P-type shallow well PB502 contacts with the left side of the third field oxygen isolation region 803, the right side of the third field oxygen isolation region 803 contacts with the left side of the second floating P + injection region 705, the right side of the second floating P + injection region 705 contacts with the fifth field oxygen isolation region 805, the right side of the fifth field oxygen isolation region 805 contacts with the left side of the second N + injection region 706, the right side of the second N + injection region 706 contacts with the left side of the second P + injection region 707, the right side of the second P + injection region 707 contacts with the left side of the sixth field oxygen isolation region 806, and the right side of the sixth field oxygen isolation region 806 contacts with the edge of the right side of the P-type substrate 101;
step eight: annealing the first P + injection region 701, the first N + injection region 702, the first floating P + injection region 703, the N + injection region 704 in the N-type well, the second floating P + injection region 705, the second N + injection region 706 and the second P + injection region 707 to eliminate the migration of impurities in the injection regions;
step nine: the first P + implant region 701 and the first N + implant region 702 are coupled together and serve as the anode of the device, and the second N + implant region 706 and the second P + implant region 707 are coupled together and serve as the cathode of the device.
Optionally, the method further comprises:
growing a silicon dioxide film on the P-type substrate, and then depositing a silicon nitride film; spin-coating a photoresist layer on a wafer, and adding a mask plate to expose and develop the wafer to form an isolation shallow slot; and etching the silicon dioxide, the silicon nitride and the isolation shallow groove, removing the photoresist layer, depositing a layer of silicon dioxide, and then performing chemical mechanical polishing until the silicon nitride layer is removed.
The manufacturing method of the bidirectional controllable silicon electrostatic protection device with low trigger and high maintenance voltage has simple process and convenient operation. The manufactured bidirectional thyristor electrostatic protection device structure has a reverse avalanche breakdown surface with lower breakdown voltage, and can effectively reduce the trigger voltage of the device. Meanwhile, the addition of the floating P + injection can effectively improve the holding voltage of the device. The device can adjust the trigger voltage of the device by controlling the size of the N + injection region of the breakdown surface according to the requirements of an ESD design window under different application scenes, and adjust the maintenance voltage of the device by controlling the size of the floating P + injection region. The device can be applied to an ESD protection design, and effectively protects an internal chip from the risk of latch-up. The device of the embodiment of the invention adopts a BCDMOS process with the thickness of 0.25 mu m.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.
Claims (7)
1. A bidirectional controllable silicon electrostatic protection device with low trigger and high maintaining voltage is characterized by comprising a P-type substrate; an N-type buried layer is arranged in the P-type substrate; an N-type trap is arranged in the middle above the N-type buried layer; a first P well is arranged on the left side of the N-type buried layer, and a second P well is arranged on the right side of the N-type buried layer; a first P + injection region, a first N + injection region and a first floating P + injection region are arranged in the first P well, wherein the first P + injection region is positioned on the left side of the first P well, the first N + injection region is positioned on the right side of the first P + injection region and is attached together, and the first floating P + injection region is positioned on the right side of the first N + injection region;
a second P + injection region, a second N + injection region and a second floating P + injection region are arranged in the second P well, wherein the second P + injection region is positioned on the right side of the second P well, the second N + injection region is positioned on the left side of the second P + injection region and is attached together, and the second floating P + injection region is positioned on the left side of the second N + injection region;
an N-type well is arranged between the first P-type well and the second P-type well, a middle N + injection region is arranged in the middle of the N-type well, and meanwhile, a first P-type shallow well PB and a second P-type shallow well PB are respectively arranged in the middle of the first P-type well, the N-type well and the second P-type well in a crossing mode;
a first high-voltage N well and a second high-voltage N well are respectively arranged on the left side and the right side above the N-type buried layer;
the first P + injection region and the first N + injection region are connected together and used as an anode of the device, and the second P + injection region and the second N + injection region are connected together and used as a cathode of the device.
2. The device of claim 1, wherein a first field oxide isolation region is disposed between a left side of the first P + implant region and a left side edge of the P-type substrate, a right side of the first P + implant region is connected to a left side of the first N + implant region, and a second field oxide isolation region is disposed between a right side of the first N + implant region and a left side of the first floating P + implant region; the left side of the second P + injection region is connected with the right side of the second N + injection region, and a fifth field oxide isolation region is arranged between the left side of the second N + injection region and the right side of the second floating P + injection region; a third field oxide isolation region is arranged on the right side of the first floating P + injection region and the left side of the first P-type shallow well PB; a fourth field oxide isolation region is arranged on the left side of the second floating P + injection region and the right side of the second P-type shallow well PB; and a sixth field oxide isolation region is arranged between the right side of the second P + injection region and the right side edge of the P-type substrate.
3. The low trigger high sustain voltage triac electrostatic discharge protection device of claim 2 wherein said first field oxide isolation region is located on the surface of said P-type substrate at the left and said first field oxide isolation region is located on the surface of said first P-well at the right; the left part of the sixth field oxygen isolation region is positioned on the surface of the second P well, and the right part of the sixth field oxygen isolation region is positioned on the surface of the P-type substrate; the second field oxide isolation region and the third field oxide isolation region are located on the surface of the first P well, and the fourth field oxide isolation region and the fifth field oxide isolation region are located on the surface of the second P well.
4. The device of claim 2, wherein when the high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the first N + injection region, the first P-well, and the N-well form a vertical NPN transistor, the first P-well, the N-well, and the second P-well form a lateral PNP transistor structure, the second N + injection region, the second P-well, and the N-well form a vertical NPN transistor, and the first P-well, the N-buried layer, and the second P-well form a lateral PNP transistor.
5. The low trigger high sustain voltage triac electrostatic protection device of claim 1 wherein when a high voltage ESD pulse reaches the anode of the device, the device cathode is at ground potential and ESD current flows along said P + implant into said forward biased diode formed by said first P-well, said first P-type shallow well PB and said middle N + implant.
6. A manufacturing method of a bidirectional triode thyristor electrostatic discharge protection device with low triggering and high maintaining voltage is characterized by comprising the following steps:
the method comprises the following steps: forming an N-type buried layer in a P-type substrate;
step two: generating an N-type trap in the middle above the N-type buried layer;
step three: sequentially generating a first field oxide isolation region, a second field oxide isolation region, a third field oxide isolation region, a fourth field oxide isolation region, a fifth field oxide isolation region and a sixth field oxide isolation region from left to right in the P-type substrate;
step four: respectively generating a first high-voltage N well, a second high-voltage N well, a first P well and a second P well on two sides above the N-type buried layer;
step five: generating a first P-type shallow well and a second P-type shallow well on two sides of the N-type well;
step six: sequentially forming a first P + injection region, a first N + injection region, a first floating P + injection region and a first P-type shallow well PB from left to right in the first P well, sequentially forming a second P-type shallow well PB, a second floating P + injection region, a second N + injection region and a second P + injection region in the second P well from left to right, and simultaneously forming an N + injection region between the first P-type shallow well and the second P-type shallow well; the left side of the first field oxide isolation region is in contact with the edge of the left side of the P-type substrate, the right side of the first field oxide isolation region is in contact with the left side of the first P + injection region, the right side of the first P + injection region is connected with the left side of the first N + injection region, the right side of the first N + injection region is in contact with the left side of the second field oxide isolation region, and the right side of the second field oxide isolation region is in contact with the left side of the first floating P + injection region; the right side of the second P-type shallow well PB is in contact with the left side of the third field oxide isolation region, the right side of the third field oxide isolation region is in contact with the left side of the second floating P + injection region, the right side of the second floating P + injection region is in contact with the fifth field oxide isolation region, the right side of the fifth field oxide isolation region is in contact with the left side of the second N + injection region, the right side of the second N + injection region is in contact with the left side of the second P + injection region, the right side of the second P + injection region is in contact with the left side of the sixth field oxide isolation region, and the right side of the sixth field oxide isolation region is in contact with the edge of the right side of the P-type substrate;
step seven: annealing the first P + injection region, the first N + injection region, the first floating P + injection region, the N + injection region in the N-type well, the second floating P + injection region, the second N + injection region and the second P + injection region to eliminate the migration of impurities in the injection regions;
step eight: the first P + injection region and the first N + injection region are connected together and serve as an anode of the device, and the second N + injection region and the second P + injection region are connected together and serve as a cathode of the device.
7. The method of claim 6, further comprising the steps of:
growing a silicon dioxide film on the P-type substrate, and then depositing a silicon nitride film; spin-coating a photoresist layer on the wafer, and adding a mask plate to expose and develop the wafer to form the shallow isolation trench; and etching the silicon dioxide, the silicon nitride and the isolation shallow groove, removing the photoresist layer, depositing a layer of silicon dioxide, and then performing chemical mechanical polishing until the silicon nitride layer is removed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110774825.9A CN115602677A (en) | 2021-07-08 | 2021-07-08 | Low-trigger high-holding-voltage bidirectional silicon controlled rectifier electrostatic protection device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110774825.9A CN115602677A (en) | 2021-07-08 | 2021-07-08 | Low-trigger high-holding-voltage bidirectional silicon controlled rectifier electrostatic protection device and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115602677A true CN115602677A (en) | 2023-01-13 |
Family
ID=84840990
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110774825.9A Pending CN115602677A (en) | 2021-07-08 | 2021-07-08 | Low-trigger high-holding-voltage bidirectional silicon controlled rectifier electrostatic protection device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115602677A (en) |
-
2021
- 2021-07-08 CN CN202110774825.9A patent/CN115602677A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9691753B2 (en) | Zener triggered silicon controlled rectifier with small silicon area | |
| CN108520875B (en) | High-maintenance voltage NPNPN type bidirectional silicon controlled rectifier electrostatic protection device | |
| US20030075726A1 (en) | Method of forming a substrate-triggered scr device in cmos technology | |
| US8390096B2 (en) | Adjustable holding voltage ESD protection device | |
| US9613946B2 (en) | Low voltage triggered silicon controlled rectifier with high holding voltage and small silicon area | |
| CN110491875B (en) | Bidirectional thyristor electrostatic protection device | |
| US8598625B2 (en) | ESD protection device with tunable design windows | |
| US8829565B1 (en) | High voltage electrostatic discharge protection device | |
| CN214848632U (en) | Bidirectional thyristor electrostatic protection device with low trigger and high holding voltage | |
| CN111799258B (en) | Interdigital asymmetric bidirectional silicon controlled electrostatic discharge device and manufacturing method thereof | |
| CN110289257B (en) | Bidirectional enhanced gate-controlled silicon controlled electrostatic protection device and manufacturing method thereof | |
| KR20090098237A (en) | Esd protection device having a stack type scr with high holding voltage | |
| CN215815877U (en) | High-maintenance high-failure bidirectional thyristor electrostatic protection device | |
| CN214848631U (en) | Low-voltage grid unidirectional silicon controlled electrostatic protection device | |
| TWI756092B (en) | Silicon-controlled rectifier | |
| CN115602677A (en) | Low-trigger high-holding-voltage bidirectional silicon controlled rectifier electrostatic protection device and manufacturing method thereof | |
| CN211265471U (en) | Bidirectional thyristor electrostatic protection device | |
| US11222886B2 (en) | ESD protection device with low trigger voltage | |
| CN115513201B (en) | High-maintenance low-resistance uniform-conduction bidirectional silicon controlled electrostatic protection device and manufacturing method thereof | |
| CN115513201A (en) | High-maintenance low-resistance uniform-conduction bidirectional silicon controlled electrostatic protection device and manufacturing method thereof | |
| CN110867440A (en) | Asymmetric bidirectional thyristor electrostatic protection device and manufacturing method thereof | |
| CN110211956B (en) | Grid enhanced type light-operated silicon controlled electrostatic discharge device structure and manufacturing method thereof | |
| CN211858654U (en) | High-protection-level unidirectional silicon controlled rectifier electrostatic protection device | |
| US11837600B2 (en) | Electrostatic discharge protection apparatus and its operating method | |
| CN116314308B (en) | Lateral insulated gate bipolar transistor and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |