CN111341844A - Symmetrical bidirectional silicon controlled rectifier electrostatic protection device with narrow design window and manufacturing method thereof - Google Patents
Symmetrical bidirectional silicon controlled rectifier electrostatic protection device with narrow design window and manufacturing method thereof Download PDFInfo
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- 230000002457 bidirectional effect Effects 0.000 title claims abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 15
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 15
- 239000010703 silicon Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 238000002347 injection Methods 0.000 claims abstract description 379
- 239000007924 injection Substances 0.000 claims abstract description 379
- 239000002184 metal Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000002955 isolation Methods 0.000 claims description 131
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 43
- 229910052760 oxygen Inorganic materials 0.000 claims description 43
- 239000001301 oxygen Substances 0.000 claims description 43
- 238000002513 implantation Methods 0.000 claims description 32
- 239000007943 implant Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 13
- 238000004088 simulation Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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Abstract
The embodiment of the invention provides a symmetrical bidirectional controllable silicon electrostatic protection device with a narrow design window and a manufacturing method thereof, wherein the symmetrical bidirectional controllable silicon electrostatic protection device comprises the following steps: the device comprises a P-type substrate, a P-type epitaxial layer, a first P well, a second P well, a third P well, a fourth P well, a first N-type deep well, a second N-type deep well, a third N-type deep well, a first P + injection region, a second P + injection region, a third P + injection region, a fourth P + injection region, a fifth P + injection region and a sixth P + injection region, as well as an N + injection region I, a P + injection region II, a P + injection region III, a P + injection region IV, a P + injection region V and a P + injection region VI, wherein the third P + injection region is connected with the N + injection region I through metal; the fourth P + injection region is connected with the N + injection region VI through metal; the first P + injection region, the second P + injection region, the sixth P + injection region and the N + injection region II are connected together and used as a cathode of the device, and the fifth P + injection region and the N + injection region II are connected together and used as an anode of the device, so that a charge leakage path is increased, and the holding voltage is improved.
Description
Technical Field
The invention relates to the field of electrostatic protection, in particular to a symmetrical bidirectional controllable silicon electrostatic protection device with a narrow design window and a manufacturing method thereof.
Background
As semiconductor processes are further developed and the process is further reduced, the performance of the device is greatly improved, but the protection against ESD poses new challenges. The traditional silicon controlled device has high trigger voltage and is easy to exceed a design window, the latch-up phenomenon is easy to cause due to low maintaining voltage, and the traditional silicon controlled device is difficult to adapt to the design window requirement of a modern ESD protection device.
The traditional bidirectional controllable silicon electrostatic protection device is improved on the basis of the traditional unidirectional controllable silicon electrostatic protection device, and can be considered as the formation of the face-to-face serial connection of two traditional unidirectional controllable silicon, the forward and reverse working modes of the traditional bidirectional controllable silicon device are the same as the forward working mode of the traditional single controllable silicon, the section view of the traditional bidirectional controllable silicon electrostatic protection device is shown in figure 1, and the equivalent circuit diagram is shown in figure 2. When electrostatic voltage appears at the anode, a forward PN junction is formed between the third P well and the first N well, charges enter the first N well from the anode, a reverse PN junction is formed between the second P well and the first N well, when the electrostatic voltage is larger than the reverse PN junction between the second P well and the first N well, the PNP triode is conducted to form avalanche charges, and the electrostatic charges flow into the second P well from the first N well and then flow out from the cathode. As the charge flowing through the second P-well increases, a forward conduction voltage is formed between the second P-well and the N + injection region i, bc of the NPN transistor Q3 is conducted, and the NPN transistor Q3 is conducted. At this time, the transistors Q2 and Q3 are turned on, thereby forming a positive feedback loop. After the positive feedback loop is formed, even if there is no avalanche current, a charge bleed-off path can be formed due to conduction of the transistor. When the cathode of the traditional bidirectional triode thyristor electrostatic protection device generates electrostatic voltage, the working principle is basically the same as that of the positive direction, but the avalanche generating region is different. When electrostatic voltage appears at the cathode, avalanche breakdown occurs in a reverse PN junction between the first N well and the third P well, so that the PNP triode Q2 and the NPN triode Q1 are conducted, and a positive feedback electrostatic discharge path is formed.
The high trigger voltage of the conventional SCR structure easily exceeds the upper limit of the design window, and the low trigger voltage easily causes latch-up.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a symmetrical bidirectional thyristor electrostatic protection device with a narrow design window and a manufacturing method thereof, which increases a path for charge leakage and improves a holding voltage.
The embodiment of the invention provides a symmetrical bidirectional controllable silicon electrostatic protection device with a narrow design window, which comprises: the device comprises a P-type substrate, wherein a P-type epitaxial layer is arranged above the P-type substrate, a first P well, a first N-type deep well, a second P well, a second N-type deep well, a third P well, a third N-type deep well and a fourth P well are sequentially arranged in the P-type epitaxial layer from left to right, and an N-type buried layer is arranged at the bottom of the P-type epitaxial layer;
a first P + injection region is arranged in the first P well;
the bottom of the first N-type deep well is connected with the N-type buried layer part;
a second P + injection region, an N + injection region I and an N + injection region II are sequentially arranged in the second P well from left to right;
the bottom of the second N-type deep well is connected with the N-type buried layer, a first N well is arranged in the second N-type deep well, and a third P + injection region and a fourth P + injection region are arranged in the first N well from left to right;
an N + injection region III is arranged at the junction of the second P well and the first N well;
an N + injection region V, an N + injection region VI and a fifth P + injection region are sequentially arranged in the third P well from left to right;
an N + injection region IV is arranged at the junction of the first N well injection region and the third P well;
the bottom of the third N-type deep well is connected with the N-type buried layer part;
a sixth P + injection region is arranged in the fourth P well;
the third P + injection region is connected with the N + injection region I through metal; the fourth P + injection region is connected with the N + injection region VI through metal;
the first P + injection region, the second P + injection region, the sixth P + injection region and the N + injection region II are connected together and used as a cathode of the device, and the fifth P + injection region and the N + injection region V are connected together and used as an anode of the device.
Wherein a first field oxide isolation region is arranged between the first P + injection region and the second P + injection region, a second field oxide isolation region is arranged between the second P + injection region and the N + injection region I, a third field oxide isolation region is arranged between the N + injection region I and the N + injection region II, a fourth field oxide isolation region is arranged between the N + injection region II and the N + injection region III, a fifth field oxide isolation region is arranged between the N + injection region III and the third P + injection region, a sixth field oxide isolation region is arranged between the third P + injection region and the fourth P + injection region, a seventh field oxide isolation region is arranged between the fourth P + injection region and the N + injection region IV, an eighth field oxide isolation region is arranged between the N + injection region IV and the N + injection region V, and a ninth field oxide isolation region is arranged between the N + injection region V and the N + injection region VI, a tenth field oxygen isolation region is arranged between the N + injection region VI and the fifth P + injection region, and an eleventh field oxygen isolation region is arranged between the fifth P + injection region and the sixth P + injection region.
The left side of the first field oxide isolation region is positioned on the surface of a first P well, the middle of the first P well crosses over a first N-type deep well, and the right side of the first P well is positioned on the surface of a second P well; the second, third and fourth field oxygen isolation regions are positioned on the surface of the second P well; the fifth, sixth and seventh field oxygen isolation regions are positioned on the surface of the first N well; the eighth, ninth and tenth field oxygen isolation regions are positioned on the surface of the third P well; the left side of the eleventh field oxide isolation region is positioned on the surface of the third P well, the middle of the eleventh field oxide isolation region stretches across the third N-type deep well, and the right side of the eleventh field oxide isolation region is positioned on the surface of the fourth P well.
When a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected with a low potential, the fifth P + injection region and the N + injection region VI form a diode D1, the second P + injection region and the N + injection region I form a diode D2, the N + injection region V, the third P well and the second N-type deep well form a transverse PNP triode Q1, the fifth P + injection region, the second N-type deep well and the second P + injection region form a longitudinal NPN triode Q2, the second N-type deep well, the second P well and the N + injection region II form a longitudinal NPN triode Q3, the N + injection region III, the second P well and the N + injection region II form a transverse NPN triode Q4, and the N + injection region IV, the third P well and the N + injection region V form a transverse NPN triode Q5, the N + injection region VI, the third P well and the N + injection region V form a transverse NPN type triode Q6, the fourth P + injection region, the first N well and the third P + injection region form a transverse PNP type triode Q7, and the N + injection region I, the second P well and the N + injection region II form a transverse NPN type triode Q8.
And the doping concentration of the N + injection region III and the N + injection region IV is higher than that of the first N well.
The doping concentrations of the third P + injection region and the fourth P + injection region are higher than that of the second P well, and the doping concentrations of the N + injection region I and the N + injection region VI are higher than that of the first N well.
The embodiment of the invention also provides a manufacturing method of the symmetrical bidirectional triode thyristor electrostatic protection device based on the narrow design window, which comprises the following steps:
the method comprises the following steps: determining the doping concentrations of the N + injection region III and the N + injection region IV according to the magnitude of the trigger voltage;
step two: forming a P-type epitaxial layer above a P-type substrate;
step three: forming an N-type buried layer at the bottom of the P-type epitaxial layer;
step four: sequentially generating a first field oxygen isolation region, a second field oxygen isolation region, a third field oxygen isolation region, a fourth field oxygen isolation region, a fifth field oxygen isolation region, a sixth field oxygen isolation region, a seventh field oxygen isolation region, an eighth field oxygen isolation region, a ninth field oxygen isolation region, a tenth field oxygen isolation region and an eleventh field oxygen isolation region from left to right in the P-type epitaxial layer;
step five: sequentially forming a first P well, a second P well, a third P well and a fourth P well from left to right on the P-type epitaxial layer;
step six: forming a first N-type deep well between the first P well and the second P well, forming a second N-type deep well on the first N well, forming a third N-type deep well between the third P well and the fourth P well, and connecting the bottoms of the first N-type deep well, the second N-type deep well and the third N-type deep well with the N-type buried layer;
step seven: forming a first P + injection region in the first P well, forming a second P + injection region in the second P well, and forming a third P + injection region and a fourth P + injection region in the first N well from left to right; forming a fifth P + injection region in the third P well, and arranging a sixth P + injection region in the fourth P well;
step eight: forming an N + injection region III at the junction of the second P well and the first N well, and forming an N + injection region IV at the junction of the first N well injection region and the third P well;
step nine: forming an N + injection region I and an N + injection region II in the second P well, forming an N + injection region V and an N + injection region VI in the third P well, wherein the left side of the first field oxide isolation region is in contact with the edge of the right side of the first P + injection region, the right side of the first field oxide isolation region is in contact with the edge of the left side of the second P + injection region, the second field oxide isolation region is between the second P + injection region and the N + injection region I, the third field oxide isolation region is between the N + injection region I and the N + injection region II, the fourth field oxide isolation region is between the N + injection region II and the N + injection region III, the fifth field oxide isolation region is between the N + injection region III and the third P + injection region, the sixth field oxide isolation region is between the third P + injection region and the fourth P + injection region, the seventh field oxide isolation region is between the fourth P + injection region and the N + injection region IV, and the eighth field oxide isolation region is between the N + injection region IV and the N + injection region V, the ninth field oxygen isolation region is arranged between the N + injection region V and the N + injection region VI, the tenth field oxygen isolation region is arranged between the N + injection region VI and the fifth P + injection region, the left side of the eleventh field oxygen isolation region is contacted with the edge of the right side of the fifth P + injection region, and the right side of the eleventh field oxygen isolation region is contacted with the edge of the left side of the sixth P + injection region;
step ten: annealing the first P + injection region, the second P + injection region, the third P + injection region, the fourth P + injection region, the fifth P + injection region, the sixth P + injection region, the N + injection region I, the N + injection region II, the N + injection region III and the N + injection region VI;
step eleven: the third P + injection region is connected with the N + injection region I through metal, the fourth P + injection region is connected with the N + injection region VI through metal, the first P + injection region, the second P + injection region, the sixth P + injection region and the N + injection region II are connected together and serve as the cathode of the device, and the fifth P + injection region and the N + injection region II are connected together and serve as the anode of the device.
Has the advantages that:
1) the different doping concentrations of the N + injection regions III and IV can be adjusted according to the size of the trigger voltage, and if the doping concentration concentrations of the N + injection regions III and IV are higher, the trigger voltage is lower; the lower the doping concentration of the N + implantation regions III and IV is, the higher the trigger voltage is.
2) The doping concentration of the third P + injection area, the fourth P + injection area and the N + injection area I and VI is higher than that of the first N well, and the metal connecting line between the N + injection area VI and the fourth P + injection area and the metal connecting line between the third P + injection area and the N + injection area I are added, so that a faster charge relief circuit can be formed on the surfaces of the third P well, the first N well and the second P well.
Drawings
FIG. 1 is a cross-sectional view of a conventional triac electrostatic protection device;
FIG. 2 is an equivalent circuit diagram of a conventional triac electrostatic protection device;
FIG. 3 is a cross-sectional view of a narrow design window symmetrical triac ESD protection device in accordance with an embodiment of the present invention;
FIG. 4 is an equivalent circuit diagram of a narrow design window symmetrical triac ESD protection device in accordance with an embodiment of the present invention;
FIG. 5 is an I-V curve diagram of a conventional triac electrostatic protection device simulation;
FIG. 6 is a current density distribution diagram of a conventional bidirectional thyristor ESD protection device;
FIG. 7 is an I-V curve diagram of a narrow design window symmetrical triac ESD device simulation in accordance with an embodiment of the present invention;
fig. 8 is a diagram of a narrow design window current density distribution for a symmetrical triac esd protection device in accordance with an embodiment of the present invention.
Detailed Description
The invention is further described below with reference to the figures and examples.
As shown in fig. 3, a symmetrical triac electrostatic protection device with a narrow design window includes a P-type substrate 101; a P-type epitaxial layer 201 is arranged above the substrate; an N-type buried layer 301 is arranged at the bottom of the P-type epitaxial layer; a first P well 401, a first N-type deep well 402, a second P well 403, a second N-type deep well 404, a third P well 405, a third N-type deep well 406 and a fourth P well 407 are sequentially arranged in the P-type epitaxial layer from left to right; a first P + injection region 501 is arranged in the first P well; the bottom of the first N-type deep well 402 is connected with part of the N-type buried layer 301; a second P + injection region 502, an N + injection region I503 and an N + injection region II 504 are sequentially arranged in the second P well from left to right; the bottom of the second N-type deep well is connected with the N-type buried layer, and a first N well 505 is arranged in the second N-type deep well; a third P + injection region 507 and a fourth P + injection region 508 are arranged in the first N well from left to right; an N + injection region III 509 is arranged at the junction of the second P well and the first N well; an N + injection region V510, an N + injection region VI 511 and a fifth P + injection region 512 are sequentially arranged in the third P well from left to right; an N + injection region IV 509 is arranged at the junction of the first N well injection region and the third P well; the bottom of the third N-type deep well 406 is connected with part of the N-type buried layer 301; a sixth P + implantation region 513 is disposed in the fourth P well 407; the third P + injection region 512 is connected with the N + injection region I503 through metal; the fourth P + injection region 508 is connected with the N + injection region VI 511 by metal; the first, second and sixth P + implant regions 501, 502 and 513 and the N + implant region ii 504 are connected together and serve as the cathode of the device, and the fifth P + implant region 512 and the N + implant region v 510 are connected together and serve as the anode of the device.
A first field oxide isolation region 601 is arranged between the first P + injection region 501 and the second P + injection region 502, a second field oxide isolation region 602 is arranged between the second P + injection region 502 and the N + injection region I503, a third field oxide isolation region 603 is arranged between the N + injection regions I503 and II 504, a fourth field oxide isolation region 604 is arranged between the N + injection regions II 504 and III 506, a fifth field oxide isolation region 605 is arranged between the N + injection region III 506 and the third P + injection region 507, a sixth field oxide isolation region 606 is arranged between the third P + injection region 507 and the fourth P + injection region 508, a seventh field oxide isolation region 607 is arranged between the fourth P + injection region and the 508N + injection region IV isolation region 509, an eighth field oxide isolation region 608 is arranged between the N + injection regions IV 509 and V510, and a ninth field oxide isolation region 609 is arranged between the N + injection regions V510 and VI 511, a tenth field oxide isolation region 610 is arranged between the N + injection region VI 511 and the fifth P + injection region 512, and an eleventh field oxide isolation region 611 is arranged between the fifth P + injection region 512 and the sixth P + injection region 513. The left side of the first field oxide isolation region 601 is located on the surface of the first P well 401, the middle of the first field oxide isolation region crosses over the first N-type deep well 402, and the right side of the first field oxide isolation region is located on the surface 403 of the second P well; the second, third and fourth field oxygen isolation regions 602, 603 and 604 are located on the second P-well surface 403; the fifth, sixth and seventh field oxide isolation regions 605, 606 and 607 are located on the surface 505 of the first N well; the eighth, ninth, and tenth field oxide isolation regions 608, 609, 610 are located on the third P-well surface 405; the eleventh field oxide isolation region 611 is located on the left side of the third P-well 405, across the third N-type deep well 406 in the middle, and on the right side of the fourth P-well 407.
Fig. 4 is an equivalent circuit diagram of the present embodiment, when the high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to the low potential, the fifth P + injection region 512 and the N + injection region vi 511 form a diode D1, the second P + injection region 502 and the N + injection region i 503 form a diode D2, the N + injection region v 510, the third P well 405 and the second N well 404 form a lateral PNP transistor Q1, the fifth P + injection region 512, the second N well 404 and the second P + injection region i 502 form a vertical NPN transistor Q2, the second N well 404, the second P well 403 and the N + injection region ii 504 form a vertical NPN transistor Q3, the N + injection region iii 506, the second P well 403 and the N + injection region ii 504 form a lateral NPN transistor Q4, the N + injection region iv 509, the third P well 405 and the N + injection region vi 510 form a lateral NPN 5, and the N + injection region iv 511, the third P well 405 and the N + injection region vi 510 form a lateral NPN transistor Q5, The third P well 405 and the N + injection region v 510 form a lateral NPN transistor Q6, the fourth P + injection region 508, the first N well 505, and the third P + injection region 507 form a lateral PNP transistor Q7, and the N + injection region i 503, the second P well 403, and the N + injection region ii 504 form a lateral NPN transistor Q8.
When the high-voltage ESD pulse reaches the anode of the device, the cathode of the device is at the ground potential, the fifth P + injection region 512 and the N + injection region VI 511 are positively biased, D1 is conducted, the third P well 405 and the first N well 505 are positively biased, bc of Q5 is conducted, the third P well 405 and the first N well 505 are positively biased, cb of Q2 is conducted, the fourth P + injection region 508 and the first N well 505 are positively biased, cb of Q7 is conducted, and current is injected into the first N well. The first N well 505 and the second P well 403 are reverse biased, the N + implant region iii 506 and the second P well 403 are reverse biased, the first N well 505 and the third P + implant region 507 are reverse biased and the N + implant region i 503 and the first P well 403 are also reverse biased. As the forward voltage continues to increase, since the doping concentration of the N + implantation region iii 506 is higher than that of the first N well 505, if the pulse voltage is higher than the reverse bias voltage of the N + implantation region iii 506 and the second P well 403, breakdown will occur preferentially between the N + implantation region iii 506 and the second P well 403. When the forward voltage continues to increase, the voltage reaches the sum of the reverse biased PN junctions of the first N well 505 and the third P + injection region 507 and the reverse biased PN junctions of the N + injection region i 503 and the second P well 403, breakdown occurs between the first N well 505 and the third P + injection region 507 and between the N + injection region i 503 and the second P well 403, a large amount of avalanche current is generated inside the device, and the voltage across the parasitic resistor is increased, so that the vertical NPN transistor Q3, the lateral NPN transistor Q4, and the lateral NPN transistor Q8 are turned on.
When the forward electrostatic voltage arrives, after the charge flows from the third P-well 405 to the first N-well 505, there are two charge draining paths, i.e. path one: a charge draining path between the N + injection region iii 506 and the second P-well 403, path two: and the first N trap 505 and the third P + injection region 507 are connected to the charge discharge path of the N + injection region I503 and the first P trap 403 through metal wires. Two charge bleeder circuits compare in traditional bidirectional thyristor device, have increased a charge bleeder route, have played the effect of reposition of redundant personnel to traditional bidirectional thyristor device, have weakened the positive feedback effect of traditional bidirectional thyristor electrostatic protection device, consequently have higher charge discharge ability, littleer design window. When the diode D1 and the triodes Q2, Q3, Q4, Q7 and Q8 are in forward conduction, the diode works.
The doping concentration of the N + injection regions III 506 and IV 509 is higher than that of the first N well 505, and can be adjusted according to the magnitude of the trigger voltage, and if the doping concentration of the N + injection regions III 506 and IV 509 is higher, the trigger voltage is lower; the lower the doping concentration of the N + implant regions iii 506, iv 509, the higher the trigger voltage.
The doping concentration of the third and fourth P + injection regions 507, 508 is higher than that of the second P well 403, the doping concentration of the N + injection regions i 503, vi 510 is higher than that of the first N well 505, and a faster charge conduction circuit can be formed on the surfaces of the third P well 405, the first N well 505, and the second P well 403 due to the higher doping concentration and the metal connection between the N + injection region vi 509 and the fourth P + injection region 508 and the metal connection between the third P + injection region 507 and the N + injection region i 503.
The device can be adjusted according to the requirements of ESD design windows under different application scenes, wherein the doping concentration of the N + injection regions III 506 and IV 509 is higher than that of the first N well 505, and can be adjusted according to the magnitude of trigger voltage, and if the doping concentration of the N + injection regions III 506 and IV 509 is higher, the trigger voltage is lower; the lower the doping concentration of the N + implant regions iii 506, iv 509, the higher the trigger voltage.
The doping concentration of the third and fourth P + injection regions 507, 508 is higher than that of the second P well 403, the doping concentration of the N + injection regions i 503, vi 510 is higher than that of the first N well 505, and a faster charge conduction circuit can be formed on the surfaces of the third P well 405, the first N well 505, and the second P well 403 due to the higher doping concentration and the metal connection between the N + injection region vi 509 and the fourth P + injection region 508 and the metal connection between the third P + injection region 507 and the N + injection region i 503.
A manufacturing method of a symmetrical bidirectional triode thyristor electrostatic protection device with a narrow design window comprises the following steps:
the method comprises the following steps: determining the doping concentration of the N + injection regions III 506 and IV 509 according to the size of the trigger voltage;
step two: forming a P-type epitaxial layer 201 above a P-type substrate 101;
step three: forming an N-type buried layer 301 at the bottom of the P-type epitaxial layer 201;
step four: a first field oxide isolation region 601, a second field oxide isolation region 602, a third field oxide isolation region 603, a fourth field oxide isolation region 604, a fifth field oxide isolation region 605, a sixth field oxide isolation region 606, a seventh field oxide isolation region 607, an eighth field oxide isolation region 608, a ninth field oxide isolation region 609, a tenth field oxide isolation region 610 and an eleventh field oxide isolation region 611 are sequentially formed in the P-type substrate 101 from left to right;
step five: a first P well 401, a second P well 403, a third P well 405 and a fourth P well 407 are sequentially formed on the P-type epitaxial layer from left to right;
step six: a first N-type 4 deep well 402 is formed between the first P well 401 and the second P well 403, a second N-type deep well 404 is formed on the basis of the first N well 505, and a third N-type deep well 406 is formed between the third P well 405 and the fourth P well 407. The bottoms of the first, second and third N-type deep wells 402, 404 and 406 are connected with the N-type buried layer.
Step seven: forming a first P + implantation region 501 in the first P well 401 and a second P + implantation region 502 in the second P well 403; third and fourth P + implantation regions 507 and 508 are formed in the first N well 505 from left to right; forming a fifth P + implant region 512 within the third P-well 405; a sixth P + implantation region 513 is disposed in the fourth P well 407;
step eight: forming an N + injection region III 506 at the boundary of the second P well 403 and the first N well 505; forming an N + injection region IV 509 at the junction of the first N well injection region 505 and the third P well 405;
step nine: forming N + injection regions I503 and II 504 in the second P trap 403; forming N + injection regions V510 and VI 511 in the third P trap 405; a first field oxide isolation area 601 is arranged between the first P + injection area 501 and the second P + injection area 502, a second field oxide isolation area 602 is arranged between the second P + injection area 502 and the N + injection area I503, a third field oxide isolation area 603 is arranged between the N + injection areas I503 and II 504, a fourth field oxide isolation area 604 is arranged between the N + injection areas II 504 and III 506, a fifth field oxide isolation area 605 is arranged between the N + injection area III 506 and the third P + injection area 507, a sixth field oxide isolation area 606 is arranged between the third P + injection area 507 and the fourth P + injection area 508, a seventh field oxide isolation area 607 is arranged between the fourth P + injection area and the 508N + injection area IV isolation area 509, an eighth field oxide isolation area 608 is arranged between the N + injection areas IV, V509 and VI 510, a ninth field oxide isolation area 511 is arranged between the N + injection areas V510 and VI 511, and a tenth field oxide isolation area 512 is arranged between the N + injection area V510 and the fifth P + injection area VI 512, an eleventh field oxide isolation region 611 is disposed between the fifth P + implantation region 512 and the sixth P + implantation region 513. The left side of the first field oxide isolation region 601 is located on the surface of the first P well 401, the middle of the first P well crosses the first N-type deep well 402, and the right side of the first P well is located on the surface 403 of the second P well; the second, third and fourth field oxide isolation regions 602, 603 and 604 are positioned on the surface 403 of the second P well; the fifth, sixth and seventh field oxide isolation regions 605, 606 and 607 are positioned on the surface 505 of the first N well; the eighth, ninth and tenth oxygen isolation regions 608, 609 and 610 are positioned on the surface 405 of the third P well; the eleventh field oxide isolation region 611 is located on the surface of the third P-well 405 on the left side, across the third N-type deep well 406 in the middle, and on the fourth P-well surface 407 on the right side.
Step ten: annealing the first to sixth P + injection regions 501, 502, 507, 508, 512 and 513 and the N + injection regions I to VI 503, 504, 506, 509, 510 and 511 to eliminate the migration of impurities in the injection regions;
step eleven: connecting the third P + injection region 512 with the N + injection region I503 by metal; the fourth P + injection region 508 is connected with the N + injection region VI 511 by metal; the first, second and sixth P + implant regions 501, 502, 513 and the N + implant region ii 504 are connected together and serve as the cathode of the device, and the fifth P + implant region 512 and the N + implant region v 510 are connected together and serve as the anode of the device.
Fig. 5 is an I-V curve diagram of a simulation of a conventional triac electrostatic discharge protection device, which shows that the trigger voltage of the conventional triac electrostatic discharge protection device is 54V and the sustain voltage is 25V. Fig. 7 is an I-V curve diagram of the simulation of the embodiment of the present invention, which shows that the design window is significantly reduced when the trigger voltage is 25V and the sustain voltage is 20V in this embodiment compared with the conventional triac electrostatic protection device.
Fig. 6 is a current density distribution diagram of a conventional triac electrostatic protection device, and fig. 8 is a current density distribution diagram of an embodiment of the present invention. By comparison, the embodiment of the present invention has a wider charge draining area and more charge draining paths, and the correctness of the equivalent circuit diagram of the embodiment of fig. 4 is verified.
According to the symmetrical bidirectional thyristor electrostatic protection device with the narrow design window, the doping concentration of the N + injection regions III and IV is higher than that of the first N well, and can be adjusted according to the magnitude of trigger voltage, and if the doping concentration of the N + injection regions III and IV is higher, the trigger voltage is lower; the lower the doping concentration of the N + implantation regions III and IV is, the higher the trigger voltage is.
The doping concentration of the third P + injection region and the fourth P + injection region is higher than that of the second P well, the doping concentration of the N + injection regions I and VI is higher than that of the first N well, and due to the higher doping concentration, a metal connecting line between the N + injection region VI and the fourth P + injection region and a metal connecting line between the third P + injection region and the N + injection region I are added, so that a faster charge conduction circuit can be formed on the surfaces of the third P well, the first N well and the second P well. The device of the embodiment of the invention adopts a BCDMOS process with the thickness of 0.25 mu m.
Claims (7)
1. A symmetrical bidirectional controllable silicon electrostatic protection device with a narrow design window is characterized by comprising: the device comprises a P-type substrate, wherein a P-type epitaxial layer is arranged above the P-type substrate, a first P well, a first N-type deep well, a second P well, a second N-type deep well, a third P well, a third N-type deep well and a fourth P well are sequentially arranged in the P-type epitaxial layer from left to right, and an N-type buried layer is arranged at the bottom of the P-type epitaxial layer;
a first P + injection region is arranged in the first P well;
the bottom of the first N-type deep well is connected with the N-type buried layer part;
a second P + injection region, an N + injection region I and an N + injection region II are sequentially arranged in the second P well from left to right;
the bottom of the second N-type deep well is connected with the N-type buried layer, a first N well is arranged in the second N-type deep well, and a third P + injection region and a fourth P + injection region are arranged in the first N well from left to right;
an N + injection region III is arranged at the junction of the second P well and the first N well;
an N + injection region V, an N + injection region VI and a fifth P + injection region are sequentially arranged in the third P well from left to right;
an N + injection region IV is arranged at the junction of the first N well injection region and the third P well;
the bottom of the third N-type deep well is connected with the N-type buried layer part;
a sixth P + injection region is arranged in the fourth P well;
the third P + injection region is connected with the N + injection region I through metal; the fourth P + injection region is connected with the N + injection region VI through metal;
the first P + injection region, the second P + injection region, the sixth P + injection region and the N + injection region II are connected together and used as a cathode of the device, and the fifth P + injection region and the N + injection region V are connected together and used as an anode of the device.
2. The narrow design window symmetrical SCR ESD device as claimed in claim 1, wherein a first field oxide isolation region is located between the first P + implantation region and the second P + implantation region, a second field oxide isolation region is located between the second P + implantation region and the N + implantation region I, a third field oxide isolation region is located between the N + implantation region I and the N + implantation region II, a fourth field oxide isolation region is located between the N + implantation region II and the N + implantation region III, a fifth field oxide isolation region is located between the N + implantation region III and the third P + implantation region, a sixth field oxide isolation region is located between the third P + implantation region and the fourth P + implantation region, a seventh field oxide isolation region is located between the fourth P + implantation region and the N + implantation region IV, and an eighth field oxide isolation region is located between the N + implantation region IV and the N + implantation region V, a ninth field oxygen isolation region is arranged between the N + injection region V and the N + injection region VI, a tenth field oxygen isolation region is arranged between the N + injection region VI and the fifth P + injection region, and an eleventh field oxygen isolation region is arranged between the fifth P + injection region and the sixth P + injection region.
3. The narrow design window symmetrical triac electrostatic protection device of claim 2, wherein said first field oxide isolation region has a left side on the surface of a first P-well, a middle portion crossing over a first N-type deep well, and a right side on the surface of a second P-well; the second, third and fourth field oxygen isolation regions are positioned on the surface of the second P well; the fifth, sixth and seventh field oxygen isolation regions are positioned on the surface of the first N well; the eighth, ninth and tenth field oxygen isolation regions are positioned on the surface of the third P well; the left side of the eleventh field oxide isolation region is positioned on the surface of the third P well, the middle of the eleventh field oxide isolation region stretches across the third N-type deep well, and the right side of the eleventh field oxide isolation region is positioned on the surface of the fourth P well.
4. The narrow design window symmetrical triac electrostatic protection device of claim 2, wherein when the high voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to the low potential, said fifth P + injection region and said N + injection region vi constitute a diode D1, said second P + injection region and said N + injection region i constitute a diode D2, said N + injection region v, said third P-well and said second N-type deep well constitute a lateral PNP transistor Q1, said fifth P + injection region, said second N-type deep well and said second P + injection region constitute a vertical NPN transistor Q2, said second N-type deep well, said second P-well and said N + injection region ii constitute a vertical NPN transistor Q3, said N + injection region iii, said second P-well and said N + injection region ii constitute a lateral NPN transistor Q4, the N + injection region IV, the third P well and the N + injection region V form a transverse NPN type triode Q5, the N + injection region VI, the third P well and the N + injection region V form a transverse NPN type triode Q6, the fourth P + injection region, the first N well and the third P + injection region form a transverse PNP type triode Q7, and the N + injection region I, the second P well and the N + injection region II form a transverse NPN type triode Q8.
5. The narrow design window symmetrical triac electrostatic protection device of claim 4, wherein said N + implant region iii, said N + implant region iv have a higher doping concentration than said first N-well.
6. The narrow design window symmetrical triac electrostatic protection device of claim 4, wherein the doping concentration of said third P + implantation region and said fourth P + implantation region is higher than the doping concentration of said second P-well, and the doping concentration of said N + implantation region i and said N + implantation region vi is higher than the doping concentration of said first N-well.
7. A method for manufacturing a symmetrical bidirectional triode thyristor electrostatic discharge protection device based on the narrow design window of any one of claims 1 to 6, comprising the following steps:
the method comprises the following steps: determining the doping concentrations of the N + injection region III and the N + injection region IV according to the magnitude of the trigger voltage;
step two: forming a P-type epitaxial layer above a P-type substrate;
step three: forming an N-type buried layer at the bottom of the P-type epitaxial layer;
step four: sequentially generating a first field oxygen isolation region, a second field oxygen isolation region, a third field oxygen isolation region, a fourth field oxygen isolation region, a fifth field oxygen isolation region, a sixth field oxygen isolation region, a seventh field oxygen isolation region, an eighth field oxygen isolation region, a ninth field oxygen isolation region, a tenth field oxygen isolation region and an eleventh field oxygen isolation region from left to right in the P-type epitaxial layer;
step five: sequentially forming a first P well, a second P well, a third P well and a fourth P well from left to right on the P-type epitaxial layer;
step six: forming a first N-type deep well between the first P well and the second P well, forming a second N-type deep well on the first N well, forming a third N-type deep well between the third P well and the fourth P well, and connecting the bottoms of the first N-type deep well, the second N-type deep well and the third N-type deep well with the N-type buried layer;
step seven: forming a first P + injection region in the first P well, forming a second P + injection region in the second P well, and forming a third P + injection region and a fourth P + injection region in the first N well from left to right; forming a fifth P + injection region in the third P well, and arranging a sixth P + injection region in the fourth P well;
step eight: forming an N + injection region III at the junction of the second P well and the first N well, and forming an N + injection region IV at the junction of the first N well injection region and the third P well;
step nine: forming an N + injection region I and an N + injection region II in the second P well, forming an N + injection region V and an N + injection region VI in the third P well, wherein the left side of the first field oxide isolation region is in contact with the edge of the right side of the first P + injection region, the right side of the first field oxide isolation region is in contact with the edge of the left side of the second P + injection region, the second field oxide isolation region is between the second P + injection region and the N + injection region I, the third field oxide isolation region is between the N + injection region I and the N + injection region II, the fourth field oxide isolation region is between the N + injection region II and the N + injection region III, the fifth field oxide isolation region is between the N + injection region III and the third P + injection region, the sixth field oxide isolation region is between the third P + injection region and the fourth P + injection region, the seventh field oxide isolation region is between the fourth P + injection region and the N + injection region IV, and the eighth field oxide isolation region is between the N + injection region IV and the N + injection region V, the ninth field oxygen isolation region is arranged between the N + injection region V and the N + injection region VI, the tenth field oxygen isolation region is arranged between the N + injection region VI and the fifth P + injection region, the left side of the eleventh field oxygen isolation region is contacted with the edge of the right side of the fifth P + injection region, and the right side of the eleventh field oxygen isolation region is contacted with the edge of the left side of the sixth P + injection region;
step ten: annealing the first P + injection region, the second P + injection region, the third P + injection region, the fourth P + injection region, the fifth P + injection region, the sixth P + injection region, the N + injection region I, the N + injection region II, the N + injection region III and the N + injection region VI;
step eleven: the third P + injection region is connected with the N + injection region I through metal, the fourth P + injection region is connected with the N + injection region VI through metal, the first P + injection region, the second P + injection region, the sixth P + injection region and the N + injection region II are connected together and serve as the cathode of the device, and the fifth P + injection region and the N + injection region II are connected together and serve as the anode of the device.
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