CN107195630A - A kind of new E SD protection structures and its implementation - Google Patents
A kind of new E SD protection structures and its implementation Download PDFInfo
- Publication number
- CN107195630A CN107195630A CN201710420086.7A CN201710420086A CN107195630A CN 107195630 A CN107195630 A CN 107195630A CN 201710420086 A CN201710420086 A CN 201710420086A CN 107195630 A CN107195630 A CN 107195630A
- Authority
- CN
- China
- Prior art keywords
- high concentration
- type doping
- type
- traps
- new
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
Abstract
The invention discloses a kind of new E SD protection structures and its implementation, the esd protection structure includes：Semiconductor substrate；It is created on the first N traps and the 2nd N traps in the semiconductor substrate；The thyristor being arranged in the first N traps and the diode structure being arranged in the 2nd N traps, high concentration p-type adulterates (28), high concentration n-type doping (20), high concentration n-type doping (22) isolation is arranged at the first N traps top, p-type ESD implant layers (40) are arranged at below the high concentration n-type doping (22), high concentration n-type doping (20) suspension joint, the high concentration p-type adulterates (28), first N traps, p-type ESD implant layers (40), high concentration n-type doping (22) constitutes the thyristor, pass through the present invention, the maintenance voltage of esd protection structure echo effect can be increased.
Description
Technical field
The present invention relates to semiconductor integrated circuit technical field, more particularly to a kind of low trigger voltage high maintenance voltage
The new E SD protection structures and its implementation of thyristor type.
Background technology
In electrostatic (ESD, Electro-Static Discharge) design protection field, thyristor (SCR,
Silicon Controlled Rectifier) because with ESD discharge capacities are strong and the small characteristic of parasitic capacitance and extensively paid attention to,
But two major defects that such device is present limit its application：First defect be the trigger voltage of echo effect very
Height, because its trigger voltage is mainly limited the breakdown reverse voltage of p-well by N traps；Second defect is the maintenance of echo effect
Voltage is very low, it is easy to cause latch-up.
For this higher defect of trigger voltage of thyristor echo effect, industrial circle proposes various schemes to drop
The trigger voltage of low echo effect, thyristor as depicted in figs. 1 and 2.
Thyristor shown in Fig. 1 is the one N-type heavy doping across N traps and p-well of insertion between N traps and p-well, from
And reduction N traps are reached to the purpose of the breakdown reverse voltage of p-well, specifically, thyristor shown in Fig. 1 (SCR,
Silicon Controlled Rectifier) type include multiple shallow trench isolations layer (STI, Shallow Trench
Isolation) 10, high concentration n-type doping (N+) 20, high concentration p-type doping (P+) 22, high concentration n-type doping (N+) 24, highly concentrated
Spend n-type doping (N+) 26, high concentration p-type doping (P+) 28, N traps (N-Well) 50, p-well (P-Well) 60, matrix (Psub) 70
And diode 80.
Whole ESD device is placed on matrix (Psub) 70, and a N trap (N-Well) is generated on the left side of matrix (Psub) 70
50, in one p-well (P-Well) 60 of the right of matrix (Psub) 70 generation, high concentration n-type doping (N+) 20, the doping of high concentration p-type
(P+) 22 the top of N traps (N-Well) 50, high concentration p-type doping (P+) 22, N traps (N-Well) 50 and matrix (Psub) 70 are placed in
Constitute equivalent PNP triode structure, high concentration n-type doping (N+) 20 and the formation diffusion resistance Equivalent conjunction of N traps (N-Well) 50
To the PNP triode base stage, high concentration p-type doping (P+) 22 constitutes the emitter stage PN of the PNP triode with N traps (N-Well) 50
Knot, matrix (Psub) 70 constitutes the colelctor electrode PN junction of the PNP triode, high concentration n-type doping (N+) with N traps (N-Well) 50
26th, high concentration p-type doping (P+) 28 is placed in the top of p-well (P-Well) 60, N traps (N-Well) 50, matrix (Psub) 70/P traps (P-
Well) 60 equivalent N PN audions, N traps (N-Well) 50 and matrix (Psub) 70 are constituted with high concentration n-type doping (N+) 26
Constitute the colelctor electrode PN junction of the NPN triode, matrix (Psub) 70/P traps (P-Well) 60 and the structure of high concentration n-type doping (N+) 26
Into the emitter stage PN junction of equivalent N PN triodes, high concentration p-type doping (P+) 26, p-well (P-Well) 60, the structure of matrix (Psub) 70
The base stage of equivalent N PN triodes is connected into diffusion resistance, high concentration n-type doping (N+) 24 is placed in N traps (N-Well) 50 and P
Above the boundary of trap (P-Well) 60, high concentration n-type doping (N+) 20, high concentration p-type doping (P+) 22, high concentration n-type doping
(N+) 24, with shallow trench isolation layer (STI, Shallow between high concentration n-type doping (N+) 26, high concentration p-type doping (P+) 28
Trench Isolation) 10 isolation；Constituted with metal connection high concentration n-type doping (N+) 20, high concentration p-type doping (P+) 24
The anode A of the thyristor type ESD device, high concentration n-type doping (N+) 26, high concentration p-type doping (P+) 28 connect after being connected
It is connected to the negative electrode K of thyristor type (SCR) ESD device.
Thyristor type ESD device shown in Fig. 2 be on the basis of the thyristor type ESD device shown in Fig. 1,
The high concentration n-type doping (N+) 26 on right side, high concentration p-type doping (P+) 28 are moved right, in the p-well (P- being newly available
Well) 60 top increases by a N-type grid (30), and the grid (30) is connected to the moon of thyristor with high-concentration dopant 26
Pole, constitutes N-type gate control diode, by introducing N-type gate control diode (Gated Diode), and further reduction N traps are to p-well
Breakdown reverse voltage, so that the purpose of the further trigger voltage of reduction thyristor echo effect is reached, even if but such as
This, the trigger voltage of the thyristor echo effect shown in Fig. 2 still compares high, and the trigger voltage is also constrained to
Existing technological parameter, the adjustment free degree is little.
For thyristor echo effect maintenance voltage than this relatively low defect, industrial circle is typically by increasing silicon
P in control rectifier N traps ties the distance (c+d) of the N knots into p-well to realize, as shown in figure 1, or passing through external diode
To realize, as shown in Figure 3.
The esd protection structure of prior art shown in Fig. 3 includes oxide layer (OX) 10, high concentration n-type doping (N+) 20, highly concentrated
Spend n-type doping (N+) 22, high concentration p-type doping (P+) 24, high concentration n-type doping (N+) 26, p-type ESD implant layers (ESD IMP)
40th, N traps (N-Well) 60, N traps (N-Well) 70, p-type matrix (Psub) 80, resistance R.
Whole esd protection structure is placed on p-type matrix (Psub) 80, and two N traps are generated in p-type matrix (Psub) 80
(N-Well) 60/70, (two N traps (N-Well) are still isolated by p-type matrix (Psub) 80 between two N traps (N-Well) 60/70
60/70 can not be overlapping), high concentration n-type doping (N+) 20, high concentration n-type doping (N+) 22 are placed on left side N traps (N-Well) 60
Portion, high concentration n-type doping (N+) 20, p-type ESD implant layers 40 constitute NPN triode structure with high concentration n-type doping (N+) 22,
High concentration n-type doping (N+) 22 be colelctor electrode, high concentration n-type doping (N+) 20 be emitter stage, high concentration p-type doping (P+) 24,
High concentration n-type doping (N+) 26 is placed in the right N traps (N-Well) 70 top, and high concentration p-type doping (P+) 24, high concentration N-type are mixed
Miscellaneous (N+) 26 constitutes diode structure, high concentration n-type doping (N+) 20, high concentration n-type doping (N+) 22, the doping of high concentration p-type
(P+) isolated between 24, high concentration n-type doping (N+) 26 with oxide layer (OX) 10, p-type ESD implant layers (ESD IMP) 40 are placed in collection
Below electrode N knots (high concentration n-type doping (N+) 22)；Adulterated with metal connection high concentration n-type doping (N+) 22, high concentration p-type
(P+) 24 to resistance R one end, and the resistance R other end is connected to high concentration n-type doping (N+) 26 i.e. esd protection structure negative electrode K,
High concentration n-type doping (N+) 20 is the anode A of esd protection structure.
Wherein, N traps (N-Well) 60 are located at N traps for the NPN structures being located at the left side in N traps (N-Well) 60 and the right
(N-Well) the diode structure isolation in 70.
But the shortcoming of the method for the forward conduction diode of above-mentioned external parallel resistance is every increase one-level forward conduction
Diode is only capable of maintenance voltage increasing 0.6 volt to 0.8 volt or so, and the shortcoming of this method is to considerably increase ESD guarantors in addition
The overall chip area of protection structure.
The content of the invention
To overcome the shortcomings of that above-mentioned prior art is present, the purpose of the present invention is to provide a kind of new E SD protection structures
And its implementation, to increase the maintenance voltage of esd protection structure echo effect.
In view of the above and other objects, the present invention proposes a kind of new E SD protection structures, it is characterised in that the ESD is protected
Structure includes：
Semiconductor substrate；
It is created on the first N traps and the 2nd N traps in the Semiconductor substrate；
The thyristor being arranged in the first N traps and the diode structure being arranged in the 2nd N traps are high
Concentration of P type doping (28), high concentration n-type doping (20), high concentration n-type doping (22) are isolated from left to right is arranged at described first
N traps top, p-type ESD implant layers (40) are arranged at below the high concentration n-type doping (22), and the high concentration n-type doping (20) is floated
Connect, the high concentration p-type doping (28), the first N traps, p-type ESD implant layers (40), high concentration n-type doping (22) constitute the silicon control
Rectifier.
Further, the high concentration p-type doping (28) is the anode A of new E SD protection structures.
Further, high concentration p-type doping (24), high concentration n-type doping (26) isolation are arranged at the 2nd N traps top, structure
Into the diode structure, the high concentration n-type doping (26) isolates setting with high concentration p-type doping (24).
Further, the high concentration p-type doping (28), high concentration n-type doping (20), high concentration n-type doping (22), height
Isolated between concentration of P type doping (24), high concentration n-type doping (26) with oxide layer (10), the high concentration p-type is adulterated (28) and high
Oxide layer (10) width between concentration N-dopant (20) is 0.5um~20um.
Further, oxide layer is placed on the left side of high concentration p-type doping (28), the right side of high concentration n-type doping (26)
(10) it is used to isolate other devices.
Further, the depth of the oxide layer (10) of all isolation exceedes the depth of doped region.
Further, the high concentration n-type doping (22), high concentration p-type doping (24) a to resistance are connected using metal
One end, the other end of the resistance is connected to the high concentration n-type doping (26) as the negative electrode of new E SD protection structures
K。
To reach above-mentioned purpose, the present invention also provides a kind of implementation method of new E SD protection structures, including following step
Suddenly：
There is provided semi-conductive substrate for step one；
Step 2, generates the first N traps and the 2nd N traps in the Semiconductor substrate；
Step 3, thyristor is formed in the first N traps, and diode structure is formed in the 2nd N traps, will
High concentration p-type doping (28), high concentration n-type doping (20), high concentration n-type doping (22) are isolated from left to right is arranged at described the
One N traps top, p-type ESD implant layers (40) are arranged at below the high concentration n-type doping (22), the high concentration n-type doping (20)
Suspension joint, the high concentration p-type doping (28), the first N traps, p-type ESD implant layers (40), high concentration n-type doping (22) constitute the silicon
Control rectifier.
Further, in step 3, high concentration p-type is adulterated (24), high concentration n-type doping (26) isolation is arranged at the
Two N traps tops, constitute the diode structure, and the high concentration n-type doping (22) isolates setting with high concentration p-type doping (24).
Further, in after step 3, in addition to：
Using high concentration p-type doping (28) as the anode of new E SD protection structures, the high concentration is connected using metal
N-type doping (22), high concentration p-type doping (24) to one end of a resistance, the other end of the resistance are connected to the high concentration N
Type adulterate (26) as new E SD protection structures negative electrode.
Compared with prior art, a kind of new E SD protection structures and its implementation of the invention, it existing by such as scheming
On the basis of esd protection structure shown in 3, added in the leftmost side of the first N traps 60 of the triode of existing esd protection structure high
Concentration of P type adulterates (P+) 28, and (P+) 28 that the high concentration p-type is adulterated is as the anode of new E SD protection structures, and by height
The suspension joint of concentration N-dopant (N+) 20, realizes the agent of ESD IMP (ESD implant layers (ESD IMP) 40) ion implanting of adjustment p-type
Amount can reduce the purpose of the trigger voltage of echo effect, and the present invention is inserted by the high concentration n-type doping (N+) 20 of suspension joint
Enter the method between high concentration p-type doping (28) and high concentration n-type doping (22), to reduce high concentration p-type doping (28) to N
Trap injects minority carrier (hole) and reaches N traps (60) and the efficiency at p-type ESD implant layers (40) interface, so as to reduce parasitism
The current gain of PNP three-levels, so as to realize the purpose of the maintenance voltage of increase new E SD protection structure echo effects, now
The essence of high concentration n-type doping (N+) 20 of suspension joint plays a part of protection ring (Guard Ring), while can be floating by regulation
The size of the N+ knots of the high concentration n-type doping (N+) 20 connect, depth and high concentration n-type doping (20) are adulterated with high concentration p-type
The distance between (28) S realizes the purpose of regulation maintenance voltage.And it is new mentioned by the present invention in the case of preferably
The maintenance voltage of thyristor P+/N-Well/PESD/N+ (i.e. 28/60/40/22) device in esd protection structure can reach
To certain ideal value, esd protection circuit can also be met even if by extraneous forward conduction diode in parallel (i.e. 24/26) removal by realizing
Design requirement, so as to greatly save the chip area of IC design.
Brief description of the drawings
Fig. 1 is the schematic diagram of the esd protection structure of a prior art；
Fig. 2 is the schematic diagram of the esd protection structure of another prior art；
Fig. 3 is the schematic diagram of the esd protection structure of another prior art；
Fig. 4 is a kind of circuit structure diagram of the preferred embodiment of new E SD protection structures of the invention；
Fig. 5 is a kind of step flow chart of the implementation method of new E SD protection structures of the invention；
Fig. 6 is application scenarios schematic diagram of the invention.
Embodiment
Below by way of specific instantiation and embodiments of the present invention are described with reference to the drawings, those skilled in the art can
Understand the further advantage and effect of the present invention easily by content disclosed in the present specification.The present invention can also pass through other differences
Instantiation implemented or applied, the various details in this specification also can based on different viewpoints with application, without departing substantially from
Various modifications and change are carried out under the spirit of the present invention.
Fig. 4 is a kind of circuit structure diagram of the preferred embodiment of new E SD protection structures of the invention.As shown in figure 4, this hair
A kind of bright new E SD protection structures, including oxide layer (OX) 10, high concentration n-type doping (N+) 20, high concentration n-type doping (N+)
22nd, high concentration p-type doping (P+) 24, high concentration n-type doping (N+) 26, high concentration p-type doping (P+) 28, p-type ESD implant layers
The N traps (N-Well) 70 of (ESD IMP) the 40, the first N traps (N-Well) the 60, the 2nd, P type substrate (P-Sub) 80, resistance R.
Whole esd protection structure is placed in P type substrate (P-Sub) 80, and two N-types are generated in P type substrate (P-Sub) 80
Trap N traps：Still by P type substrate between first N traps (N-Well) 60 and the 2nd N traps (N-Well) 70, two N traps (N-Well) 60/70
(P-Sub) 80 isolation (two N traps (N-Well) 60/70 can not be overlapping), high concentration p-type doping (P+) 28, high concentration n-type doping
(N+) 20, high concentration n-type doping (N+) 22 is placed in the top of the first N traps (N-Well) of the left side 60, p-type ESD implant layers (ESD IMP)
40 are placed in the lower section of high concentration n-type doping (N+) 22, the suspension joint of high concentration n-type doping (N+) 20, high concentration p-type doping (P+) 28, the
One N traps 60, p-type ESD implant layers (ESD IMP) 40, high concentration n-type doping (N+) 22 constitute thyristor, and high concentration p-type is mixed
Miscellaneous (P+) 28 is the anode A of the ESD device, and the doping of high concentration p-type (P+) 24, high concentration n-type doping (N+) 26 are placed in the right the
The top of two N traps (N-Well) 70, high concentration p-type doping (P+) 24, high concentration n-type doping (N+) 26 constitute diode structure, high
Concentration of P type doping (P+) 28, high concentration n-type doping (N+) 20, high concentration n-type doping (N+) 22, high concentration p-type doping (P+)
24th, isolated between high concentration n-type doping (N+) 26 with oxide layer (OX) 10, high concentration p-type doping (P+) 28 left side, high concentration N
The isolation of oxide layer (OX) 10 is also placed with by esd protection structure and other device isolations in type doping (N+) 26 right side, it is all every
From oxide layer (OX) 10 depth exceed doped region (high concentration p-type doping (P+) 28, high concentration n-type doping (N+) 20,
High concentration n-type doping (N+) 22, p-type ESD implant layers (ESD IMP) 40, high concentration p-type doping (P+) 24, high concentration n-type doping
(N+) depth 26)；(P+) 24 is adulterated to resistance R one end with metal connection high concentration n-type doping (N+) 22, high concentration p-type,
The resistance R other end is connected to high concentration n-type doping (N+) the 26 i.e. negative electrode K of esd protection structure.
Wherein, the first N traps (N-Well) 60 and the first N traps (N-Well) 70 are used to that the first N traps (N-Well) 60 will to be located at
Interior silicon-controlled rectifier structure is isolated with the diode structure in the 2nd N traps (N-Well) 70.
Fig. 5 is a kind of step flow chart of the implementation method of new E SD protection structures of the invention.As shown in figure 5, of the invention
A kind of implementation method of new E SD protection structures, comprises the following steps：
Step 501 is there is provided semi-conductive substrate, and there is provided a P type substrate (P-Sub) 80 in the specific embodiment of the invention.
Step 502, two N traps, i.e. the N traps (N- of the first N traps (N-Well) the 60, the 2nd are generated in the Semiconductor substrate
Well) 70, in the specific embodiment of the invention, generated in p-type matrix (P-Sub) 80 between two N traps, two N traps 60/70 still
(two N traps 60/70 can not be overlapping) is isolated by p-type matrix (P-Sub) 80, in present pre-ferred embodiments, the generation of the first N traps
On the left of p-type matrix, the 2nd N traps are created on the right side of p-type matrix.
Step 503, thyristor is formed in the first N traps 60, diode structure is formed in the 2nd N traps 70.Specifically
Ground said, adulterate (P+) 28, high concentration n-type doping (N+) 20, high concentration n-type doping (N+) 22 of high concentration p-type is placed in into the left side the
The top of one N traps (N-Well) 60, p-type ESD implant layers (ESD IMP) 40 are placed in the lower section of high concentration n-type doping (N+) 22, high concentration
The suspension joint of n-type doping (N+) 20, it is high concentration p-type doping (P+) the 28, the first N traps 60, p-type ESD implant layers (ESD IMP) 40, highly concentrated
Spend n-type doping (N+) 22 and constitute thyristor, high concentration p-type doping (P+) 24, high concentration n-type doping (N+) 26 are placed in the right side
The top of the 2nd N traps (N-Well) of side 70, high concentration p-type doping (P+) 24, high concentration n-type doping (N+) 26 constitute diode junction
Structure, high concentration p-type doping (P+) 28, high concentration n-type doping (N+) 20, high concentration n-type doping (N+) 22, the doping of high concentration p-type
(P+) isolated between 24, high concentration n-type doping (N+) 26 with oxide layer (OX) 10, (P+) 28 left side it is preferred that high concentration p-type is adulterated
The isolation of oxide layer (OX) 10 is also placed with by ESD device and other device isolations in side, the right side of high concentration n-type doping (N+) 26.
The depth of the oxide layer (OX) 10 of all isolation exceedes doped region (high concentration p-type doping (P+) 28, high concentration n-type doping
(N+) 20, high concentration n-type doping (N+) 22, p-type ESD implant layers (ESD IMP) 40, high concentration p-type doping (P+) 24, high concentration
N-type doping (N+) 26) depth.
Step 504, the anode A and negative electrode K of new E SD protection structures are built, i.e., is made high concentration p-type doping (P+) 28
For the anode A of new E SD protection structures, the high concentration n-type doping (N+) 22, high concentration p-type doping (P are connected using metal
+) 24 to one resistance R one end, the resistance R other end is connected to high concentration n-type doping (N+) 26 as new E SD protection knots
The negative electrode K of structure.
It can be seen that the present invention is whole in the silicon control shown in the NPN triode type esd protection structure and Fig. 1 shown in existing Fig. 3
A kind of ESD device proposed on the basis of stream type ESD device, the thyristor of the new E SD devices of the present invention is by P+/N-
Well/PESD/N+ (i.e. 28/60/40/22) structure is constituted, can be by adjusting the ESD IMP (ESD implant layers (ESD of p-type
IMP) 40) dosage of ion implanting reduces the trigger voltage of echo effect；The present invention is mixed by the high concentration N-type of suspension joint in addition
Miscellaneous (N+) 20 is inserted in the method between high concentration p-type doping (28) and high concentration n-type doping (22), to reduce high concentration p-type
The minority carrier (hole) that doping (28) is injected to N traps reaches N traps (60) and the efficiency at p-type ESD implant layers (40) interface, from
And the current gain of parasitic PNP triode is reduced, so that realize the maintenance voltage of increase new E SD device echo effects
Purpose, now the high concentration n-type doping (N+) 20 of suspension joint is substantive plays a part of protection ring (Guard Ring), while of the invention
The size of the high concentration n-type doping (N+) 20 for adjusting suspension joint, depth and high concentration n-type doping (20) and high concentration can be passed through
P-type doping the distance between (28) S (i.e. oxide layer 10, S span is 0.5um~20um) adjusts maintenance voltage, and
And in the case of preferably, the thyristor P+/N-Well/PESD/N+ in new E SD protection structures mentioned by the present invention
The maintenance voltage of (i.e. 28/60/40/22) device can reach ideal value, even if realizing the extraneous pole of forward conduction in parallel two
Pipe (i.e. 24/26), which is removed, can also meet esd protection circuit design, so as to greatly save the chip area of circuit design.
The new E SD protection structures of the present invention can be applied to input/output terminal and protection electricity in esd protection circuit
In road in the protection circuit of power supply over the ground, to lift the ESD protection capability that chip is overall, as shown in Figure 6.
In summary, a kind of new E SD protection structures and its implementation of the invention, it is tied by being protected in existing ESD
On the basis of structure, high concentration p-type doping (P+) 28 is added in the leftmost side of the first N traps 60 of the triode of existing esd protection structure,
The high concentration p-type is adulterated to (P+) 28 as the anode of new E SD devices, to realize that (ESD is implanted into the ESD IMP of adjustment p-type
Layer (ESD IMP) 40) ion implanting dosage can reduce echo effect trigger voltage purpose, and the present invention pass through will
The suspension joint of high concentration n-type doping (N+) 20, is inserted between high concentration p-type doping (28) and high concentration n-type doping 22, now suspension joint
The essence of high concentration n-type doping (N+) 20 play a part of protection ring (Guard Ring), the doping of high concentration p-type can be reduced
(28) minority carrier (hole) injected to N traps reaches N traps (60) and the efficiency at p-type ESD implant layers (40) interface, so as to drop
The current gain of low parasitic PNP triode, so as to realize the mesh of the maintenance voltage of increase new E SD device echo effects
, the size that the N+ of the high concentration n-type doping (N+) 20 by adjusting suspension joint is tied, depth and high concentration N can be realized in addition
Type doping (20) adulterates the distance between (28) S to adjust the purpose of maintenance voltage with high concentration p-type, and in preferable situation
Under, the maintenance voltage of new E SD P+/N-Well/PESD/N+ (i.e. 28/60/40/22) device mentioned by the present invention can reach
To ideal value, esd protection circuit design can also be met even if by extraneous forward conduction diode in parallel removal by realizing, so that greatly
The big chip area for saving circuit design.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.Any
Art personnel can be modified above-described embodiment and changed under the spirit and scope without prejudice to the present invention.Therefore,
The scope of the present invention, should be as listed by claims.
Claims (10)
1. a kind of new E SD protection structures, it is characterised in that the esd protection structure includes：
Semiconductor substrate (80)；
It is created on the first N traps (60) and the 2nd N traps (70) in the Semiconductor substrate；
The thyristor being arranged in the first N traps and the diode structure being arranged in the 2nd N traps, high concentration
P-type doping (28), high concentration n-type doping (20), high concentration n-type doping (22) are isolated from left to right is arranged at the first N traps
Top, p-type ESD implant layers (40) are arranged at below the high concentration n-type doping (22), high concentration n-type doping (20) suspension joint,
High concentration p-type doping (28), the first N traps, p-type ESD implant layers (40), that high concentration n-type doping (22) constitutes the silicon control is whole
Flow device.
2. a kind of new E SD protection structures as claimed in claim 1, it is characterised in that：High concentration p-type doping (28) is
The anode A of new E SD protection structures.
3. a kind of new E SD protection structures as claimed in claim 2, it is characterised in that：High concentration p-type doping (24), highly concentrated
Degree n-type doping (26) isolation is arranged at the 2nd N traps top, constitutes the diode structure, the high concentration n-type doping (22) and height
Concentration of P type doping (24) isolation is set.
4. a kind of new E SD protection structures as claimed in claim 3, it is characterised in that：The high concentration p-type doping (28),
High concentration n-type doping (20), high concentration n-type doping (22), high concentration p-type doping (24), high concentration n-type doping use oxygen between (26)
Change layer (10) isolation, oxide layer (10) width between the high concentration p-type doping (28) and high concentration n-type doping (20) is
0.5um~20um.
5. a kind of new E SD protection structures as claimed in claim 4, it is characterised in that：A left side for high concentration p-type doping (28)
Oxide layer (10) is placed for isolating other devices in side, the right side of high concentration n-type doping (26).
6. a kind of new E SD protection structures as claimed in claim 5, it is characterised in that：The oxide layer (10) of all isolation
Depth exceed doped region depth.
7. a kind of new E SD protection structures as claimed in claim 4, it is characterised in that：The high concentration N is connected using metal
Type doping (22), high concentration p-type doping (24) to one end of a resistance, the other end of the resistance are connected to the high concentration N
Type adulterate (26) as new E SD protection structures negative electrode K.
8. a kind of implementation method of new E SD protection structures, comprises the following steps：
There is provided semi-conductive substrate (80) for step one；
Step 2, generates the first N traps (60) and the 2nd N traps (70) in the Semiconductor substrate；
Step 3, thyristor is formed in the first N traps, and diode structure is formed in the 2nd N traps, will be highly concentrated
Degree p-type doping (28), high concentration n-type doping (20), high concentration n-type doping (22) are isolated from left to right is arranged at the first N
Trap top, p-type ESD implant layers (40) are arranged at below the high concentration n-type doping (22), and the high concentration n-type doping (20) is floated
Connect, the high concentration p-type doping (28), the first N traps (60), p-type ESD implant layers (40), high concentration n-type doping (22), which are constituted, is somebody's turn to do
Thyristor.
9. a kind of implementation method of new E SD protection structures as claimed in claim 8, it is characterised in that：, will in step 3
High concentration p-type doping (24), high concentration n-type doping (26) isolation are arranged at the 2nd N traps top, constitute the diode structure,
The high concentration n-type doping (26) isolates setting with high concentration p-type doping (24).
10. a kind of implementation method of new E SD protection structures as claimed in claim 9, it is characterised in that in after step 3,
Also include：
Using high concentration p-type doping (28) as the anode of new E SD protection structures, the high concentration N-type is connected using metal
Doping (22), high concentration p-type doping (24) to one end of a resistance, the other end of the resistance are connected to the high concentration N-type
Adulterate the negative electrode of (26) as new E SD protection structures.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710420086.7A CN107195630B (en) | 2017-06-06 | 2017-06-06 | A kind of new E SD protection structure and its implementation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710420086.7A CN107195630B (en) | 2017-06-06 | 2017-06-06 | A kind of new E SD protection structure and its implementation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107195630A true CN107195630A (en) | 2017-09-22 |
| CN107195630B CN107195630B (en) | 2019-11-26 |
Family
ID=59876438
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710420086.7A Active CN107195630B (en) | 2017-06-06 | 2017-06-06 | A kind of new E SD protection structure and its implementation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107195630B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107516657A (en) * | 2017-07-31 | 2017-12-26 | 上海华力微电子有限公司 | A kind of new E SD protection structures and its implementation |
| US10504886B1 (en) | 2018-09-05 | 2019-12-10 | Hong Kong Applied Science and Technology Research Institute Company, Limited | Low-capacitance electro-static-discharge (ESD) protection structure with two floating wells |
| CN110783328A (en) * | 2018-07-31 | 2020-02-11 | 立积电子股份有限公司 | Anti-parallel diode device |
| CN112086451A (en) * | 2020-10-30 | 2020-12-15 | 上海华力微电子有限公司 | Silicon controlled rectifier type ESD (electro-static discharge) protection structure without hysteresis effect and implementation method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102163840A (en) * | 2010-02-24 | 2011-08-24 | 台湾积体电路制造股份有限公司 | Electrostatic discharge protection circuit, structure and radio-frequency receiver |
| CN102569360A (en) * | 2012-03-09 | 2012-07-11 | 浙江大学 | Bidirectional triode thyristor based on diode auxiliary triggering |
| KR20140038813A (en) * | 2012-09-21 | 2014-03-31 | 단국대학교 산학협력단 | Electrostatic discharge protecting device of having low trigger voltage and high holding voltage |
| CN103730461A (en) * | 2014-01-16 | 2014-04-16 | 湘潭大学 | SCR structure with high maintaining voltage and manufacturing method thereof |
| KR101392587B1 (en) * | 2013-02-19 | 2014-05-27 | 주식회사 동부하이텍 | High voltage electro-static discharge protection device |
| CN106356335A (en) * | 2016-09-26 | 2017-01-25 | 上海华力微电子有限公司 | Novel ESD (Electro-Static Discharge) device and manufacturing method thereof |
-
2017
- 2017-06-06 CN CN201710420086.7A patent/CN107195630B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102163840A (en) * | 2010-02-24 | 2011-08-24 | 台湾积体电路制造股份有限公司 | Electrostatic discharge protection circuit, structure and radio-frequency receiver |
| CN102569360A (en) * | 2012-03-09 | 2012-07-11 | 浙江大学 | Bidirectional triode thyristor based on diode auxiliary triggering |
| KR20140038813A (en) * | 2012-09-21 | 2014-03-31 | 단국대학교 산학협력단 | Electrostatic discharge protecting device of having low trigger voltage and high holding voltage |
| KR101392587B1 (en) * | 2013-02-19 | 2014-05-27 | 주식회사 동부하이텍 | High voltage electro-static discharge protection device |
| CN103730461A (en) * | 2014-01-16 | 2014-04-16 | 湘潭大学 | SCR structure with high maintaining voltage and manufacturing method thereof |
| CN106356335A (en) * | 2016-09-26 | 2017-01-25 | 上海华力微电子有限公司 | Novel ESD (Electro-Static Discharge) device and manufacturing method thereof |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107516657A (en) * | 2017-07-31 | 2017-12-26 | 上海华力微电子有限公司 | A kind of new E SD protection structures and its implementation |
| CN107516657B (en) * | 2017-07-31 | 2019-10-25 | 上海华力微电子有限公司 | A kind of new E SD protection structure and its implementation |
| CN110783328A (en) * | 2018-07-31 | 2020-02-11 | 立积电子股份有限公司 | Anti-parallel diode device |
| CN110783328B (en) * | 2018-07-31 | 2022-09-06 | 立积电子股份有限公司 | Anti-parallel diode device |
| US10504886B1 (en) | 2018-09-05 | 2019-12-10 | Hong Kong Applied Science and Technology Research Institute Company, Limited | Low-capacitance electro-static-discharge (ESD) protection structure with two floating wells |
| WO2020047903A1 (en) * | 2018-09-05 | 2020-03-12 | Hong Kong Applied Science and Technology Research Institute Company Limited | Low-capacitance electro-static-discharge (esd) protection structure with two floating wells |
| CN112086451A (en) * | 2020-10-30 | 2020-12-15 | 上海华力微电子有限公司 | Silicon controlled rectifier type ESD (electro-static discharge) protection structure without hysteresis effect and implementation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107195630B (en) | 2019-11-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104752417B (en) | Controllable silicon electrostatic protection device and forming method thereof | |
| CN108183101B (en) | Without echo effect thyristor type esd protection structure and its implementation | |
| CN107369682B (en) | A kind of novel thyristor type esd protection structure and its implementation | |
| CN107248514B (en) | A kind of new E SD protection structure and its implementation | |
| CN107564906B (en) | A kind of novel thyristor type esd protection structure and its implementation | |
| CN109037203A (en) | Thyristor type esd protection structure and implementation method | |
| CN107195630B (en) | A kind of new E SD protection structure and its implementation | |
| CN106449635A (en) | Novel low-trigger-voltage silicon-controlled rectifier and manufacturing method therefor | |
| US8390096B2 (en) | Adjustable holding voltage ESD protection device | |
| CN101506974A (en) | Latch-up free vertical TVS diode array structure using trench isolation | |
| CN108091650B (en) | Without echo effect thyristor type esd protection structure and its implementation | |
| CN110649016B (en) | Silicon controlled rectifier type ESD (electro-static discharge) protection structure without hysteresis effect and implementation method thereof | |
| CN107731811A (en) | A kind of SCR device triggered by longitudinal BJT for ESD protection | |
| CN107731810A (en) | A kind of low trigger voltage MLSCR devices for ESD protection | |
| CN107799517A (en) | ESD devices for semiconductor structure | |
| CN110518012A (en) | A kind of grid constraint thyristor ESD device and its implementation | |
| CN110491875B (en) | Bidirectional thyristor electrostatic protection device | |
| CN112928112B (en) | Low-trigger high-maintenance bidirectional SCR protective device and process method thereof | |
| CN103904076B (en) | ESD protection circuit | |
| CN105977253A (en) | Multi-trigger positive and negative voltage resisting SCR ESD protection device and technological method therefor | |
| CN106356335B (en) | A kind of ESD device and preparation method thereof | |
| CN103872038B (en) | Two-way three utmost point grid current body devices and manufacture method thereof and the circuit that comprises this device | |
| CN110504253A (en) | A kind of novel grid constraint thyristor ESD device and its implementation | |
| CN107516657B (en) | A kind of new E SD protection structure and its implementation | |
| CN110504254A (en) | A kind of novel grid constraint thyristor ESD device and its implementation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |