KR100854440B1 - Semiconductor integrated circuit - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides a semiconductor integrated circuit capable of stably separating and isolating analog circuits from electrical noise in a single integrated circuit for simultaneously supporting digital circuits, analog circuits, and radio frequency (RF) circuits. The present invention provides a semiconductor integrated circuit in which a digital circuit and an analog circuit are integrated on a single substrate, comprising: a substrate including a region where the digital circuit is to be formed and a region where the analog circuit is to be formed; A deep-well formed at a predetermined depth in the substrate so as to surround an area where an element of the digital circuit is formed or an area where an element of the analog circuit is to be formed so as to prevent interference between elements and elements of the digital circuit. To provide a semiconductor integrated circuit comprising a well).

Integrated circuits, Modular Bipolar-CMOS-DMOS (MBCD), Modular System On Chip (MSOC), Heterojunction Bipolar Transistor (HBT), Bipolar Junction Transistor (BJT), Complementary Metal Oxide Semiconductor (CMOS), Lateral Double Diffused Metal Oxide Semiconductor (STI), Shallow Trench Isolation (STI), Medium Trench Isolation (MTI), Deep Trench Isolation (DTI)

Description

Semiconductor Integrated Circuits {SEMICONDUCTOR INTEGRATED CIRCUIT}

1 is a cross-sectional view illustrating a semiconductor integrated circuit according to an embodiment of the present invention.

2A to 2F are cross-sectional views illustrating a method of manufacturing the semiconductor integrated circuit illustrated in FIG. 1.

<Explanation of symbols for the main parts of the drawings>

100: substrate 101, 102, 103: device isolation film

104A: Deep-well 104B, 104C: Collector

105A: Well 105B: Base

106: gate insulating film 107: gate conductive film

108: gate electrode 109: spacer

110A: Source and Drain Area 110B: Emitter

110C: pick up area 111: base

112: emitter

The present invention relates to a semiconductor integrated circuit and a manufacturing technology thereof, and more particularly, to a semiconductor integrated circuit for supporting digital circuits, analog circuits, and radio frequency (hereinafter referred to as RF) circuits as a single microchip. It relates to a manufacturing method.

MBCD for smart card integrated circuits for high frequency high voltage telecommunication systems such as automotive power integrated circuits and DC / DC converters, which are in high demand. Modular Bipolar-CMOS-DMOS Modular System On Chip (MSOC) is used as a single integrated circuit.

These single integrated circuits integrate these circuits together to simultaneously support digital circuits, analog circuits and RF circuits, thereby improving the quantity and quality of portable RF devices for wireless and optical communication applications. It was.

However, the integration of these various circuit types presents several inherent problems.

One of them is the problem of cross talk due to the unique characteristics of various circuit types. In other words, placing each of these various circuit types on a single integrated circuit allows one to get the advantage of inter-circuit interaction through a single integrated circuit board, but on the other hand, digital circuits, analog circuits and RF It is vulnerable to interference between circuits.

Analog circuits are very sensitive to electrical noise generated by other circuits or devices. In contrast, digital circuits are much less sensitive to electrical noise than analog circuits because of their digital characteristics. However, digital circuits generate a considerable amount of current noise by their nature. Thus, integrating analog and digital circuits on a single integrated circuit may result in the integration of analog and digital circuits on a single integrated circuit since the high noise components generated by the digital circuits may affect the analog circuits. In this case, the analog circuits need to be isolated or isolated from the electrical noise generated by the digital circuits.

Accordingly, the present invention has been proposed to solve the above problems of the prior art, and has the following objects.

First, an object of the present invention is to provide a semiconductor integrated circuit capable of stably separating and isolating analog circuits from electrical noise in a single integrated circuit for simultaneously supporting digital circuits, analog circuits, and RF circuits. .

Second, another object of the present invention is to provide a semiconductor integrated circuit capable of reducing the size of a single integrated circuit for simultaneously supporting digital circuits, analog circuits, and RF circuits.

Third, the present invention provides a single integrated circuit for simultaneously supporting digital circuits, analog circuits, and RF circuits, and includes a high voltage device constituting these various circuits and a device operating at a high voltage of 30V or more, such as a DMOS (Diffused Metal Oxide Semiconductor). Another object of the present invention is to provide a semiconductor integrated circuit capable of stably implementing device separation between the devices.

Fourth, another object of the present invention is to provide a semiconductor integrated circuit capable of minimizing manufacturing costs in a single integrated circuit for simultaneously supporting digital circuits, analog circuits, and RF circuits.

According to an aspect of the present invention, there is provided a semiconductor integrated circuit in which a digital circuit and an analog circuit are integrated on a single substrate, including a region where the digital circuit is to be formed and a region where the analog circuit is to be formed. A predetermined depth within the substrate so as to surround a region in which the elements of the digital circuit are formed or an region in which the elements of the analog circuit are formed to prevent interference between the substrate and the elements of the analog circuit and the elements of the digital circuit. Provided is a semiconductor integrated circuit including a deep well formed in the semiconductor device.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. This will be described.

In the drawings, the thicknesses of layers and regions are exaggerated for clarity, and where it is said that a layer is on another layer or substrate it may be formed directly on another layer or substrate, or A third layer may be interposed between them. Also, in the embodiments, the same reference numerals denote the same elements.

More specifically, in the embodiment, only some of the various elements constituting digital circuits, analog circuits, and RF circuits will be described for convenience of description. For example, Heterojunction Bipolar Transistor (HBT), Bipolar Junction Transistor (BJT), Complementary Metal Oxide Semiconductor (CMOS) devices as analog circuit devices, Lateral Double Diffused Metal Oxide Semiconductor (LDMOS) as digital circuit devices, and RF CMOS as RF circuit devices. An element is demonstrated as an example.

Example

1 is a cross-sectional view illustrating a semiconductor integrated circuit in accordance with an embodiment of the present invention.

Referring to FIG. 1, a semiconductor integrated circuit according to an exemplary embodiment of the present invention supports all the elements of an analog circuit, the elements of an RF circuit, and the elements of a digital circuit on a single substrate 100. The number, structure and arrangement of the elements is not limited.

A semiconductor integrated circuit according to an embodiment of the present invention is formed to have a predetermined depth in the substrate 100 so as to surround a region where elements of an analog circuit are to be formed and a region where elements of an RF circuit are to be formed, or a region where elements of a digital circuit are to be formed. Deep-well (104A).

The deep-well 104A is preferably formed in the region where elements of the digital circuit will be formed. This is because most of the electrical noise generated in semiconductor integrated circuits is generated in digital circuits. Therefore, rather than forming the deep-well 104A so as to surround both the region where the elements of the analog circuit are to be formed and the region where the elements of the RF circuit are to be formed, it surrounds only the region where the elements of the digital circuit are to be formed in terms of manufacturing cost. It is advantageous. However, as shown in the embodiment of the present invention, when the area where the elements of the digital circuit are to be formed is wider than the area including both the elements of the analog circuit and the area where the elements of the RF circuit are to be formed, the analog circuit and the RF circuit are It may be formed in the region to be formed.

In consideration of the electrical aspects, semiconductor integrated circuits integrate various circuits on a single substrate having a constant conductivity type. This allows a single substrate to function as a resistor that connects the elements of all circuits. Thus, it is possible to integrate the elements of the various circuits on a single substrate by strategically placing the elements of the various circuits on the deep-well 104A to isolate and isolate the elements of the various circuits from each other.

As such, the deep-well 104A performs a function of preventing interference between the analog circuit and the digital circuit, and is preferably formed through an ion implantation process having a relatively simple process. Instead of the deep-well 104A, a silicon on insulator (SOI) substrate formed with a buried oxide layer (BOX) may be used to prevent interference, but in this case, it is relatively inexpensive because it has a bad effect on manufacturing cost. bulk) substrate, and the process forms a deep-well 104A through a simple ion implantation process.

For example, the dip-well 104A may be appropriately changed according to the conductivity type of the substrate 100, and may be formed as n-well when using a p-type substrate and as p-well when using an n-type substrate. .

In addition, the semiconductor integrated circuit according to the embodiment of the present invention is a device isolation film 101 having a shallow trench isolation (STI), a medium trench isolation (MTI), and a deep trench isolation (DTI) structure to implement an operating range of elements of various circuits. 102, 103).

The device isolation film 101 of the STI structure has a trench depth for electrical isolation between low voltage devices such as BJT, CMOS, RF-CMOS, and Shallow Trench isolation-LDMOS (ST-LDMOS) devices operating at 10V or less. Is formed to have a depth within 1 μm from the upper surface of the substrate 100.

The device isolation layer 102 of the MTI structure may include a substrate 100 for electrical isolation between medium voltage devices, for example, medium-tension isolation-LDMOS (MT-LDMOS) devices, or between them and low-voltage devices. It is formed to have a depth of 1 ~ 3㎛ from the top surface.

The device isolation film 103 having the DTI structure is a high voltage device of 30V or more, for example, Deep Trench isolation-LDMOS (30V to 50V), HV-LDMOS (50V to several hundred V), high voltage HBT device A depth of at least 3 μm from the top surface of the substrate 100, such as 3-50 μm, preferably 3-10 μm, for electrical separation between high voltage elements such as or between them and low voltage elements or medium voltage elements. It is formed to have a depth of.

In addition, the semiconductor integrated circuit according to the embodiment of the present invention is an epitaxial layer in the substrate 100 of the region where the HV-LDMOS device is to be formed to implement the HV-LDMOS device operating from 50V to several hundreds of devices of the digital circuit Instead of forming an epitaxial layer, a high voltage well (not shown) formed through a drive-in process after a medium implant (MI) process is included.

Here, the MI process is, for example, in order to implant the impurity ions to a depth of 1 ~ 3㎛ from the upper surface of the substrate 100, by setting the ion implantation target (target) to a depth of 1 ~ 3㎛ It means the process of injecting into the substrate 100. In addition, the drive-in process refers to a process of controlling the temperature and the process time of the amount of impurity ions implanted at a predetermined depth through the MI process to have a final ion implantation depth and concentration distribution.

In addition, the description of the devices not illustrated in FIG. 1 will be described in detail through the method of manufacturing the semiconductor integrated circuit shown in FIGS. 2A through 2F.

First, as shown in FIG. 2A, since the HV-LDMOS device requires the largest depletion region, a HV-LDMOS device must form a high voltage well region (not shown), which is a process having the largest thermal budget. At this time, the high voltage well is formed by the MI process and the drive-in process as described above. For example, the high voltage well may be implanted with n-type or p-type impurity ions into the substrate 100 at a predetermined depth, and then subjected to a drive-in process at a temperature of about 1000 to 1200 ° C. for 2 to 15 hours. From a few to several tens of micrometers deep, the thickness of which is the same as that of the epi layer in a typical high voltage device.

On the other hand, the well for DT-LDMOS device can also use the high voltage well for HV-LDMOS device in common.

Subsequently, device isolation layers 101, 102, and 103 for device isolation are formed in the substrate 100. In this case, the device isolation layers 101, 102, and 103 are formed of STI, MTI, and DTI structures having different depths in order to obtain the widest operating range of the device implemented in the semiconductor integrated circuit.

For example, the device isolation layers 101, 102, and 103 may be formed in two ways corresponding to each structure.

The first method is a buried method using an insulating film. This method forms a trench by etching the substrate 100 to a predetermined depth, and then deposits an insulating film, for example, an HDP (High Density Plasma) oxide film having excellent embedding characteristics, so that the trench is buried. Then, the chemical mechanical polishing (CMP) process is performed to planarize the HDP oxide film.

The second method is an ion implantation method using O ₂ ions. This method proceeds to the step of directly injecting O ₂ ions having insulating properties into the substrate 100. In order to implement STI, MTI, and DTI structures in this way, instead of using a general ion implantation process, a so-called 'stack implant' is used.

The stack implant process is performed by changing the ion implantation energy in the whole process. First, high ion implantation energy is applied to inject the O ₂ ions at the deepest and then the ion implantation energy is lowered step by step to reduce the STI, MTI, and DTI structures. To form.

For example, the method of forming the device isolation film 101 having the STI structure using the first method is as follows.

First, a pad nitride film, which functions as a buffer oxide and a hard mask, is sequentially deposited on the substrate 100, and then an etch mask is formed by performing a photo process thereon. Then, an etching process using the etching mask is performed to sequentially etch a portion of the pad nitride film, the buffer oxide film, and the substrate 100 to form a shallow trench within 1 μm, and then to the inner wall of the trench. An oxidation process is performed to form a wall oxide film. Then, the HDP oxide film is buried so that the trench is buried, and then planarized by performing a CMP process. Thereafter, the pad nitride layer and the buffer oxide layer are removed to form an isolation layer 101 having an STI structure.

Similar to the STI structure described above, device isolation films 102 and 103 having an MTI structure and a DTI structure can be formed. Unlike the STI structure, however, the MTI structure is formed to a depth of 1 to 3 μm deeper than the STI structure, and the DTI structure is formed to a depth of 3 μm or more deeper than the MTI structure.

Subsequently, as shown in FIG. 2B, deep-well 104A is formed. In this case, the deep-well 104A is formed to surround the region where the analog circuit is to be formed or the region where the digital circuit is to be formed in order to prevent interference between the elements of the analog circuit and the elements of the digital circuit. For example, the deep-well 104A is formed in the p-type substrate 100 as n-type, and is formed with high ion implantation energy in a region where CMOS and RF-CMOS devices, which are devices of analog circuits, are to be formed.

Meanwhile, collectors 104B and 104C are formed in regions where the HBT element and the BJT element are to be formed during the deep-well 104A forming process.

Subsequently, as shown in FIG. 2C, other devices other than the HV-LDMOS and DT-LDMOS devices, that is, the CMOS, RF-CMOS, ST-LDMOS, MT-LDMOS devices, may be formed. Well 105A is formed at a low concentration. In the same figure, the well 105A is not shown in the ST-LDMOS and MT-LDMOS device regions, but this is for convenience of description, and the well is substantially the same in the region where the ST-LDMOS and MT-LDMOS devices are to be formed. 105A is formed.

Meanwhile, a base 105B is formed in a region where the BJT element is to be formed during the well 105A forming process. Therefore, in order to increase the gain of the BJT device, the width of the base 105B must be narrow. To this end, the collector may be formed with a lower ion implantation energy than the deep-well 104A by performing a photo process and an ion implantation process separately from the above-described deep-well 104A process.

Subsequently, as shown in FIG. 2D, the gate electrode 108 is formed on the substrate 100. In this case, the gate electrode 108 is formed in a stacked structure of the gate insulating film 106 and the gate conductive film 107. The gate insulating film 106 is formed in a stacked structure in which an oxide film (for example, SiO ₂ ) or an oxide film and a nitride film are stacked. The gate conductive film 107 is formed of a polysilicon film, a transition metal, a rare earth metal, an alloy film, a metal nitride film, a metal silicide layer, or a stacked structure thereof.

Meanwhile, the gate of the LDMOS device may be formed as a gate having a recess structure instead of a vertical structure stacked on the substrate 100 as shown in the same drawing.

Subsequently, as shown in FIG. 2E, an ion implantation process is performed to form a shallow low concentration junction region (not shown) in the substrate 100 exposed to both sides of the gate electrode 108.

Subsequently, gate spacers 109 are formed on both sidewalls of the gate electrode 108. At this time, the gate spacer 109 is formed of an oxide film, a nitride film, or a laminated film thereof.

Subsequently, a high concentration bonding region 110A deeper than a low concentration bonding region is formed in the substrate 100 exposed to both sides of the spacer 109. As a result, a source and drain region of a lightly doped drain (LDD) structure including a low concentration junction region and a high concentration junction region 110A is formed.

Meanwhile, the emitter 110B is formed in a region where the BJT element is to be formed during the process of forming the high concentration junction region 110A, and a pick-up region for supplying a bias to each well in the other region. 110C) is formed.

Subsequently, as shown in FIG. 2F, the base 111 and the emitter 112 are formed on the substrate 100 in the region where the HBT element is to be formed. At this time, the base 111 is formed of SiGe, and the emitter 112 is formed of a polysilicon film.

Subsequently, although not shown, a metal-insulator-metal (MIM) capacitor, a resistor, an inductor, or the like may be formed of RF passive elements in a region where the RF-CMOS is to be formed. transformers), and in addition, metal wirings or the like for connection between devices may be formed in integrated circuits. At this time, the inductor is formed of aluminum or copper.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the following effects can be obtained.

First, according to the present invention, in a single integrated circuit for simultaneously supporting digital circuits, analog circuits, and RF circuits, a deep well so as to surround an area where elements of the analog circuit are to be formed or an area where the elements of the digital circuit are to be formed. Analog circuits can be reliably isolated or isolated from electrical noise by forming

Second, according to the present invention, in a single integrated circuit for simultaneously supporting digital circuits, analog circuits, and RF circuits, STI, MTI, instead of a device isolation film formed through a conventional LOCOS (LOCal Oxidation of Silicon) process By forming the device isolation layer with the DTI structure, the size of a single integrated circuit can be greatly reduced compared to the existing.

Third, according to the present invention, in a single integrated circuit for simultaneously supporting digital circuits, analog circuits, and RF circuits, isolation between devices having a wide operating range is formed by forming device isolation layers with STI, MTI, and DTI structures. Can be reliably implemented.

Fourthly, according to the present invention, in a single integrated circuit for simultaneously supporting digital circuits, analog circuits, and RF circuits, a device isolation layer is formed by STI, MTI, and DTI structures to perform separation and isolation between devices. For isolation between devices, the length of a relatively long region of the junction region (source or drain region) of the LDD structure may be asymmetrically reduced, thereby reducing the size of the semiconductor integrated circuit as a whole.

Fifth, according to the present invention, in a single integrated circuit for simultaneously supporting digital circuits, analog circuits, and RF circuits, an epitaxial well is formed by using an ion implantation process and a drive-in process instead of an epitaxial layer. By performing the same function as the layer, the manufacturing cost can be reduced in comparison with the existing integrated circuit forming the epi layer.

Claims (31)

In a semiconductor integrated circuit in which a digital circuit and an analog circuit are integrated on a single substrate, A substrate including a region where the digital circuit is to be formed and a region where the analog circuit is to be formed; A deep-well formed to a predetermined depth in the substrate to surround a region where elements of the digital circuit are to be formed or a region where the elements of the analog circuit are to be formed; And A plurality of device isolation layers respectively formed between the elements of the analog circuit and the elements of the digital circuit, and formed to have different depths from an upper surface of the substrate Semiconductor integrated circuit comprising a. The method of claim 1, The semiconductor integrated circuit further comprises elements of an RF (Radio Frequency) circuit formed on the substrate. The method of claim 2, And the elements of the RF circuit are formed to be surrounded by the deep-well. The method according to claim 1 or 3, And the deep-well is an n-well or p-well. The method of claim 1, And the devices of the analog circuit include a plurality of devices having different operating ranges. The method of claim 1, And the devices of the digital circuit include a plurality of devices having different operating ranges. delete The method according to claim 5 or 6, Devices having different operating ranges, A first element having a first operating range; A second element having a second operating range higher than the first operating range; And A third device having a third operating range higher than the second operating range Semiconductor integrated circuit comprising a. The method of claim 8, The first operating range is 1 ~ 10V semiconductor integrated circuit. The method of claim 8, The second operating range is 10 ~ 30V semiconductor integrated circuit. The method of claim 8, The third operating range is 30 ~ 50V semiconductor integrated circuit. The method of claim 8, The devices having different operating ranges further include a fourth device having a fourth operating range higher than the third operating range. The method of claim 12, The fourth operating range is 50 ~ 900V semiconductor integrated circuit. The method of claim 8, The device isolation layer for separating and isolating the first device of the plurality of device isolation layer is formed 0.1 ~ 1㎛ depth from the upper surface of the substrate. The method of claim 8, The device isolation film for separating and isolating the second device of the plurality of device isolation film is formed to a depth of 1 ~ 3㎛ from the upper surface of the substrate. The method of claim 8, And a device isolation layer for separating and isolating the third device from among the plurality of device isolation layers is 3 to 50 μm deep from an upper surface of the substrate. The method of claim 8, The plurality of device isolation layers may be formed in a structure in which an insulating film is buried in the substrate in a trench form. The method of claim 8, The plurality of device isolation layers are formed through a stack implant process using O ₂ ions in the substrate. The method of claim 1, Elements of the digital circuit include ST-LDMOS (Shallow Trench Isolation-LDMOS), MT-LDMOS (Medium Trench Isolation-LDMOS), DT-LDMOS (Deep Trench Isolation-LDMOS), and HV-LDMOS (High Voltage Well-LDMOS) devices. Semiconductor integrated circuit comprising a. The method of claim 19, The HV-LDMOS device is formed to be surrounded by a high voltage well. The method of claim 20, And the high voltage well is an n-well or p well. The method of claim 20, The high voltage well is formed by implanting impurity ions to a predetermined depth from an upper surface of the substrate and then diffusing the implanted impurity ions through a drive-in process. The method of claim 22, The implanted impurity ions are implanted to a depth of 1 ~ 3㎛ from the upper surface of the substrate. The method of claim 22, The drive-in process is a semiconductor integrated circuit is carried out for 2 to 15 hours at a temperature of about 1000 to 1200 ℃. The method of claim 1, The device of the analog circuit includes at least one of a Bipolar Junction Transistor (BJT), a Complementary Metal Oxide Semiconductor (CMOS) device and a Hetero Junction Bipolar Transistor (HBT). The method of claim 25, The bipolar junction transistor (BJT), A collector formed to a predetermined depth in the substrate; An emitter formed in the substrate to be spaced apart from the collector; And A base formed between the collector and the emitter Semiconductor integrated circuit comprising a. The method of claim 26, And the collector is formed at the same concentration and depth as the deep-well. The method of claim 26, And the collector is formed to a depth lower than the top surface of the substrate than the deep-well formed to surround neighboring elements of the analog circuit. The method of claim 25, The hetero junction bipolar transistor (HBT) A collector formed to a predetermined depth in the substrate; A base formed on the upper surface of the substrate; And An emitter formed on the base Semiconductor integrated circuit comprising a. The method of claim 29, And the collector is formed at the same concentration and depth as the deep-well. The method of claim 29 or 30, The collector is a semiconductor integrated circuit formed by a stack implant (stack implant) process.

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