KR102081225B1 - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

Disclosed are a semiconductor device in which various functional elements are integrated on a single substrate, and a manufacturing method thereof. An improved semiconductor device according to the embodiment includes an SOI substrate having a first semiconductor layer, a buried insulating layer, and a second semiconductor layer stacked thereon; A first region in which a plurality of high density transistors having the second semiconductor layer as an active layer are formed; And a second region having the buried insulating layer as a gate insulating layer and a plurality of high voltage transistors having the first semiconductor layer as an active layer.

Description

Semiconductor device and method of manufacturing the same

Disclosed is a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device and a method for manufacturing the same, including an inductor for an RF device, a power management IC (PMIC), and a high density logic device. will be.

Due to the improvement in the integration of semiconductor devices and the development of manufacturing design techniques, various attempts have been made to integrate a plurality of devices having various functions into one chip. The one-chipization of the system that directly transfers the system formed on a printed circuit board (PCB) onto a single semiconductor is called a som-on-a-chip (SOC), and it refers to a product that includes a fully driveable product on one chip. . It has been developed to integrate other low voltage circuits such as controller and memory into one chip.

In recent years, RF CMOS technology has been developed due to the use of wireless communication terminals. The wireless communication terminal may use the RF switch circuit to change the transmission path of the high frequency signal, the RF switch circuit may be composed of an RF switch for changing the signal path and a controller for controlling it. Such RF switch circuits are gradually increasing RF switch circuits manufactured by CMOS processes. A research focus shift has been made to highly integrated and wide variety of CMOS system-on-a-chip (SOC) technologies that integrate all wireless mixed-signal systems on a single chip.

Thus, the current system-on-a-chip (SOC) implements a conventional semiconductor element such as a CMOS and an RF circuit element as one chip. After forming the semiconductor wiring on the substrate, the inductor is placed on top of the semiconductor wiring. Will be produced.

In addition, in the SOC (Sytem-On-a-Chip), the circuit part for controlling the power of the system, that is, the circuit having the main functions of the input terminal and the output terminal, must be one-chip. Since the input terminal and the output terminal are circuits to which a high voltage is applied, they cannot be constituted by general low voltage CMOS circuits, and thus are constituted by high voltage power transistors. The technology that makes this possible is a PMIC (Power management IC), which implements a Lateral DMOS (LDMOS) device that enables high voltage breakdown by placing a drift region between the channel and the drain.

The problem addressed by the inventions of the described embodiments is to provide a semiconductor device and a method for manufacturing the same, in which elements of various functions are integrated on a single substrate.

In an embodiment, a semiconductor device may include an SOI substrate on which a first semiconductor layer, a buried insulating layer, and a second semiconductor layer are stacked; A first transistor having the second semiconductor layer as an active layer; And a second transistor having the buried insulating layer as a gate insulating layer and having the first semiconductor layer as an active layer.

A semiconductor device according to another embodiment of the present invention includes an SOI substrate having a first semiconductor layer, a buried insulating layer, and a second semiconductor layer stacked thereon; A first region in which a plurality of high density transistors having the second semiconductor layer as an active layer are formed; And a second region having the buried insulating layer as a gate insulating layer and having a plurality of high voltage transistors having the first semiconductor layer as an active layer.

In accordance with still another aspect of the present invention, a semiconductor device includes: an SOI substrate having a first semiconductor layer, a buried insulating layer, and a second semiconductor layer stacked thereon; A high voltage transistor having the buried insulating layer as a gate insulating layer and having the first semiconductor layer as an active layer; An inductor formed on the second semiconductor layer; And an air gap formed in the first semiconductor layer on the rear surface of the substrate facing the inductor.

In accordance with still another aspect of the present invention, a semiconductor device includes: an SOI substrate having a first semiconductor layer, a buried insulating layer, and a second semiconductor layer stacked thereon; A high density transistor having the second semiconductor layer as an active layer; An inductor formed on the second semiconductor layer; And an air gap formed in the first semiconductor layer on the rear surface of the substrate facing the inductor.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes providing an SOI substrate on which a first semiconductor layer, a buried insulating layer, and a second semiconductor layer are stacked; Removing the second semiconductor layer to expose the buried insulating layer in a first region; Performing a thermal process to cure the buried insulating layer in the first region and to form a gate insulating layer on the second semiconductor layer in the second region; Forming a first gate on the buried insulating layer of the first region, and forming a second gate on the second gate insulating layer of the second region; Forming a first source / drain region in the first semiconductor layer under the first gate side, and forming a second source / drain region in the second semiconductor layer under the second gate side, A high voltage transistor may be formed in the first region, and a high density transistor may be formed in the second region.

The improved semiconductor device of the embodiment efficiently integrates various functional devices such as RF inductors, high density logic devices, and power management ICs (PMICs) into one wafer.

1 is a cross-sectional view illustrating an improved semiconductor device in accordance with an embodiment.
2 through 9 are process cross-sectional views illustrating an improved method of manufacturing a semiconductor device.

In the description of an embodiment, each layer (or film), region, pattern, or structure is “on” or “under” the substrate, each layer (film), region, pad, or pattern. In the case of being described as being formed "in", "upper / up" and "lower / lower" include both "directly" or "indirectly" formed.

In addition, the reference to the top / top or bottom / bottom of each layer is a reference to the drawings. In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description.

Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings. Embodiments described are directed to an improved semiconductor device in which an RF inductor, a PMIC (Power Management IC) and a High Density Logic device are integrated.

1 is a cross-sectional view illustrating an improved semiconductor device in accordance with an embodiment.

Referring to FIG. 1, an improved semiconductor device includes a first region A in which a first transistor 100, which is a high density logic device, is formed, a second region B, in which an RF inductor is formed, and It may be divided into a third region C in which the second transistors 200 and 300 serving as a power management IC (PMIC) are formed.

In addition, the improved semiconductor device may be fabricated based on a substrate on which the first semiconductor layer 10, the buried insulating layer 20, and the second semiconductor layer 30 are stacked, for example, a silicon on insulator (SOI) substrate. . In addition, the first semiconductor layer 10 may have a structure in which a low concentration epitaxial layer (P− Epi.) Is grown on, for example, a heavily doped P + substrate (P + Sub.).

The first region A is a first fabricated based on a substrate on which the first semiconductor layer 10, the buried insulating layer 20, and the second semiconductor layer 30 are stacked, for example, a silicon on insulator (SOI) substrate. The transistor 100 may be included. The first transistor 100 may have the second semiconductor layer 30 as an active layer. That is, the source / drain regions 130A and 130B and the channel region 130C of the first transistor 100 may be configured in the second semiconductor layer 30. The gate insulating layer 120 may be formed on the second semiconductor layer 30, and the gate 110 of the first transistor 100 may be formed on the second semiconductor layer 30.

In addition to the first transistor 100, other transistors may be further formed in the first region A. FIG. Therefore, the device isolation layer 55 may be formed in the first region A. FIG. The device isolation layer 55 may be connected to the buried insulating layer 20 through the second semiconductor layer 30. As a result, a Fully Depleted SOI (FD-SOI) technology in which a body of the first transistor 100 is completely separated from other elements adjacent to each other in the first region A may be applied. Fully Depleted SOI (FD-SOI) technology can eliminate the short channel effect, thereby reducing the channel length, which is advantageous for implementing a high density logic device. This short channel effect is because the channel depth is small and all the channels are depleted so that the charge sharing effect due to the junction does not occur.

The second region B may be an inductor fabricated based on a substrate on which the first semiconductor layer 10, the buried insulating layer 20, and the second semiconductor layer 30 are stacked, for example, a silicon on insulator (SOI) substrate. 440). The RF inductor 440 may form an interlayer insulating layer 77 on the second semiconductor layer 30, and may be formed on the interlayer insulating layer 77. The RF inductor 440 may be formed of a thick metal layer.

In general, inductors increase the loss of RF and severe degradation of passive circuit components due to the silicon substrate's conductivity. This is due to the eddy current caused by inductance, and a semiconductor substrate having a high resistance is required to prevent this. In order to satisfy this, the improved semiconductor device may have an air gap 66 on the back side of the substrate of the inductor 440. That is, the air gap 66 may be formed in the first semiconductor layer 10 on the rear surface of the substrate facing the inductor 440. The air gap 66 may be configured in a space in which the P + substrate P + Sub. And the low concentration epi layer are etched.

In the third region C, second transistors 200 and 300 for high voltage and high current having a relatively thick gate insulating layer are formed. Therefore, the buried insulating layer 20 may be used as the gate insulating layers 220 and 320 of the second transistors 200 and 300. To this end, the second semiconductor layer 30 may be removed in the third region (C). In addition, the second transistors 200 and 300 may have a low concentration epitaxial layer of the first semiconductor layer 10 as an active layer. That is, the source / drain regions 230A, 230B, 330A, and 330B and the channel region of the second transistors 200 and 300 may be configured in the low concentration epitaxial layer P-Ep. Gates 210 and 310 of each transistor may be formed on the gate insulating layers 220 and 320. The low concentration epitaxial layer (P-Epi) serves to suppress noise caused by the high voltage of the second transistors 200 and 300.

Device isolation layers 56 and 57 may be formed in the low concentration epitaxial layer (P− Epi). In the second transistor 300, the gate 310 may overlap a portion of the device isolation layer 57, and a drift junction 88 may be formed under the device isolation layer 57. The drift junction 88 is used to form the second transistor 300 as a high voltage transistor (LDMOS), which forms a device isolation film 57 by an STI process in the active region, and drains 330B. ) Is positioned horizontally, and the drift junction 88 is positioned between the channel and the drain. The buried insulating layer 20 is commonly located in the first region A, the second region B, and the third region C. FIG. The buried insulating layer 20 is used to implement the FD-SOI technology for the short channel effect in the first region A, and is used as an etch stop layer when the air gap 66 is formed in the second region B. In the third region C, the gate insulating layers 220 and 320 are used.

2 through 9 are cross-sectional views illustrating a process of an improved semiconductor device in accordance with an embodiment.

Referring to FIG. 2, a substrate on which the first semiconductor layer 10, the buried insulating layer 20, and the second semiconductor layer 30 are stacked is prepared. In this case, the first semiconductor layer 10 may have a structure in which a low concentration epi layer is formed on a high concentration P + substrate (P + sub.).

The buried insulating layer 20 may be 30 nm or less, and the second semiconductor layer 30 may be a thin semiconductor thin film of 20 nm or less, and preferably, the second semiconductor layer 30 is about 10 nm thick. It may have a thickness.

Fully Depleted SOI (FD-SOI) substrate means a fully depleted SOI substrate where the depletion layer reaches the buried insulating layer 20 of the silicon-on-insulator (SOI) substrate, and the gate length of the field effect transistor is 100 nm. Even if it is below, the short channel effect can be suppressed and a drain current can be ensured even at low operating voltage, and the board | substrate density can be made low. Therefore, since the fall of the carrier mobility accompanying the increase of impurity scattering is suppressed, high drive current can be attained.

Subsequently, as illustrated in FIG. 3, the drift junction 88 and the device isolation layers 56 and 57 may be formed in the third region C. Referring to FIG. In this case, the drift junction 88 may be formed before the device isolation layers 56 and 57 so that wafer distortion does not occur. The device isolation layers 56 and 57 may be formed through the buried insulating layer 20 to a depth of 2000 to 4000 micrometers. The drift junction 88 may be formed to have a depth surrounding the device isolation layer 57. This is to form a lateral diffusion MOS (LDMOS) for the second transistor 300 to be used for high volatility (HV), and form a device isolation film 57 by an STI process in the active layer to form a drain 330B. Placed horizontally, the drift region 88 is positioned between the channel and the drain.

In addition, annealing for forming the drift junction 88 is performed before forming the STI so that distortion of the wafer does not occur. In this case, the drift junction 88 may be formed by implanting N-type impurity ions, for example, phosphorus (P) ions, and then performing an impurity diffusion process .

Subsequently, as shown in FIG. 4, an isolation layer 55 may be formed in the first region A. FIG. The device isolation layer 55 may contact the buried insulating layer 20 through the second semiconductor layer 30. Formation of the device isolation film 55 is preferably formed at a depth of 200 ~ 400Å. Thereafter, the second semiconductor layer 30 may be removed to expose the surface of the buried insulating layer 20 in the third region C. FIG. Meanwhile, when the device isolation layers 55, 56, and 57 are formed first, and then the second semiconductor layer 30 is removed from the third region C, damage and contamination of the buried insulating layer 20 may be minimized. The buried insulating layers of three regions may be used as the gate insulating layers 220 and 320 of the second transistors 200 and 300.

Referring to FIG. 5, the gate insulation layer 120 may be formed in the first region A and the second region B by thermally oxidizing the resultant product of FIG. 4. In this case, the buried insulating layer 20 in the third region C may have an effect of curing surface damage. Subsequently, the gate electrodes 110, 210, and 310 may be formed by depositing and patterning a conductive layer such as a polysilicon film.

6 shows a state in which source / drain regions and spacers are formed. Referring to FIG. 6, in forming a lightly doped drain (LDD), first, an LDD of the second transistors 200 and 300 may be formed first and then rapidly thermally processed, and then an LDD of the first transistor 100 may be formed. This is to minimize the thermal budget on the first transistor 100 during the rapid heat treatment. Thereafter, spacers may be formed on sidewalls of the gates 110, 210, and 310, and then source / drain ion implantation may be performed to form source / drain regions 130A, 130B, 230A, 230B, 330A, and 330B.

Referring to FIG. 7, an interlayer insulating layer 77, for example, an inter-metallic dielectric (IMD) and an inter-layer dielectric (ILD) may be formed on the resultant of FIG. 8. The interlayer insulating layer 77 uses insulating materials having excellent gap fill characteristics, and may include, for example, a high density plasma (HDP) oxide film, TetraEthylOrthoSilicate (TEOS), Plasma Enhanced TetraEthylOrthoSilicate (PE-TEOS), and O3-TEOS (O3-Tetra Ethyl). Ortho Silicate, Undoped Silicate Glass (USG), PhosphoSilicate Glass (PSG), Borosilicate Glass (BSG), BoroPhosphoSilicate Glass (BPSG), Fluoride Silicate Glass (FSG), Spin On Glass (SOG), or Tonen SilaZene (TOSZ) Can be. Or a combination thereof may be used and may be formed using a chemical vapor deposition (CVD) method, a spin coating method, or the like.

Referring to FIG. 8, an inductor 440 may be formed on the interlayer insulating layer 77 of the second region B. Referring to FIG. The inductor may be formed of a thick metal having a thickness of several um or more.

Next, referring to FIG. 9, an air gap 66 is formed on the rear surface of the substrate of the second region B. Referring to FIG. The buried insulating layer 20 may be formed by back-side etching using the etch stop layer. Etching to form the air gap 66 may be performed through conventional wet or dry etching processes. In order to completely remove the insulating material remaining after the etching process, a cleaning process may be additionally performed as necessary. As a dry etching method, a reactive ion etching (RIE) method may be used. As a preferred embodiment, a wet etching method may be used in etching for an air gap, and an anisotropic wet etching solution such as KOH (potassium hydroxide), TMAH (tetramethyl ammonium hydroxide) or EDP (ethylene diannmine pyrocatechol) may be used.

On the other hand, for mechanical strength of the structure, the air gap 66 may be gapfilled with a dielectric material, in particular with a low dielectric constant material. Material dielectric siloxane resins, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, PSG (phosphorus glass), BPSG (phosphorus boron glass), alumina, etc. having a low dielectric constant may also be used. As the forming method, plasma enhanced CVD (PECVD), high density plasma CVD (HDP-CVD), atmospheric pressure CVD (APCVD), spin on deposition (SOD) spin coat, or the like may be used, depending on the material.

An improved semiconductor device of an embodiment includes a first region A in which a high density transistor such as a memory cell is formed, a third region C in which a high voltage, high current transistor is formed, and a second region B in which an RF inductor is formed. Has However, only at least two of the first region A, the second region B, and the third region C may be included. That is, the improved semiconductor device may have only the high density transistor of the first region A and the high voltage transistor of the third region C. FIG. In addition, the improved semiconductor device may have only a high density transistor in the first region A and an inductor in the second region B. FIG. In addition, the improved semiconductor device may have only an inductor in the second region B and a high voltage transistor in the third region C. FIG.

Features, structures, effects, and the like described in the above embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, and the like illustrated in each embodiment may be combined or modified with respect to other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be interpreted that the contents related to such a combination and modification are included in the scope of the present invention.

100: first transistor (high density transistor)
200, 300: second transistor (high voltage transistor)
440: Inductor
10: first semiconductor layer
20: buried insulation layer
30: second semiconductor layer

Claims (19)

An SOI substrate including a first region in which a first semiconductor layer, a buried insulating layer, and a second semiconductor layer are stacked, and a second region in which the first semiconductor layer and a buried insulating layer are stacked;
A first transistor formed in the first region and having the second semiconductor layer as an active layer;
A second transistor formed in the second region and having the buried insulating layer and the first semiconductor layer as a gate insulating layer and an active layer, respectively;
A first device isolation layer penetrating the second semiconductor layer in the first region and connected to the buried insulating layer;
A second device isolation layer formed through the buried insulating layer in the second region to a depth of the first semiconductor layer; And
A drift junction formed in the second region and surrounding the second device isolation layer
A semiconductor device comprising a.
The method of claim 1,
An inductor formed on the second semiconductor layer; And
And an air gap formed in the first semiconductor layer behind the SOI substrate opposite the inductor.
The method of claim 1,
The first semiconductor layer has a structure in which a low concentration epitaxial layer is formed on a high concentration layer.
An SOI substrate including a first region in which a first semiconductor layer, a buried insulating layer, and a second semiconductor layer are stacked, and a second region in which the first semiconductor layer and a buried insulating layer are stacked;
A plurality of high density transistors formed in the first region and having the second semiconductor layer as an active layer;
A plurality of high voltage transistors formed in the second region and each of the buried insulating layer and the first semiconductor layer as a gate insulating layer and an active layer;
A first device isolation layer penetrating the second semiconductor layer in the first region and connected to the buried insulating layer;
A second device isolation layer penetrating the buried insulating layer in the second region; And
A drift junction formed in the second region and surrounding the second device isolation layer
A semiconductor device comprising a.
delete delete The method of claim 4, wherein
And a third region having an air gap formed in the first semiconductor layer and having an inductor formed on the second semiconductor layer. The method of claim 4, wherein
The first semiconductor layer has a structure in which a low concentration epitaxial layer is formed on a high concentration layer.
Providing an SOI substrate comprising a first semiconductor layer, a buried insulating layer, and a second semiconductor layer stacked thereon, the first semiconductor layer comprising a first region and a second region;
Forming a drift junction in the first region;
Forming a first device isolation layer in the first region, penetrating the second semiconductor layer and the buried insulating layer to a depth of a portion of the first semiconductor layer;
Forming a second device isolation layer in the second region through the second semiconductor layer to be connected to the buried insulating layer;
Removing the second semiconductor layer from the first region to expose the buried insulating layer;
Performing a thermal process to cure the buried insulating layer in the first region and to form a gate insulating layer on the second semiconductor layer in the second region;
Forming a first gate on the buried insulating layer of the first region, and forming a second gate on the gate insulating layer of the second region;
Forming a first source / drain region in the first semiconductor layer under the first gate side, and forming a second source / drain region in the second semiconductor layer under the second gate side;
A high voltage transistor is formed in the first region, and a high density transistor is formed in the second region.
delete The method of claim 9,
The SOI substrate further includes a third region,
Forming an inductor on the second semiconductor layer in the third region; And
And forming an air gap in the first semiconductor layer on the backside of the SOI substrate facing the inductor.
The method of claim 11,
Forming the air gap,
And etching the first semiconductor layer from the backside of the SOI substrate using the buried insulating layer as an etch stop layer. The method of claim 12,
Etching for forming the air gap is a semiconductor device manufacturing method using a tetramethyl ammonium hydroxide (TMAH), ethylene diannmine pyrocatechol (EDP) or KOH (potassium hydroxide) solution.
The method of claim 9,
The first semiconductor layer has a structure in which a low concentration epitaxial layer is formed on a high concentration layer.
delete delete delete delete delete

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