CN104241281B - A kind of integrated circuit and its manufacture method - Google Patents
A kind of integrated circuit and its manufacture method Download PDFInfo
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- CN104241281B CN104241281B CN201310243253.7A CN201310243253A CN104241281B CN 104241281 B CN104241281 B CN 104241281B CN 201310243253 A CN201310243253 A CN 201310243253A CN 104241281 B CN104241281 B CN 104241281B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
Abstract
The present invention provides a kind of integrated circuit and its manufacture method, is related to technical field of semiconductors.The integrated circuit of the present invention, by using the first group transistor, the second group transistor, the 3rd group transistor of different lateral, and the component such as integrated passive devices and MEMS, it is integrated into by wafer work flow on one chip, relative to the existing RF front-end module by made by system Integration in Package, with higher signal to noise ratio, lower power consumption, smaller device size and lower cost.The manufacture method of the integrated circuit of the present invention, for manufacturing said integrated circuit, while obtained integrated circuit has above-mentioned advantage, can reduce the complexity and manufacturing cost of final RF front-end module encapsulation.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of integrated circuit and its manufacture method.
Background technology
In technical field of semiconductors, RF front-end module(Radio Frequency Frond-EndModule, referred to as
RF FEM)It is Wireless Telecom Equipment(Such as mobile phone, tablet personal computer)In key component.In the prior art, radio-frequency front-end
Module(RF FEM)Generally pass through system in package by multiple different chips(SiP)Realize.In general, RF front-end module
(RF FEM)Generally include power amplifier core(Power amplifier core), power amplifier controller(PA
controller), tuner(Tuners), RF switch(RFswitch), wave filter(Filters), duplexer
(Duplexer)Etc. different chips and including envelope detected(envelope tracking)Other chips including chip.Its
In, power amplifier core generally uses GaAs(GaAs)Chip or high voltage(HV)And power(POWER)Complementary metal
Oxide semiconductor(CMOS)Chip;Power amplifier controller generally uses CMOS chip, and tuner generally uses radio frequency
CMOS chip, RF switch generally uses silicon-on-insulator mos field effect transistor(SOI MOS), filtering
Device generally uses radio frequency integrated passive devices(RF IPD), duplexer is generally using MEMS(MEMS), and other chips
(Such as envelope detected chip)Generally use CMOS chip.
However, in the prior art, RF front-end module(RF FEM)Due to passing through system-level by multiple different chips
Encapsulation(SiP)Obtain, the interconnection of each chip chamber in system in package, often using terminal conjunction method(Wire bonding)Come real
It is existing.Therefore, existing RF front-end module(RF FEM)With module size is big, signal to noise ratio(SNR)It is low, the shortcomings of power consumption is big.
In addition, the method for manufacture RF front-end module(That is, system-in-a-package method)Often there is process complexity height, cost height etc. to lack
Point.
Therefore, in order to solve the above problems, the present invention proposes a kind of new integrated circuit and its manufacture method.
The content of the invention
In view of the shortcomings of the prior art, the present invention provides a kind of integrated circuit and its manufacture method, real by one chip
Existing RF front-end module of the prior art(RF FEM)Part or all of function.
The embodiment of the present invention one provides a kind of integrated circuit, a kind of integrated circuit, it is characterised in that including:The first half lead
Body substrate, respectively positioned at the of the first area of first surface of first Semiconductor substrate, second area and the 3rd region
One group transistor, the second group transistor and the 3rd group transistor and on the second surface of first Semiconductor substrate
First body dielectric layer, wherein,
By positioned at described the first half between each transistor in first group transistor of the first area
First group of shallow trench in conductor substrate is isolated, wherein first group of shallow trench isolation is close to first semiconductor
The distance of the first surface of the side of the second surface of substrate away from first Semiconductor substrate is the first distance;
By positioned at described the first half between each transistor in second group transistor of the second area
First group of deep trench isolation in conductor substrate is isolated, wherein first group of deep trench isolation is close to first semiconductor
The distance of the first surface of the side of the second surface of substrate away from first Semiconductor substrate is second distance;
By positioned at the first semiconductor between each transistor in the 3rd group transistor in the 3rd region
Second group of shallow trench in substrate is isolated, wherein second group of shallow trench isolation is close to first Semiconductor substrate
The second surface the first surface of the side away from first Semiconductor substrate distance be first distance;
Wherein, the second distance is more than first distance, and the second distance is less than or equal to described first
The thickness of Semiconductor substrate.
Wherein, first group transistor is low voltage mos transistor, and second group transistor is high-voltage MOS transistor.
Further, second group transistor is laterally diffused MOS transistor.
Wherein, the 3rd group transistor is complete depletion type MOS transistor.
Wherein, the first body dielectric layer is also included positioned at the 4th region and the 5th region of first Semiconductor substrate
Part, wherein, the first body dielectric layer be located at first Semiconductor substrate the 4th region and the 5th region part
Through first Semiconductor substrate.
Wherein, the integrated circuit also includes the four-range silicon hole positioned at first Semiconductor substrate, described
Silicon hole is located at the four-range part of first Semiconductor substrate through the first body dielectric layer.
Wherein, the integrated circuit also includes being located at the first body dielectric layer is located at first Semiconductor substrate the
The integrated passive devices of the top of the part in five regions.
Wherein, the integrated passive devices include electric capacity and/or inductance.
Wherein, the integrated circuit also includes being arranged at the first body dielectric layer positioned at first Semiconductor substrate
The MEMS of the top of the part in four-range part and/or the 5th region(MEMS)Device.
Wherein, the integrated circuit is also included positioned at first group transistor, second group transistor and described the
MEMS above or below three group transistors are at least one of(MEMS)Device.
Wherein, the integrated circuit also includes the conduct carrying lining on the first surface of first Semiconductor substrate
Second Semiconductor substrate at bottom, also, the integrated circuit is also micro electronmechanical in second Semiconductor substrate including being arranged at
System(MEMS)Device.
The embodiment of the present invention two provides a kind of manufacture method of integrated circuit, and methods described includes:
Step S101:The first Semiconductor substrate is provided, in the first area and the 3rd region of first Semiconductor substrate
First group of shallow trench isolation and second group of shallow trench isolation are formed respectively, are formed in the second area of first Semiconductor substrate
First group of deep trench isolation, wherein, first group of shallow trench isolation is close to first Semiconductor substrate and described first
The distance of the first surface of the side of the relative second surface in surface away from first Semiconductor substrate is the first distance, institute
Second group of shallow trench isolation is stated close to the side of the second surface of first Semiconductor substrate away from first semiconductor
The distance of the first surface of substrate is first distance, and first group of deep trench isolation is close to first semiconductor
The distance of the first surface of the side of the second surface of substrate away from first Semiconductor substrate is second distance, institute
Second distance is stated more than first distance;
Step S102:Form respectively in the first area of first Semiconductor substrate, second area and the 3rd region
One group transistor, the second group transistor and the 3rd group transistor, wherein, first group transistor, the second group transistor and
Three group transistors are respectively positioned on the first surface side of first Semiconductor substrate;
Step S103:The first body dielectric layer, first body are formed on the second surface of first Semiconductor substrate
Dielectric layer is located at first area, the part of second area and the 3rd region and the first surface of first Semiconductor substrate
Distance it is identical.
Wherein, first group transistor is low voltage mos transistor, and second group transistor is high-voltage MOS transistor.
Further, second group transistor is laterally diffused MOS transistor.
Wherein, the 3rd group transistor is complete depletion type MOS transistor.
Wherein, step S1023 is also included between the step S102 and the step S103:
Back-end process technique is carried out with the first surface of first Semiconductor substrate formation metal interconnection structure.
Wherein, also comprise the following steps between the step S1023 and the step S103:
Step S10231:In the first surface engagement of first Semiconductor substrate as carrying the second the half of substrate
Conductor substrate;
Step S10232:Reduction processing is carried out to the second surface of first Semiconductor substrate to cause place is thinned
The distance of first surface of the second surface of the first Semiconductor substrate after reason away from first Semiconductor substrate is the 3rd distance,
3rd distance is more than or equal to the second distance.
Wherein, in the step S101, first group of shallow trench isolation, second group of shallow trench isolation are being formed
Before first group of deep trench isolation, the institute away from first Semiconductor substrate is formed in first Semiconductor substrate
The distance for stating first surface is the thinned stop-layer of the 3rd distance;In the step S10232, the reduction processing is stopped
Terminate on the thinned stop-layer.
Wherein, the step of forming the thinned stop-layer includes:From the second surface of first Semiconductor substrate
Non- Si ion implantation is carried out to first Semiconductor substrate with the shape at the second depth location of first Semiconductor substrate
Into non-silicon sheath, wherein the non-silicon ion includes oxonium ion, carbon ion, Nitrogen ion or at least both groups among them
Close.
Wherein, the step of the formation non-silicon sheath after also include, first Semiconductor substrate is carried out high
The step of temperature processing.
Wherein, in the step S103, the first body dielectric layer also includes the 4th positioned at the Semiconductor substrate
Region and the part in the 5th region, also, the step S103 includes:
Step S1031:First Semiconductor substrate is performed etching, with the 4th area of first Semiconductor substrate
Domain and the 5th region form the first groove through first Semiconductor substrate through reduction processing;
Step S1032:Filled dielectric material and carry out planarization process in the first groove, with formed be located at it is described
First area, second area, the 3rd region, the first body dielectric layer in the 4th region and the 5th region.
Wherein, step S104 is also included after the step S103:
Silicon hole is formed in the 4th region of first Semiconductor substrate, the silicon hole runs through the first body dielectric
Layer is located at the four-range part of first Semiconductor substrate.
Wherein, step S105 is also included after the step S104:
The top for being located at the part in the 5th region of first Semiconductor substrate in the first body dielectric layer forms collection
Into passive device.
Wherein, the integrated passive devices include electric capacity and/or inductance.
Wherein, step S104 ' is also included after the step S103:
It is located at the four-range part and/or the 5th region of first Semiconductor substrate in the first body dielectric layer
Part top formed MEMS(MEMS)Device.
Wherein, step S104 ' ' is also included after the step S103:
First group transistor, second group transistor and the 3rd group transistor it is at least one of on
It is square into MEMS(MEMS)Device.
Wherein, in the step S10231, MEMS is formed with second Semiconductor substrate(MEMS)Device
Part.
The integrated circuit of the present invention, with passing through the RF front-end module made by system Integration in Package in the prior art
(RF FEM)Compare, with higher signal to noise ratio(SNR), lower power consumption, smaller device size and lower cost.This
The manufacture method of the integrated circuit of invention, can reduce encapsulation complexity and manufacturing cost, also, according to manufactured by this method
Integrated circuit, compared with RF front-end module of the prior art, has the advantages that signal to noise ratio is high, low in energy consumption, device size is small.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.
In accompanying drawing:
Figure 1A is a kind of a kind of schematic cross sectional views of the structure of integrated circuit of the embodiment of the present invention one;
Figure 1B is a kind of another schematic cross sectional views of the structure of integrated circuit of the embodiment of the present invention one;
The figure that Fig. 2A to 2J is formed for a kind of correlation step of the manufacture method of integrated circuit of the embodiment of the present invention two
Schematic cross sectional views;
Fig. 3 is a kind of a kind of indicative flowchart of the manufacture method of integrated circuit of the embodiment of the present invention two;
Fig. 4 is a kind of another indicative flowchart of the manufacture method of integrated circuit of the embodiment of the present invention two.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And, it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that be referred to as when element or layer " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or when " being directly coupled to " other elements or layer, then in the absence of element or layer between two parties.Although it should be understood that can make
Various elements, part, area, floor and/or part are described with term first, second, third, etc., these elements, part, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish element, part, area, floor or part with it is another
One element, part, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, portion
Part, area, floor or part are represented by the second element, part, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., can describe for convenience herein and by using so as to the element or feature shown in description figure with
The relation of other elements or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term is intended to also include making
With the different orientation with the device in operation.If for example, the device upset in accompanying drawing, then, is described as " under other elements
Face " or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated and (be rotated by 90 ° or it
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, " one " and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determine the feature, it is whole
Number, step, operation, the presence of element and/or part, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, part and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
Hair is described herein with reference to the cross-sectional view of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Bright embodiment.As a result, it is contemplated that due to the change caused by such as manufacturing technology and/or tolerance from shown shape.Therefore,
Embodiments of the invention should not necessarily be limited to the given shape in area shown here, but including due to for example manufacturing caused shape
Shape deviation.For example, being shown as that the injection region of rectangle generally has circle at its edge or bending features and/or implantation concentration ladder
Degree, rather than the binary change from injection region to non-injection regions.Equally, the disposal area can be caused by injecting the disposal area formed
Some injections in area between the surface passed through during injection progress.Therefore, the area shown in figure is substantially schematic
, their shape is not intended the true form in the area of display device and is not intended to limit the scope of the present invention.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Explain integrated circuit proposed by the present invention and its manufacture method.Presently preferred embodiments of the present invention is described in detail as follows, but except
Outside these are described in detail, the present invention can also have other embodiment.
Embodiment one
Below, reference picture 1A and Figure 1B come describe the embodiment of the present invention proposition integrated circuit structure.Wherein, Tu1AWei
A kind of a kind of schematic cross sectional views of the structure of integrated circuit of the embodiment of the present invention, Figure 1B is one kind of the embodiment of the present invention one
Another schematic cross sectional views of the structure of integrated circuit.
The present embodiment provides a kind of integrated circuit, its can as the communication equipments such as mobile phone RF front-end module(RF
FEM).As shown in Figure 1A, the integrated circuit of the present embodiment includes:First Semiconductor substrate 100, positioned at the first Semiconductor substrate
The first body dielectric layer 1001 on 100 and the first group transistor 1102 positioned at the first area of the first Semiconductor substrate 100,
The second group transistor 1202 positioned at the second area of the first Semiconductor substrate 100 and positioned at the first Semiconductor substrate 100
3rd group transistor 1302 in three regions.Wherein, the first group transistor 1102 is core MOS transistor(Core MOS), typically
For low voltage mos transistor, the second group transistor 1202 is high-voltage MOS transistor(HV MOS), the 3rd group transistor 1302 is complete
Depletion-type mos transistor(FD MOS).Further, the second group transistor is ldmos transistor(That is, laterally diffused MOS crystal
Pipe).In the present embodiment, the first group transistor 1102, the second group transistor 1202 and the 3rd group transistor 1302 include many
Individual transistor, it is brief for expression, it schematically show only one per group transistor in figure ia.Wherein, the 3rd group of crystalline substance
Body pipe 1302 can be silicon-on-insulator(SOI)Transistor.
In the present embodiment, by positioned at the first Semiconductor substrate between each transistor in the first group transistor 1102
100 first area and first group of shallow trench isolation with the first depth H 1(STI)1101 are isolated, and bottom is situated between by the first body
The part that electric layer 1001 is located at the first area is isolated;Between each transistor in second group transistor 1202 by positioned at
The second area of first Semiconductor substrate 100 and first group of deep trench isolation with the second depth H 2(DTI)1201 are isolated,
The part that bottom is located at the second area by the first body dielectric layer 1001 is isolated;It is each in 3rd group transistor 1302
Between individual transistor by positioned at the 3rd region of the first Semiconductor substrate 100 and with the first depth H 1 second group of shallow trench every
From(STI)1301 are isolated, and the part that bottom is located at the 3rd region by the first body dielectric layer 1001 is isolated.At this
In embodiment, the second depth H 2 is more than the first depth H 1, and the second depth H 2 is less than or equal to the thickness of the first Semiconductor substrate 100
Degree.Also, the first body dielectric layer 1001 is located at part, the part of the part of second area and the 3rd region of first area
It is respectively positioned on the second surface of the first Semiconductor substrate 100.Wherein, first group of shallow trench isolation(STI)1101st, first group of deep trench
Isolation(DTI)1201 and the isolation of second group of shallow trench(STI)1301 can be considered as the isolated side wall of each group transistor(Abbreviation side
Wall).First body dielectric layer 1001 can be considered as the bottom of each group transistor.That is, the first group transistor, the second group transistor,
Three group transistors employ different lateral and bottom insulation.
In the present embodiment, the first surface of the first Semiconductor substrate 100(" front "), refer to the first Semiconductor substrate
100 are formed with the surface of transistor;Second surface(" back side or " reverse side "), then refer to the first Semiconductor substrate 100 with " first
The relative another surface in surface ".Also, in the present embodiment, " depth " is exactly " distance " on ordinary meaning, the calculating of " depth "
Method is using the first surface of the first Semiconductor substrate 100 as reference, and " a certain layer has the first depth H 1(Or second depth H 2)”
The distance for referring to the first surface of this layer of the first Semiconductor substrate of distance 100 is H1(Or H2), for details, reference can be made to Figure 1A to H1 and
H2 sign, other situations are by that analogy.Specifically, in the present embodiment, first group of shallow trench isolation 1101 is close to first
The distance of first surface of the side of the second surface of Semiconductor substrate 100 away from the first Semiconductor substrate 100 is " the first distance "
H1;First group of deep trench isolation 1201 is close to the side of the second surface of the first Semiconductor substrate 100 away from the first Semiconductor substrate
The distance of 100 first surface is " second distance " H2;Second group of shallow trench isolation(STI)1301 close to the first Semiconductor substrate
The distance of first surface of the side of 100 second surface away from the first Semiconductor substrate 100 is also " the first distance " H1.
In the integrated circuit of the present embodiment, as shown in Figure 1A, the semiconductor lining of the region of the first group transistor 1102
The thickness at bottom is identical with the thickness of the Semiconductor substrate of the region of the second group transistor 1202, still, positioned at first group of crystal
The depth of first group of shallow trench isolation 1101 of the side of different transistors, which is less than, in pipe 1202 is located at the second group transistor
First group of deep trench isolation 1201 of the side of different transistors in 1202.3rd group transistor 1302 region is partly led
The thickness of body substrate is less than the thickness and the second group transistor of the Semiconductor substrate of the region of the first group transistor 1102
The thickness of the Semiconductor substrate of 1202 regions, in the 3rd group transistor 1,302 second group of different crystal pipe side it is shallow
The depth of trench isolations 1301 is identical with the depth of first group of shallow trench isolation 1101.
Exemplarily, the integrated circuit of the present embodiment also includes the positioned at the 6th region of the first Semiconductor substrate 100
By positioned at the of the first Semiconductor substrate 100 between each transistor in four group transistors 1402, the 4th group transistor 1402
Six regions and the 3rd group of shallow trench isolation with the first depth(STI)1401 are isolated, and bottom is by the first body dielectric layer 1001
Part positioned at the 6th region is isolated, wherein the part that the first body dielectric layer 1001 is located at the 6th region has the second depth
H2.Wherein, the structure of the 4th group transistor 1402 is identical with the first group transistor 1102, is used also as core transistor device
Part.In this example, because the structure of the 4th group transistor 1402 is identical with the first group transistor 1102, therefore, the 6th region
A part for first area can be considered as.In the present embodiment, the top of the 4th group transistor 1402 is also provided with microcomputer
Electric system(MEMS)Device 14031, specifically, MEMS(MEMS)Device 14031 can be arranged to be situated between positioned at the first body
In second body dielectric layer 1002 of the top of electric layer 1001, as shown in Figure 1A.
The integrated circuit of the present embodiment further comprises the four-range silicon hole positioned at the first Semiconductor substrate 100
(TSV)1505 and first Semiconductor substrate 100 the 5th region silicon hole 1605, silicon hole 1505 and silicon hole 1605 run through
First body dielectric layer 1001 is located at the part 1504 in the 4th region and the 5th region of the first Semiconductor substrate 100.Wherein,
Integral dielectric layer 1001 is located at the 4th region of the first Semiconductor substrate 100 and the part 1504 in the 5th region leads through the first half
Body substrate 100, also, the first body dielectric layer 1001 is located at the 4th region of the first Semiconductor substrate 100 and the portion in the 5th region
The first surface of points 1504 upper and lower surface respectively with the first Semiconductor substrate 100(Front)And second surface(The back side)In same
One horizontal plane.In the present embodiment, the effect of silicon hole 1505 and silicon hole 1605 is connection position in the first Semiconductor substrate
100 first surfaces(Front)And second surface(The back side)Device.Wherein, silicon hole 1505 and silicon hole 1605 can be one
It is individual or multiple, a silicon hole 1505 and a silicon hole 1605 are illustrate only in order to represent brief, in Figure 1A.Need what is explained
It is that the first body dielectric layer 1001 of the present embodiment includes part 1304, the position positioned at the 3rd region of the first Semiconductor substrate 100
Part 1504 and its positioned at the first Semiconductor substrate 100 in the 4th region of the first Semiconductor substrate 100 and the 5th region
The part 1100 in his region, as shown in Figure 1A.Also, subregion shows in a 1100th, 1304 and 1504 generally entirety, Figure 1A
Go out only to facilitate describing and explanation.
The integrated circuit of the present embodiment further comprises the integrated nothing positioned at the 5th region of the first Semiconductor substrate 100
Source device(IPD), the integrated passive devices include electric capacity 16061 and inductance 16062.In the present embodiment, integrated passive devices
It is located at the top of the part in the 5th region of the first Semiconductor substrate 100 positioned at the first body dielectric layer 1001, as shown in Figure 1A.Its
In, electric capacity 16061 and inductance 16062 can be one or more, and an inductance is illustrate only in order to represent brief, in Figure 1A
With an electric capacity.In the present embodiment, integrated passive devices can also only include inductively or capacitively, for number inductively or capacitively
Amount, the present embodiment is not defined.In the present embodiment, electric capacity 16061 passes through the Semiconductor substrate of silicon hole 1605 and first
100 first surfaces(Also referred to as front or upper surface)Miscellaneous part be connected, when integrated passive devices not include electric capacity 16061 when,
Silicon hole 1605 can be omitted.
The conduct that the integrated circuit of the present embodiment is typically also included on the first surface of the first Semiconductor substrate 100 is held
The second Semiconductor substrate 103 of substrate is carried, the second Semiconductor substrate 103 is general by adhesive layer 102 and positioned at the first semiconductor
The metal intermetallic dielectric layer of the first surface of substrate 100 or the bonding of other film layers, as shown in Figure 1A.Wherein, the second semiconductor lining
Bottom 103 can as the encapsulation of the integrated circuit a part.Certainly, the integrated circuit of the present embodiment can not also include second
Semiconductor substrate 103.
In the present embodiment, the integrated circuit also includes back segment metal interconnection structure, pad structure(Such as pad 1507, weldering
Disk 16071 and pad 16072 and connection pad 1506 etc.)And the structure, such as Figure 1A such as interlayer dielectric layer, metal intermetallic dielectric layer
It is shown.
In the present embodiment, the integrated circuit except integrated first group transistor 1102, the second group transistor 1202, the 3rd group
Outside the component such as transistor 1302, the 4th group transistor 1402 and integrated passive devices and MEMS, can with it is integrated its
His various assemblies, are not defined herein.
Figure 1B shows another schematic cross sectional views of the structure of the integrated circuit of the embodiment of the present invention.The integrated circuit
The difference of structure and the structure of the integrated circuit shown in Figure 1A be, the MEMS included by the integrated circuit
(MEMS)Device 14032 is arranged in the second Semiconductor substrate 103 as carrying substrate, as shown in Figure 1B.Of the invention real
Apply in example, MEMS(MEMS)Device can also be set in addition to the position that can be arranged on shown in Figure 1A and Figure 1B
In other any appropriate positions, for example:MEMS can be arranged at the first surface positioned at the first body Semiconductor substrate 100
On metal interconnection structure and the second Semiconductor substrate 103 between dielectric layer(Such as adhesive layer 102)It is interior, it is arranged at the second body
Other body dielectric layers of the top of dielectric layer 1002(Generally interlayer dielectric layer or metal intermetallic dielectric layer)It is interior.In fact, in this reality
In the integrated circuit for applying example, except forming the first group transistor 1102, the second group transistor 1202, the 3rd group transistor 1302 and the
The film layer and formation metal interconnection structure of the grade transistor of four group transistor 1402(That is, metal interconnection layer)Film layer outside other
Film layer(Generally interlayer dielectric layer or metal intermetallic dielectric layer)On or within MEMS can be set, for example, MEMS
It is at least one of that device can be located at first group transistor, second group transistor and the 3rd group transistor
Above or below.Also, what MEMS can be arranged at the first Semiconductor substrate 100 includes first area, second area, the
Regional including three regions, the 4th region, the 5th region and the 6th region.Concrete structure, MEMS on MEMS
Specific preparation method of the annexation of miscellaneous part and MEMS etc., those skilled in the art in device and integrated circuit
Member can be selected with reference to prior art according to actual needs, and here is omitted.
The integrated circuit of the present embodiment, due to be integrated with the first group transistor 1102, the second group transistor 1202, the 3rd group
The component such as transistor 1302, the 4th group transistor 1402 and integrated passive devices and MEMS, therefore can be used for realizing
RF front-end module(RFFEM)Function.Wherein, the first group transistor 1102 can be used for the work(for realizing power amplifier controller
Can, the second group transistor 1202 can be used for the function of realizing power amplifier core, and the 3rd group transistor 1302 can be used for
The function of RF switch is realized, the 4th group transistor 1402 can be used for the function of realizing tuner, and MEMS can be used for
Realize the function of duplexer, integrated passive devices(Such as electric capacity 16061 and inductance 16062)It can be used for the work(for realizing wave filter
Energy.
The integrated circuit of the present embodiment, due to being isolated between each group transistors such as the first group transistor 1102 by shallow trench
Or deep trench isolation(Shallow trench is isolated or deep trench isolation can be considered as the side wall of transistor)And the first body dielectric layer 1001
Isolated, with preferable noise isolation effect, making an uproar between the different parts in the integrated circuit can be avoided
Acoustic jamming so that whole integrated circuit has higher signal to noise ratio on the whole(SNR).And radio-frequency front-end mould of the prior art
Block(RF FEM)Realized by multiple chips by system in package, the cabling of different chip chambers can cause the generation of noise, past
It is relatively low toward signal to noise ratio.
In addition, the radio-frequency front-end of the integrated circuit of the present embodiment obviously than being realized by multiple chips by system in package
Module has smaller device size and lower power consumption and lower cost.Also, due to the integrated circuit of the present embodiment
The function of RF front-end module is realized by one chip form, therefore can relatively easily realize the functions such as many base band of multimode
More comprehensive communication function.
In short, the integrated circuit of the present invention, by using the first group transistor of different lateral and bottom insulation, second group
The component such as transistor, the 3rd group transistor and integrated passive devices and MEMS, list is integrated into by wafer work flow
On one chip, with passing through the RF front-end module made by system Integration in Package in the prior art(RF FEM)Compare,
With higher signal to noise ratio, lower power consumption, smaller device size and lower cost.
Embodiment two
Below, reference picture 2A- Fig. 2 J and Fig. 3, Fig. 4 describe the manufacturer of the integrated circuit of proposition of the embodiment of the present invention
The detailed step of one illustrative methods of method.Wherein, Fig. 2A to 2J is a kind of manufacturer of integrated circuit of the embodiment of the present invention
The schematic cross sectional views of the figure of the correlation step formation of method;Fig. 3 is a kind of manufacturer of integrated circuit of the embodiment of the present invention
A kind of indicative flowchart of method;Fig. 4 is a kind of the another schematic of the manufacture method of integrated circuit of the embodiment of the present invention
Flow chart.
The manufacture method of the integrated circuit of the embodiment of the present invention, for manufacturing the integrated circuit described in embodiment one, specifically
Comprise the following steps:
Step A1:First Semiconductor substrate 100 is provided, the first half are formed in parallel with the first Semiconductor substrate 100 and is led
The thinned stop-layer 101 on the surface of body substrate 100.Wherein, stop-layer 101 is thinned has depth in the first Semiconductor substrate 100
H2.The figure of formation, as shown in Figure 2 A.
In the present embodiment, the first surface of the first Semiconductor substrate 100(Or " front "), refer to the first Semiconductor substrate
100 are formed with transistor(Such as the first group transistor 1202)Surface;Second surface(" back side or " reverse side ")Then refer to the first half
Another surface relative with " first surface " of conductor substrate 100.Also, in the present embodiment, " depth " is exactly ordinary meaning
Upper " distance ", the computational methods of " depth " are using the first surface of the first Semiconductor substrate 100 as reference, and " a certain layer has second
Depth H 2 " refers to that the distance of the first surface of this layer of the first Semiconductor substrate of distance 100 is H2, for details, reference can be made to Fig. 2A to H2's
Sign, other situations(Such as depth is H1 situation)By that analogy.
In the present embodiment, exemplary, the first Semiconductor substrate 100 includes first area, second area, the 3rd area
Six regions such as domain, the 4th region, the 5th region and the 6th region, as shown in Figure 2 A.In fact, the first Semiconductor substrate 100
It can also include being less than six regions or the situation more than six regions.Regional is typically formed different devices, when
So, certain two or more region therein can also form identical device, not be defined herein.
In the present embodiment, the first Semiconductor substrate 100 typically uses body silicon(bulk Si).Stop-layer 101 and island is thinned
The horizontal separation layer 1300 of shape can use oxide(Silica)Or other suitable materials.Exemplary, stop-layer is thinned
101 and the horizontal separation layer 1300 of island be silica.
Wherein, forming the method for thinned stop-layer 101 can include:From second table of the first Semiconductor substrate 100
Non- Si ion implantation is carried out with the position of the second depth H 2 of the first Semiconductor substrate 100 in face of the first Semiconductor substrate 100
Form non-silicon sheath.Wherein, the non-silicon sheath can be used as that stop-layer 101 is thinned.Wherein, the non-silicon ion includes oxygen
Ion, carbon ion, Nitrogen ion or at least both combinations among them.
Further, it is described formation non-silicon sheath the step of after can also include to first Semiconductor substrate
The step of carrying out high-temperature process.
In the present embodiment, the effect that stop-layer 101 is thinned is essentially consisted in as subsequently entering to the first Semiconductor substrate 100
Stop-layer during row reduction processing.In the present embodiment, the processing step for forming thinned stop-layer 101 can be according to actual conditions
Omitted.
Step A2:Shallow trench isolation is formed in the first Semiconductor substrate 100(STI)And deep trench isolation(DTI).
Specifically, first group of shallow trench with the first depth H 1 is formed in the first area of the first Semiconductor substrate 100
Isolation 1101, in first group deep trench isolation of the second area formation with the second depth H 2 of the first Semiconductor substrate 100
1201, second group of shallow trench isolation 1301 with the first depth H 1 is formed in the 3rd region of the first Semiconductor substrate 100,
6th region of the first Semiconductor substrate 100 forms the 3rd group of shallow trench isolation 1401 with the first depth H 1, such as Fig. 2 B institutes
Show.
Wherein, H2 is more than H1.In the present embodiment, first group of shallow trench isolation 1101, second group of shallow ridges can be initially formed
Groove isolation 1301 and the 3rd group of shallow trench isolation 1401, re-form first group of deep trench isolation 1201.
In the present embodiment, first group of shallow trench isolation 1101 is close to the one of the second surface of the first Semiconductor substrate 100
The distance of first surface of the side away from the first Semiconductor substrate 100 is " the first distance " H1(That is, first group shallow trench isolation 1101 has
There is the first depth H 1);First group of deep trench isolation 1201 is close to the side of the second surface of the first Semiconductor substrate 100 away from first
The distance of the first surface of Semiconductor substrate 100 is " second distance " H2(That is, first group deep trench isolation 1201 has second deeply
Spend H2);Second group of shallow trench isolation(STI)1301 close to the side of the second surface of the first Semiconductor substrate 100 away from the first half
The distance of the first surface of conductor substrate 100 is also " the first distance " H1(That is, second group shallow trench isolation 1301 has first deeply
Spend H1).The distance that first surface of the stop-layer 101 away from the first Semiconductor substrate 100 is thinned is " second distance " H2.
In addition, in the present embodiment, the depth of first group of deep trench isolation 1201 of formation in the first Semiconductor substrate 100
Degree might be less that depth of the thinned stop-layer 101 in the first Semiconductor substrate 100, but still need to be more than first group of shallow trench every
From 1101, second group of shallow trench isolation 1301 and the 3rd group of shallow trench isolate 1401 depth in the first Semiconductor substrate 100.
The depth of stop-layer, which is now thinned, can be referred to as the 3rd depth or the 3rd distance, and the 3rd depth is more than H2.
Step A3:In the first area of the first Semiconductor substrate 100, second area, the 3rd region and the 6th region difference
The first group transistor 1102, the second group transistor 1202, the 3rd group transistor 1302 and the 4th group transistor 1402 are formed, is such as schemed
Shown in 2C.Wherein, the first group transistor 1102, the second group transistor 1202, the 3rd group transistor 1302 and the 4th group transistor
1402 are respectively positioned on the first surface side of the first Semiconductor substrate 100, as shown in Figure 2 C.
In the present embodiment, the first group transistor 1102, the second group transistor 1202, the 3rd group transistor 1302 and the 4th
Group transistor 1402 includes multiple transistors, brief for expression, only shows per group transistor in Fig. 2 C and relevant drawings
Show a transistor to meaning property.Also, in the present embodiment, to forming the first group transistor 1102, the second group transistor
1202nd, the sequencing of the 3rd group transistor 1302 and the 4th group transistor 1402 is not defined, those skilled in the art
Member can be selected according to actual needs.
Wherein, the first group transistor 1102 is core MOS transistor(Core MOS), generally low voltage mos transistor,
Two group transistors 1202 are high-voltage MOS transistor(HVMOS), the 3rd group transistor 1302 is complete depletion type MOS transistor(FD
MOS), the 4th group transistor 1402 is also core MOS transistor(Core MOS).Further, the second group transistor is LDMOS
Transistor(That is, laterally diffused MOS transistor).Due to the structure and the phase of the first group transistor 1102 of the 4th group transistor 1402
Together, therefore, the 6th region can be considered as a part for first area.In the present embodiment, if follow-up include forming micro electronmechanical
System(MEMS)The step of device, MEMS individually can be formed without at first group in the top of the 4th group transistor 1402
The top of transistor 1102 is formed.
Wherein, by positioned at the first of the first Semiconductor substrate 100 between each transistor in the first group transistor 1102
Region and first group of shallow trench isolation with the first depth H 1(STI)1101 are isolated;It is each in second group transistor 1202
Between individual transistor by the second area positioned at the first Semiconductor substrate 100 and with the second depth H 2 first group of deep trench every
From(DTI)1201 are isolated;By positioned at the first Semiconductor substrate 100 between each transistor in 3rd group transistor 1302
3rd region and second group of shallow trench isolation with the first depth H 1(STI)1301 are isolated;In 4th group transistor 1402
Each transistor between by positioned at the 6th region of the first Semiconductor substrate 100 and with the first depth H 1 the 3rd group of shallow ridges
Groove is isolated(STI)1401 are isolated.
Step A4:Carry out back-end process(BEOL)Technique forms metal interconnection with the front in the first Semiconductor substrate 100
Structure, as shown in Figure 2 D.
Specifically, the back-end process of semiconductor devices is passed through(BEOL)Technique, in the firstth area of the first Semiconductor substrate 100
Domain, second area, the 3rd region, the 6th region, the 4th region and the 5th region formed respectively the first metal interconnection structure 1103,
Second metal interconnection structure 1203, the 3rd metal interconnection structure 1303, the 4th metal interconnection structure 1403, fifth metal mutually link
The metal interconnection structure 1603 of structure 1503 and the 6th, as shown in Figure 2 D.The method for forming metal interconnection structure, can use existing skill
Various methods in art.Formed metal interconnection structure when, need to also be formed in the first Semiconductor substrate 100 interlayer dielectric layer,
The film layers such as metal level, here is omitted.
Step A5:Engaged in the first surface of the first Semiconductor substrate 100 for as carrying substrate(carrier
substrate)The second Semiconductor substrate 103.Exemplarily, the second Semiconductor substrate 103 by adhesive layer 102 with positioned at the
The metal intermetallic dielectric layer bonding of the first surface of semi-conductive substrate 100, as shown in Figure 2 E.
Wherein, the material of adhesive layer 102 can be oxide skin(coating) or other suitable materials.Second Semiconductor substrate 103
Can be various Semiconductor substrates, its role is to for carrying and supporting the first Semiconductor substrate 100.Wherein, the second half lead
Body substrate 103 can be removed in subsequent technique, can also be retained.Such as retained, the second Semiconductor substrate 103 can be with
In subsequent encapsulating process as integrated circuit encapsulation a part.The second Semiconductor substrate 103 of carrying substrate will be used as
A part for the encapsulation of integrated circuit is retained as, material can be saved, cost is reduced.
Step A6:Reduction processing is carried out to the second depth H 2 to the second surface of the first Semiconductor substrate 100, such as Fig. 2 F institutes
Show.
Wherein, second surface is the surface relative with first surface;Reduction processing to the second depth H 2 refers to thinned place
The thickness of the first Semiconductor substrate 100 after reason is identical with the second depth H 2.It is thinned when being formed with the first Semiconductor substrate 100
During stop-layer 101, it is preferable that reduction process is stopped on thinned stop-layer 101, i.e. the first Semiconductor substrate 100 is located at
The part on stop-layer 101 is thinned to be completely removed, as shown in Figure 2 F.
Step A7:The first body dielectric layer 1001 is formed in the first Semiconductor substrate 100, as shown in Figure 2 G.
Wherein, the first body dielectric layer 1001 is included positioned at the 4th region and the 5th region of first Semiconductor substrate 100
Part 1504 and the part 1100 positioned at other regions of the first Semiconductor substrate 100, as shown in Figure 2 G.1100 and 1504 is general
For an entirety, subregion is shown only to facilitate describing and explanation in Fig. 2 G.
Wherein, the first body dielectric layer 1001 can be silica or other suitable materials;It is preferred that, the first body dielectric layer
1001 be silica.
In the present embodiment, the first body dielectric layer is located at the upper and lower surface point of the part 1504 in the 4th region and the 5th region
Not with the first surface of the first Semiconductor substrate 100 Jing Guo reduction processing(Front)And second surface(Reverse side)In same water
Plane.
Exemplary, step A7 is generally comprised the steps:
Step A701:First Semiconductor substrate 100 is performed etching, is formed and run through through subtracting in the 4th region and the 5th region
The first groove of first Semiconductor substrate 100 of thin processing;
Step A702:Filled dielectric material and planarization process is carried out in first groove, to form the first body dielectric layer
1001.Wherein, dielectric material can be oxide.
Wherein, planarization process is carried out, second to the first Semiconductor substrate 100 after filled dielectric material is specifically referred to
Surface carries out planarization process.After planarization process, the second surface of the first Semiconductor substrate 100 is by the first body dielectric layer
1001 are covered, as shown in Figure 2 G.The technique for carrying out planarization process, can be chemically mechanical polishing(CMP)Or other method.
Step A8:The silicon for forming the part 1504 for being located at the 4th region and the 5th region through the first body dielectric layer 1001 leads to
Hole 1505 and silicon hole 1605, as illustrated in figure 2h.
Wherein, the effect of silicon hole 1505 and silicon hole 1605 is connection position in the table of the first Semiconductor substrate 100 first
Face and the device of second surface.In the present embodiment, silicon hole 1505 and silicon hole 1605 can be one or more, in order to
What is represented is brief, and Fig. 2 H and follow-up other accompanying drawings illustrate only a silicon hole 1505 and a silicon hole 1605.
Step A9:The top for being located at the part in the 5th region in the first body dielectric layer 1001 forms integrated passive devices
(IPD).Wherein, integrated passive devices include electric capacity and/or inductance element.
Exemplary, the top for being located at the part in the 5th region in the first body dielectric layer 1001 as shown in figure 2i forms electric capacity
16061 and inductance 16062, wherein, electric capacity 16061 is capacity plate antenna, including the Top electrode and bottom electrode formed by metal level.Show
Example property, electric capacity 16061 and inductance 16062 are formed at the second body dielectric layer 1002 of the top of the first body dielectric layer 1001
In.Wherein, electric capacity 16061 and inductance 16062 can be to be one or more, in order to represent brief, in Fig. 2 I and relevant drawings
It illustrate only an inductance and an electric capacity.In the present embodiment, integrated passive devices can also only include inductively or capacitively, right
In quantity inductively or capacitively, the present embodiment is not defined.In the present embodiment, electric capacity 16061 passes through silicon hole 1605
It is connected with the miscellaneous part of the first surface of the first Semiconductor substrate 100, when integrated passive devices do not include electric capacity 16061, silicon
Through hole 1605 can be omitted.In this step, it can also be formed while integrated passive devices are formed and be located at silicon hole
The connection pad 1506 of 1505 tops.
Step A10:Form the pad structure for connecting silicon hole and integrated passive devices.
Exemplary, as shown in fig. 2j, pad structure 1507,16071 and 16072 is formed, wherein, pad structure 1507 is used
In the outside that silicon hole 1505 is guided into integrated circuit, pad structure 16071 is used to guide electric capacity 16061 into integrated circuit outer
Portion, pad structure 16072 is used for the outside that inductance 16062 is guided into integrated circuit.
So far, the introduction of the correlation step of the manufacture method of the integrated circuit of the present embodiment is completed, can subsequently be passed through
The steps such as scribing, encapsulation complete the manufacture of final integrated circuit, and here is omitted.
In the present embodiment, between step A7 and A10, it is additionally may included in the first body dielectric layer 1001 and is located at the first half
The top of the four-range part of conductor substrate 100 and/or the part in the 5th region forms MEMS(MEMS)Device
The step of(It is denoted as step A8 '), it is exemplary, before step A9 after step A8, form the second body dielectric layer 1002 and position
In MEMS 14031 therein, as shown in Fig. 2 I and 2J.Also, between step A7 and A10, it is additionally may included in first
Group transistor 1102, the second group transistor 1202 and at least one of top of the 3rd group transistor 1302 form micro-electro-mechanical systems
System(MEMS)The step of device(It is denoted as step A8 ' ').Wherein, step A8 ' and step A8 ' ' can it is synchronous with step A8, can be with
It is synchronous with step A9, can be located between step A8 and step A9, can be located at step A9 after, may be located on step A8 it
Before, the present embodiment is defined not to this.In addition, in step A5 there is provided the second Semiconductor substrate 103 in can be with shape
Into there is MEMS(MEMS)Device.Also, can also the first dielectric layer on metal interconnection structure in step A5
(Such as interlayer dielectric layer or metal intermetallic dielectric layer)It is interior or on form MEMS, rejoin the second Semiconductor substrate 103.
In the present embodiment, being formed, the first group transistor 1102, the second group transistor 1202, the 3rd group transistor 1302 and the 4th group are brilliant
After the grade transistor of body pipe 1402 and metal interconnection structure, on or within each interlayer dielectric layer or metal intermetallic dielectric layer
MEMS can be formed, for example, MEMS can be located at first group transistor, second group transistor and institute
State the 3rd group transistor it is at least one of above or below.Also, the MEMS formed can be located at the first semiconductor
Each including first area, second area, the 3rd region, the 4th region, the 5th region and the 6th region of substrate 100
Region.Annexation and MEMS devices on miscellaneous part in the concrete structure of MEMS, MEMS and integrated circuit
Specific preparation method of part etc., those skilled in the art can be selected with reference to prior art according to actual needs, herein
Repeat no more.
In addition, the manufacture method of the integrated circuit of the present embodiment, except including the first group transistor of formation 1102, second group of crystalline substance
The component such as body pipe 1202, the 3rd group transistor 1302, the 4th group transistor 1402 and integrated passive devices and MEMS
Outside step, the step of can also including forming other various assemblies, it is not defined herein.
The integrated circuit according to made from the manufacture method of the integrated circuit of the present embodiment, is integrated with the first group transistor
1102nd, the second group transistor 1202, the 3rd group transistor 1302, the 4th group transistor 1402 and integrated passive devices and MEMS
The components such as device, can be used for realizing RF front-end module(RF FEM)Function.
The manufacture method of the integrated circuit of the present embodiment, due to foring shallow trench isolation or deep trench isolation and first
Body dielectric layer etc., can be to isolating between each components such as the first group transistor 1102, thus can avoid the integrated circuit
In different components between noise jamming so that whole integrated circuit has higher signal to noise ratio on the whole(SNR).And
RF front-end module of the prior art(RF FEM)Realized by multiple chips by system in package, different chip chambers are walked
Line can cause the generation of noise, and often signal to noise ratio is relatively low.
In addition, integrated circuit made from the manufacture method of the integrated circuit of the present embodiment, it is clear that than being led to by multiple chips
Crossing the RF front-end module of system in package realization has smaller device size and lower power consumption.And relative to prior art
In realize RF front-end module by way of system in package, the manufacture method of the integrated circuit of the present embodiment, due to using
The form of one chip realizes that the complexity of encapsulation will be reduced significantly, thus manufacturing cost can be also reduced.
Generally, the manufacture method of the present embodiment integrated circuit, can reduce the complexity and manufacturing cost of encapsulation, and
And, the integrated circuit according to obtained by this method, compared with RF front-end module of the prior art, with signal to noise ratio height, work(
The advantages of consumption is low, device size is small.
Fig. 3 shows a kind of a kind of indicative flowchart of the manufacture method for integrated circuit that the embodiment of the present invention is proposed,
Typical process for schematically illustrating the manufacture method.Specifically include:
Step S101:The first Semiconductor substrate is provided, in the first area and the 3rd region of first Semiconductor substrate
The isolation of first group of shallow trench and second group of shallow trench isolation with first depth are formed respectively, in first semiconductor
First group deep trench isolation of the second area formation with the second depth of substrate, wherein, second depth is more than described the
One depth;
Step S102:Form respectively in the first area of first Semiconductor substrate, second area and the 3rd region
One group transistor, the second group transistor and the 3rd group transistor, wherein, first group transistor, the second group transistor and
Three group transistors are respectively positioned on the first surface side of first Semiconductor substrate;
Step S103:The first body dielectric layer, first body are formed on the second surface of first Semiconductor substrate
Dielectric layer is located at first area, the part of second area and the 3rd region and the first surface of first Semiconductor substrate
Distance it is identical.
Fig. 4 shows a kind of another schematic flow of the manufacture method for integrated circuit that the embodiment of the present invention is proposed
Figure, for a kind of relative typical process for being illustrated in detail in the manufacture method.Specifically include:
Step S101:The first Semiconductor substrate is provided, in the first area and the 3rd region of first Semiconductor substrate
The isolation of first group of shallow trench and second group of shallow trench isolation with first depth are formed respectively, in first semiconductor
First group deep trench isolation of the second area formation with the second depth of substrate, wherein, second depth is more than described the
One depth;
Step S102:Form respectively in the first area of first Semiconductor substrate, second area and the 3rd region
One group transistor, the second group transistor and the 3rd group transistor, wherein, first group transistor, the second group transistor and
Three group transistors are respectively positioned on the first surface side of first Semiconductor substrate;
Step S103:The first body dielectric layer is formed on the second surface of first Semiconductor substrate;
Step S104:Silicon hole is formed in the 4th region of first Semiconductor substrate, the silicon hole is through described
First body dielectric layer is located at the four-range part of first Semiconductor substrate;
Step S105:In the first body dielectric layer positioned at the upper of the part in the 5th region of first Semiconductor substrate
It is square into integrated passive devices.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member according to the teachings of the present invention it is understood that the invention is not limited in above-described embodiment, can also make more kinds of
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (27)
1. a kind of integrated circuit, it is characterised in that including:First Semiconductor substrate, respectively be located at first Semiconductor substrate
The first area of first surface, the first group transistor of second area and the 3rd region, the second group transistor and the 3rd group it is brilliant
Body pipe and the first body dielectric layer on the second surface of first Semiconductor substrate, wherein,
By positioned at first semiconductor between each transistor in first group transistor of the first area
First group of shallow trench in substrate is isolated, wherein first group of shallow trench isolation is close to first Semiconductor substrate
The second surface the first surface of the side away from first Semiconductor substrate distance be the first distance;
By positioned at first semiconductor between each transistor in second group transistor of the second area
First group of deep trench isolation in substrate is isolated, wherein first group of deep trench isolation is close to first Semiconductor substrate
The second surface the first surface of the side away from first Semiconductor substrate distance be second distance;
By positioned at the first Semiconductor substrate between each transistor in the 3rd group transistor in the 3rd region
Second group of interior shallow trench is isolated, wherein institute of second group of shallow trench isolation close to first Semiconductor substrate
The distance for stating the first surface of the side away from first Semiconductor substrate of second surface is first distance;
Wherein, the second distance is more than first distance, and the second distance is less than or equal to described the first half and led
The thickness of body substrate,
First group transistor, the second group transistor, the bottom of each transistor in the 3rd group transistor are by described first
Body dielectric layer is isolated.
2. integrated circuit as claimed in claim 1, it is characterised in that first group transistor is low voltage mos transistor, institute
The second group transistor is stated for high-voltage MOS transistor.
3. integrated circuit as claimed in claim 1, it is characterised in that the 3rd group transistor is complete depletion type MOS crystal
Pipe.
4. integrated circuit as claimed in claim 2, it is characterised in that second group transistor is laterally diffused MOS crystal
Pipe.
5. integrated circuit as claimed in claim 1, it is characterised in that the first body dielectric layer also includes being located at described first
The 4th region and the part in the 5th region of Semiconductor substrate, wherein, the first body dielectric layer is located at first semiconductor
First Semiconductor substrate is run through in 4th region of substrate and the part in the 5th region.
6. integrated circuit as claimed in claim 5, it is characterised in that the integrated circuit, which also includes being located at described the first half, leads
The four-range silicon hole of body substrate, the silicon hole is located at first Semiconductor substrate through the first body dielectric layer
Four-range part.
7. integrated circuit as claimed in claim 5, it is characterised in that the integrated circuit also includes being located at first body Jie
Electric layer is located at the integrated passive devices of the top of the part in the 5th region of first Semiconductor substrate.
8. integrated circuit as claimed in claim 7, it is characterised in that the integrated passive devices include electric capacity and/or inductance.
9. the integrated circuit as described in any one of claim 5 to 8, it is characterised in that the integrated circuit also includes being arranged at
The first body dielectric layer is upper positioned at the part in the four-range part of first Semiconductor substrate and/or the 5th region
MEMS (MEMS) device of side.
10. the integrated circuit as described in any one of claim 1 to 8, it is characterised in that the integrated circuit also includes being located at institute
State the first group transistor, second group transistor and the 3rd group transistor it is at least one of above or below it is micro-
Mechatronic Systems (MEMS) device.
11. the integrated circuit as described in any one of claim 1 to 8, it is characterised in that the integrated circuit also includes being located at institute
State the second Semiconductor substrate as carrying substrate on the first surface of the first Semiconductor substrate, also, the integrated circuit
Also include MEMS (MEMS) device being arranged in second Semiconductor substrate.
12. a kind of manufacture method of integrated circuit, it is characterised in that methods described includes:
Step S101:First Semiconductor substrate is provided, distinguished in the first area of first Semiconductor substrate and the 3rd region
First group of shallow trench isolation and second group of shallow trench isolation are formed, in the second area formation first of first Semiconductor substrate
Group deep trench isolation, wherein, first group of shallow trench isolation is close to the relative with first surface of first Semiconductor substrate
Second surface the first surface of the side away from first Semiconductor substrate distance be the first distance, described second group
Side institute away from first Semiconductor substrate of the shallow trench isolation close to the second surface of first Semiconductor substrate
The distance for stating first surface is first distance, institute of the first group of deep trench isolation close to first Semiconductor substrate
State second surface the first surface of the side away from first Semiconductor substrate distance be second distance, described second away from
With a distance from more than described first;
Step S102:First group is formed respectively in the first area of first Semiconductor substrate, second area and the 3rd region
Transistor, the second group transistor and the 3rd group transistor, wherein, first group transistor, the second group transistor and the 3rd group
Transistor is respectively positioned on the first surface side of first Semiconductor substrate;
Step S103:The first body dielectric layer, the first body dielectric are formed on the second surface of first Semiconductor substrate
Layer be located at the part in the first area of first Semiconductor substrate, second area and the 3rd region and the first surface away from
From identical,
Wherein, the bottom of first group transistor, the second group transistor, each transistor in the 3rd group transistor is by described
First body dielectric layer is isolated.
13. the manufacture method of integrated circuit as claimed in claim 12, it is characterised in that first group transistor is low pressure
MOS transistor, second group transistor is high-voltage MOS transistor.
14. the manufacture method of integrated circuit as claimed in claim 12, it is characterised in that the 3rd group transistor is full consumption
Most type MOS transistor.
15. the manufacture method of integrated circuit as claimed in claim 13, it is characterised in that second group transistor is laterally
Spread MOS transistor.
16. the manufacture method of integrated circuit as claimed in claim 12, it is characterised in that in the step S102 and the step
Also include step S1023 between rapid S103:
Back-end process technique is carried out with the first surface of first Semiconductor substrate formation metal interconnection structure.
17. the manufacture method of integrated circuit as claimed in claim 16, it is characterised in that the step S1023 with it is described
Also comprise the following steps between step S103:
Step S10231:The second semiconductor for carrying substrate is used as in the first surface engagement of first Semiconductor substrate
Substrate;
Step S10232:The second surface of first Semiconductor substrate is carried out reduction processing to cause after reduction processing
The first Semiconductor substrate first surface of the second surface away from first Semiconductor substrate distance be the 3rd distance, it is described
3rd distance is more than or equal to the second distance.
18. the manufacture method of integrated circuit as claimed in claim 17, it is characterised in that
In the step S101, first group of shallow trench isolation, second group of shallow trench isolation and described the are being formed
Before one group of deep trench isolation, first table away from first Semiconductor substrate is formed in first Semiconductor substrate
The distance in face is the thinned stop-layer of the 3rd distance;
In the step S10232, the reduction processing is stopped on the thinned stop-layer.
19. the manufacture method of integrated circuit as claimed in claim 18, it is characterised in that form the step of the thinned stop-layer
Suddenly include:Non- Si ion implantation is carried out to first Semiconductor substrate from the second surface of first Semiconductor substrate
With at the second depth location of first Semiconductor substrate formed non-silicon sheath, wherein the non-silicon ion include oxygen from
Son, carbon ion, Nitrogen ion or at least both combinations among them.
20. the manufacture method of integrated circuit as claimed in claim 19, it is characterised in that in the formation non-silicon sheath
Also include after step, the step of high-temperature process is carried out to first Semiconductor substrate.
21. the manufacture method of integrated circuit as claimed in claim 12, it is characterised in that
In the step S103, the first body dielectric layer is also included positioned at the 4th region and the 5th of the Semiconductor substrate
The part in region, also, the step S103 includes:
Step S1031:First Semiconductor substrate is performed etching, with the 4th region of first Semiconductor substrate and
5th region forms the first groove through first Semiconductor substrate through reduction processing;
Step S1032:Filled dielectric material and planarization process is carried out in the first groove, be located at described first to be formed
Region, second area, the 3rd region, the first body dielectric layer in the 4th region and the 5th region.
22. the manufacture method of integrated circuit as claimed in claim 21, it is characterised in that also wrapped after the step S103
Include step S104:
Silicon hole is formed in the 4th region of first Semiconductor substrate, the silicon hole is through the first body dielectric layer position
In the four-range part of first Semiconductor substrate.
23. the manufacture method of integrated circuit as claimed in claim 22, it is characterised in that also wrapped after the step S104
Include step S105:
The top for being located at the part in the 5th region of first Semiconductor substrate in the first body dielectric layer forms integrated nothing
Source device.
24. the manufacture method of integrated circuit as claimed in claim 23, it is characterised in that the integrated passive devices include electricity
Hold and/or inductance.
25. the manufacture method of integrated circuit as claimed in claim 22, it is characterised in that also wrapped after the step S103
Include step S104 ':
It is located at the four-range part of first Semiconductor substrate and/or the portion in the 5th region in the first body dielectric layer
The top divided forms MEMS (MEMS) device.
26. the manufacture method of the integrated circuit as described in any one of claim 12 to 21, it is characterised in that in the step
Also include step S104 " after S103:
First group transistor, second group transistor and the 3rd group transistor it is at least one of it is square
Into MEMS (MEMS) device.
27. the manufacture method of integrated circuit as claimed in claim 17, it is characterised in that in the step S10231, institute
State and MEMS (MEMS) device is formed with the second Semiconductor substrate.
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CN106847753A (en) * | 2015-01-29 | 2017-06-13 | 江西师范大学 | The forming method of the gas sensor of CMOS technique compatible |
CN105480934B (en) * | 2015-02-09 | 2017-04-26 | 江西师范大学 | CMOS (Complementary Metal Oxide Semiconductor) humidity sensor |
US10861841B2 (en) * | 2018-09-28 | 2020-12-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with multiple polarity groups |
DE102019101999B4 (en) | 2018-09-28 | 2021-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | SEMICONDUCTOR DEVICE WITH MULTIPLE POLARITY GROUPS |
CN117615987A (en) * | 2022-03-31 | 2024-02-27 | 京东方科技集团股份有限公司 | Electronic device and preparation method thereof |
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CN101064307A (en) * | 2006-04-26 | 2007-10-31 | 美格纳半导体有限会社 | Semiconductor integrated circuit |
CN101410967A (en) * | 2006-05-16 | 2009-04-15 | 国际商业机器公司 | Dual wired integrated circuit chips |
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SE0200414D0 (en) * | 2002-02-13 | 2002-02-13 | Ericsson Telefon Ab L M | Semiconductor fabrication process lateral pnp transistor, and integrated circuit |
US6845034B2 (en) * | 2003-03-11 | 2005-01-18 | Micron Technology, Inc. | Electronic systems, constructions for detecting properties of objects, and assemblies for identifying persons |
US8216913B2 (en) * | 2007-12-24 | 2012-07-10 | Texas Instruments Incorporated | Strain modulation in active areas by controlled incorporation of nitrogen at si-SiO2 interface |
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CN101064307A (en) * | 2006-04-26 | 2007-10-31 | 美格纳半导体有限会社 | Semiconductor integrated circuit |
CN101410967A (en) * | 2006-05-16 | 2009-04-15 | 国际商业机器公司 | Dual wired integrated circuit chips |
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Effective date of registration: 20180523 Address after: No. 18 Zhangjiang Road, Pudong New Area, Shanghai Co-patentee after: Core integrated circuit (Ningbo) Co., Ltd. Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: No. 18 Zhangjiang Road, Pudong New Area, Shanghai Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |