CN105480934B - CMOS (Complementary Metal Oxide Semiconductor) humidity sensor - Google Patents
CMOS (Complementary Metal Oxide Semiconductor) humidity sensor Download PDFInfo
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- CN105480934B CN105480934B CN201510873464.8A CN201510873464A CN105480934B CN 105480934 B CN105480934 B CN 105480934B CN 201510873464 A CN201510873464 A CN 201510873464A CN 105480934 B CN105480934 B CN 105480934B
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00349—Creating layers of material on a substrate
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
- B81C1/00246—Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
Abstract
The invention discloses a CMOS (Complementary Metal Oxide Semiconductor) humidity sensor, which comprises a substrate, a thermal insulation area and a hanging structure, wherein the substrate comprises an MOS (Metal Oxide Semiconductor) device area and a sensor area, a top dielectric layer, a third dielectric layer, a second dielectric layer and a first dielectric layer which are arranged in the sensor area and an annular groove in part of the substrate, and the annular groove surrounds a first metal interconnection layer, a first electric connection layer, a bottom electrode layer, a second electric connection layer and a top electrode layer; the thermal insulation area is arranged in the sensor area; and the hanging structure is arranged above the sensor area. According to the CMOS humidity sensor, a forming process of the humidity sensor is completely compatible with a forming process of the MOS device, and the humidity sensor and the MOS device are integrated on one chip, so that the chip area is reduced, the power consumption is reduced and the integration level and the yield are improved.
Description
The application be the Application No. 201510066381.8, applying date on 2 9th, 2015, entitled CMOS it is wet
The divisional application of the Chinese invention patent application of degree sensor and forming method thereof.
Technical field
The present invention relates to field of semiconductor fabrication technology, more particularly to a kind of CMOS humidity sensors.
Background technology
At present, all it is frequently necessary to that ambient humidity is measured and controlled in fields such as industrial and agricultural production, environmental protection, space flight
System, in conventional ambient parameter, humidity is to be most difficult to one of accurate parameter for measuring.
Humidity sensor be the physical effect related to humidity can be occurred based on its functional material or chemical reaction manufacture and
Into, it has the function that humidity physical quantity is converted into the signal of telecommunication.Humidity sensor can divide according to the difference of its operation principle
For：Telescopic humidity sensor, is changed using the linear dimension of defat hair with the change of environment moisture content；Vaporation-type is wet
Degree sensor, i.e. wet and dry bulb humidity sensor, using dry bulb and wet bulb thermometer, temperature difference becomes both in relative humidity variations
Change and be obtained；Dew-point humidity sensor, makes the steam in gas reach saturation and condense, according to dew point temperature using cooling means
Relative humidity in spending to measure gas；Electronic type humidity sensor, including resistance-type, condenser type and electrolytic.Capacity type wet
Degree sensor is changed and is changed capacitance using dielectric constant after wet sensory material water suction, its have sensitivity it is high, low in energy consumption,
The advantage such as temperature drift is little, thus receive extensive concern.
Microsensor is integrated with the signal processing circuit of surrounding, fabrication and processing on the same chip, with realize
The performance of more functions and Geng Gao, while reducing the cost of sensor, it has also become MEMS (Micro-Electro-
Mechanical System) development a new focus and trend.By the system integration, humidity sensor and signal processing electricity
Road is close as far as possible, so as to largely reduce parasitic parameter and external disturbance；Single chip integrated humidity sensor may be used also
To reduce the integrity problem interconnected between different chips.
Therefore, using CMOS (Complementary Metal Oxide Semiconductor) technologies by humidity sensor
Device and signal processing circuit carry out it is integrated on piece, and formed humidity sensor technique will not cause bad to signal processing circuit
Affect, be the study hotspot and focus of following humidity sensor.Therefore, need badly and a kind of formation side of new humidity sensor is provided
Method, at the same humidity sensor and cmos signal processing apparatus is integrated on the same chip, and the technique for forming humidity sensor
Cmos signal processing apparatus will not be had undesirable effect.
The content of the invention
The problem that the present invention is solved is to provide a kind of CMOS humidity sensors, formation process and the MOS devices of humidity sensor
The formation process compatibility of part is high, reduces chip area, improves integrated level and yield, reduces power consumption and production cost.
To solve the above problems, the present invention provides a kind of CMOS humidity sensors, including：Substrate, the substrate includes MOS
Device region and sensor regions, are formed with polysilicon gate, the sensor regions section substrate on MOS device area section substrate
On be formed with polysilicon zone of heating, be formed with the substrate and be covered in polycrystalline silicon gate surface and polysilicon heating layer surface
First medium layer；First sub- metal interconnecting layer of the first medium layer surface above the MOS device area, described first is sub
Metal interconnecting layer is electrically connected with polysilicon gate；The some mutual electricity of the first medium layer surface above the sensor regions is absolutely
First metal interconnecting layer of edge, the first electric connection layer and lower electrode layer, and first metal interconnecting layer, the first electrical connection
Floor and lower electrode layer across MOS device area and the boundary of sensor regions, wherein, the first metal of at least 2 electrically insulated from one another
Interconnection layer is electrically connected with polysilicon zone of heating；Positioned at first interest belong to interconnection layer surfaces, the first metal interconnecting layer surface, under
The second dielectric layer of electrode layer surface and first medium layer surface；Second dielectric layer table above the MOS device area
The second sub- metal interconnecting layer in face, the second sub- metal interconnecting layer is electrically connected with polysilicon gate；On the sensor regions
Second electric connection layer of the second medium layer surface of side, second electric connection layer is electrically connected with the first electric connection layer；Positioned at institute
State the 3rd dielectric layer that the second interest belongs to interconnection layer surfaces, the second electric connection layer surface and second medium layer surface；Positioned at institute
State the 3rd sub- metal interconnecting layer of the 3rd dielectric layer surface above MOS device area, and the 3rd sub- metal interconnecting layer with it is many
Crystal silicon grid are electrically connected；The upper electricity electrically connected with the second electric connection layer of the 3rd dielectric layer surface above the sensor regions
There is relative coincidence face between pole layer, and the upper electrode layer and lower electrode layer；Positioned at the 3rd interest belong to interconnection layer surfaces,
Upper electrode layer surface and the top layer dielectric layer of the 3rd dielectric layer surface；Top layer dielectric layer positioned at the sensor regions, the 3rd
Dielectric layer, second dielectric layer, first medium layer and section substrate internal ring connected in star, the annular groove is mutual around the first metal
Connect layer, the first electric connection layer, lower electrode layer, the second electric connection layer and upper electrode layer；Positioned at the thermal insulation areas of the sensor regions
Domain, the area of insulation mutually runs through with annular groove, and the area of insulation is located between substrate and polysilicon zone of heating；Position
Through hole in the top layer dielectric layer of the sensor regions and the 3rd dielectric layer of segment thickness, and positioned at residual thickness
The 3rd dielectric layer in groove, the groove mutually runs through with through hole, and has between the groove and lower electrode layer relative
Coincidence face, has relative coincidence face between the groove and upper electrode layer；The humidity-sensitive material layer of the full groove of filling and through hole.
Compared with prior art, technical scheme has advantages below：
The invention provides a kind of superior CMOS humidity sensors of structural behaviour, MOS device is integrated with humidity sensor
On the same chip, chip area is little, and CMOS humidity sensors is low in energy consumption.
Description of the drawings
Fig. 1 to Figure 25 is the structural representation of CMOS humidity sensors forming process provided in an embodiment of the present invention.
Specific embodiment
From background technology, processing technology and the CMOS technology poor compatibility of prior art humidity sensor, it is difficult to adopt
Humidity sensor is made with the CMOS technology of standard.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent from, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 1 to Figure 25 is the structural representation of CMOS humidity sensors forming process provided in an embodiment of the present invention.
With reference to Fig. 1, there is provided substrate 100, the substrate 100 includes MOS device area I and sensor regions II.
The material of the substrate 100 is silicon, germanium, SiGe, carborundum or GaAs, and the substrate 100 can also be exhausted
The germanium on silicon, insulator or the SiGe on insulator on edge body.The surface of the substrate 100 can also form some extensions
Boundary layer or strained layer, to improve the electric property of CMOS humidity sensors.In the present embodiment, the substrate 100 is silicon substrate.
The MOS device area I is the region of MOS signal processors to be formed, for be subsequently formed PMOS transistor, nmos pass transistor or
CMOS transistor provides signal processing circuit platform, for detecting or gathering the signal of telecommunication in humidity sensor；The sensor
Area II is the region of humidity sensor to be formed, and to be subsequently formed humidity sensor work platformses are provided.The MOS device area I
Isolation structure can also be formed in substrate 100, the isolation structure can be fleet plough groove isolation structure (STI, Shallow
Trench Isolation), the packing material of isolation structure is the insulant such as silicon oxide, silicon nitride or silicon oxynitride.May be used also
To form some well regions in MOS device area I substrates 100, the type of the well region is true according to the type of MOS device to be formed
Fixed, the doping type of the well region is that n-type doping or p-type are adulterated.For example, nmos pass transistor is formed on part MOS device area I
When, then P type trap zone is formed in corresponding MOS device area I substrates 100, the dopant ion of the P type trap zone is B, Ga or In；
When forming PMOS transistor on part MOS device area I, then N-type well region, the N are formed in corresponding MOS device area I substrates 100
The dopant ion of type well region is P, As or Sb.
The present embodiment is subsequently formed as an example, accordingly humidity sensor with a MOS device area I, a sensor regions II
The quantity of device is 1, on parallel to the surface direction of substrate 100, the size of the sensor regions II be 10 microns × 10 microns extremely
50 microns × 50 microns.In other embodiments, the quantity in MOS device area can be the arbitrary natural number more than or equal to 1, sensing
The quantity in device area can also be the arbitrary natural number more than or equal to 1, then the quantity and sensor of the humidity sensor being correspondingly formed
The quantity in area is identical.
In the present embodiment, subsequently with the formation PMOS transistor in MOS device area I as an example.
With reference to Fig. 2, in the MOS device area I and sensor regions II surfaces oxide layer is formed；In the oxidation layer surface shape
Into polysilicon layer；The polysilicon layer and oxide layer of the graphical MOS device area I, forms and is located at MOS device area I parts lining
First oxide layer 111 and the polysilicon gate 112 positioned at the surface of the first oxide layer 111 on the surface of bottom 100；The graphical biography
The polysilicon layer and oxide layer of sensor area II, forms the second oxide layer positioned at the surface of sensor regions II section substrate 100
121 and positioned at the polysilicon zone of heating 122 on the surface of the second oxide layer 121.The material of the oxide layer is silicon oxide, is adopted
Chemical vapor deposition method forms the oxide layer；The material of the polysilicon layer is the polysilicon of polysilicon or doping, is adopted
Chemical vapor deposition method forms the polysilicon layer.In the present embodiment, in the technique with along with, the graphical MOS is carried out
The polysilicon layer and oxide layer of device region I and sensor regions II.In the present embodiment, in the MOS device area I section substrates 100
Upper formation is formed with the first oxide layer 111 between polysilicon gate 112, and the polysilicon gate 112 and substrate 100；Forming institute
While stating polysilicon gate 112, polysilicon zone of heating 122 is formed on the sensor regions II section substrates 100, and it is described many
The second oxide layer 121 is formed between crystal silicon zone of heating 122 and substrate 100.First oxide layer 111 and polysilicon gate 112
Constitute the grid structure of MOS device.The polysilicon zone of heating 122 as humidity sensor adding thermal resistance, subsequent current stream
Joule's heat energy is produced during Jing polysilicon zones of heating 122 in polysilicon zone of heating 122, so as to enter to the humidity-sensitive material layer being subsequently formed
Row heating, improves humidity-sensitive material layer and senses the sensitivity of humidity, shortening the response time of humidity sensor.Parallel to substrate
On the direction on 100 surfaces, the section shape of the polysilicon zone of heating 122 is square, square waveform, zig-zag, annular or spiral shell
Rotation shape, wherein, spiral type can be square spiral.In the present embodiment, the polysilicon zone of heating 122 is shaped as sawtooth waveforms
Shape, the thickness of polysilicon zone of heating 122 is 2 nanometers to 300 nanometers.After the grid structure for forming MOS device, also including step
Suddenly：The substrate 100 of grid structure both sides is doped, source region and the drain region of MOS device is correspondingly formed.
With reference to Fig. 3, first medium floor 103 is formed in the MOS device area I and the surface of sensor regions II substrate 100, it is described
First medium layer 103 is also covered in the surface of polysilicon gate 112 and the surface of polysilicon zone of heating 122.The first medium layer 103
The sidewall surfaces of polysilicon gate 112, the sidewall surfaces of polysilicon zone of heating 122 are not only covered in, the top of polysilicon gate 112 is also covered in
Surface, the top surface of polysilicon zone of heating 122.The material of the first medium layer 103 be insulant, can for silicon oxide,
Silicon nitride or silicon oxynitride.In the present embodiment, the first medium layer 103 is formed using chemical vapor deposition method, first is situated between
The material of matter layer 103 is silicon oxide.With continued reference to Fig. 3, if being formed in the first medium layer 103 above the sensor regions II
Dry first conductive plunger 301, first conductive plunger 301 is electrically connected with polysilicon zone of heating 122.In the present embodiment, while
The first conductive plunger 301 is formed in first medium floor 103 above MOS device area I, first above MOS device area I is conductive
Connector 301 is electrically connected with the transistor in MOS signal processors, such as the source electrode, drain electrode or polysilicon gate 112 with transistor
Electrical connection, the first metal interconnecting layer that the first conductive plunger 301 above MOS device area I is also subsequently formed with MOS device area I
Electrical connection.At least 2 the first conductive plungers 301 above the II of sensor regions are electrically connected with polysilicon zone of heating 122, by first
Conductive plunger 301 to polysilicon zone of heating 122 provides electric current, so as to produce joule's heat energy, sensor in polysilicon zone of heating 122
The first metal interconnecting layer that the first conductive plunger 301 above area II is also subsequently formed with sensor regions II is electrically connected.At one
In specific embodiment, forming the processing step of first conductive plunger 301 includes：In the surface shape of the first medium layer 103
Into graph layer；First medium layer 103 described in the graph layer as mask etching, if being formed in the first medium layer 103
Dry first conductive through hole, the first conductive through hole positioned at MOS device area exposes source electrode, drain electrode and the polysilicon gate of transistor
112 surfaces, the first conductive through hole bottom-exposed positioned at sensor regions II goes out the surface of polysilicon zone of heating 122；Form filling full
Push up with first medium layer 103 at the top of first conductive plunger 301 of first conductive through hole, and first conductive plunger 301
Portion flushes.The material of first conductive plunger 301 be metal, for example the material of the first conductive plunger 301 can for copper, aluminum or
Tungsten.
With reference to Fig. 4 to Fig. 6, Fig. 4 is top view, and Fig. 5 is cross-sectional views of the Fig. 4 along line of cut AA1, and Fig. 6 is Fig. 4
Along the cross-sectional view of line of cut BB1, the surface of first medium layer 103 above the sensor regions II forms some phases
The first metal interconnecting layer 401, the first electric connection layer 421 and the lower electrode layer 411 being mutually electrically insulated, wherein, at least 2 are mutually electric
First metal interconnecting layer 401 of insulation is electrically connected with polysilicon zone of heating 122.The lower electrode layer 411, the first electric connection layer
421 is identical with the material of the first metal interconnecting layer 401, and is formed using the technique with along with.First metal interconnecting layer 401
Material is metal, and such as material of the first metal interconnecting layer 401 is copper, aluminum or tungsten；The material of the lower electrode layer 411 is gold
Category, such as material of lower electrode layer 411 are copper, aluminum or tungsten.And in the present embodiment, the first metal is formed above the II of sensor regions
While interconnection layer 401, the first sub- metal interconnecting layer electrically connected with polysilicon gate 112 is also formed above MOS device area I
431.The first sub- metal interconnecting layer 431 above MOS device area I is electrically connected with polysilicon gate 112, specifically by first
Conductive plunger 301 makes the first sub- metal interconnecting layer 431 electrically connect with polysilicon gate 112.
The lower electrode layer 411 is the bottom electrode plate of capacitor that is subsequently formed, and the lower electrode layer 411 is also located at
The surface of MOS device area I parts first mediums floor 103, i.e., described lower electrode layer 411 is handed over across MOS device area I and sensor regions II
Boundary, so that a part of the lower electrode layer 411 as the support arm being subsequently formed, and make the lower electrode layer 411 access to MOS
In signal processing circuit.
The first metal interconnecting layer 401 above the II of sensor regions is heated by the first conductive plunger 301 and polysilicon
Layer 122 is electrically connected, and the electrically insulated from one another of the first metal interconnecting layer 401 electrically connected with the polysilicon zone of heating 122 so that after
Continuous electric current is flowed in polysilicon zone of heating 122, then via another first metal interconnecting layer via one first metal interconnecting layer 401
401 flow out, so that electric current flows through from polysilicon zone of heating 122, and then make to produce joule's heat energy in polysilicon zone of heating 122.
First electric connection layer 421 is electrically connected with the upper electrode layer being subsequently formed, and by the first electric connection layer 421 upper electrode layer is connect
Enter into MOS signal processing circuits, and upper electrode layer and the electrically insulated from one another of lower electrode layer 411.In the present embodiment, the first metal is mutual
Even floor 401 is also located at the surface of part first medium floor 103 of MOS device area I, i.e., the first metal interconnecting layer 401 is across MOS device
Area I and sensor regions II have a common boundary, so that as the support arm being subsequently formed of first metal interconnecting layer 401
Point, additionally it is possible to by the first metal interconnecting layer 401, polysilicon zone of heating 122 is accessed in MOS signal processing circuits.Equally
, the first electric connection layer 421 also across the boundary of MOS device area I and sensor regions II so that first electric connection layer
421 as the support arm being subsequently formed a part, additionally it is possible to make electric pole plate access to MOS by the first electric connection layer 421
In signal processing circuit.By deposition, etching technics make first metal interconnecting layer 401, the first electric connection layer 421, the
One sub- metal interconnecting layer 431 and lower electrode layer 411.
With reference to Fig. 7 to Fig. 9, Fig. 7 is top view, and Fig. 8 is cross-sectional views of the Fig. 7 along line of cut AA1, and Fig. 9 is Fig. 7
Along the cross-sectional view of line of cut BB1, formation is covered in the surface of first medium layer 103, the first sub- metal interconnecting layer
431st, the second dielectric layer on the surface of the first metal interconnecting layer 401, the surface of the first electric connection layer 421 and the surface of lower electrode layer 411
104；Some second conductive plungers 302 are formed in second dielectric layer 104 above the II of sensor regions, and second conduction is inserted
Plug 302 is electrically connected with the first electric connection layer 421；Form second in the second dielectric layer 104 above device region I simultaneously conductive slotting
Plug 302, second conductive plunger 302 is electrically connected with polysilicon gate 122.The material of the second dielectric layer 104 is insulation material
Material, can form the second dielectric layer 104 using chemical vapor deposition, physical vapour deposition (PVD) or atom layer deposition process.It is described
The top surface of second dielectric layer 104 is higher than the top surface of the first metal interconnecting layer 401.Above the II of sensor regions second is led
Electric plug 302 and lower electrode layer 411, the electrically insulated from one another of polysilicon zone of heating 122, and second above the II of sensor regions lead
Electric plug 302 is electrically connected with the first electric connection layer 421, subsequently through first electric connection layer 421 so that what is be subsequently formed is upper
Electrode layer accesses to MOS signal processing circuits.It is conductive slotting that the forming method of second conductive plunger 302 refers to aforementioned first
The forming method of plug 301.
With reference to figures 10 to Figure 12, Figure 10 is top view, and Figure 11 is cross-sectional views of the Figure 10 along line of cut AA1, is schemed
12 be Figure 10 along line of cut BB1 cross-sectional view, the surface shape of second dielectric layer 104 above the sensor regions II
Into the second metal interconnecting layer 402 and the second electric connection layer 422, second electric connection layer 422 is electric with the first electric connection layer 421
Connection, and there is relative coincidence face between second metal interconnecting layer 402 and lower electrode layer 411.Refer to relative coincidence face
Be：Second metal interconnecting layer 402 is projected on the figure and lower electrode layer 411 on the surface of substrate 100 and is projected on the surface of substrate 100
Figure there is the part that overlaps.In the present embodiment, the second conductive plunger 302 positioned at sensor regions II is electrically connected with second
Connect layer 422 to electrically connect, the electricity of the first electric connection layer 421 and the second electric connection layer 422 is realized by second conductive plunger 302
Connection.In the present embodiment, while the second sub- metal interconnecting layer 432 is formed on the surface of second dielectric layer 104 of MOS device area I, and
The second sub- metal interconnecting layer 432 above MOS device area I is electrically connected with polysilicon gate 112.The present embodiment is forming described second
The surface of second dielectric layer 104 while 402 and second electric connection layer 422 of metal interconnecting layer, also above the II of sensor regions
Form pseudo- metal interconnecting layer 412, the electrically insulated from one another of 412 and second electric connection layer of pseudo- metal interconnecting layer 422, and the pseudo- gold
Category interconnection layer 412 is across MOS device area I and the boundary of sensor regions II.And the pseudo- metal interconnecting layer 412 is located at the first metal
The surface of interconnection layer 401, the first electric connection layer 421.In the technical process that subsequent etching forms annular groove, can etch sudden and violent
Expose the surface of pseudo- metal interconnecting layer 412, and the etching technics is very little to the etch rate of pseudo- metal interconnecting layer 412, therefore
During etching forms annular groove, the pseudo- metal interconnecting layer 412 plays the first metal interconnecting layer 401 of protection and the
The effect of one electric connection layer 421, prevents the first metal interconnecting layer 401 and the first electric connection layer 421 to be exposed in external environment,
So as to the signal of telecommunication in the upper electrode layer that avoids polysilicon zone of heating 122 and be subsequently formed is subject to external interference.Also, due to
Afterwards extended meeting etching removes the second metal interconnecting layer 401, the second medium being located in the present embodiment immediately below pseudo- metal interconnecting layer 401
Layer 104 plays a part of to protect the first metal interconnecting layer 401 and the first electric connection layer 421, prevents the first metal interconnecting layer 401
And first electric connection layer 421 be etched removal.The second electrical connection being located in the present embodiment directly over the first electric connection layer 421
Layer 422 is electrically connected with the first electric connection layer 421, and be located at the second electric connection layer 422 directly over the first metal interconnecting layer 401 and
First electric connection layer 421 is electrically insulated.Second metal interconnecting layer 402 is identical with the material of the second electric connection layer 422.This enforcement
In example, the material of second metal interconnecting layer 402 is aluminum.Afterwards extended meeting etching removes the second metal interconnecting layer 402, is subsequently filled
Humidity-sensitive material layer, therefore the position of second metal interconnecting layer 402 is the position of the part humidity-sensitive material layer being subsequently formed, and is
There is relative coincidence face, when moisture content becomes in environment between this described second metal interconnecting layer 402 and lower electrode layer 411
During change, the relative dielectric coefficient of the dielectric layer between lower electrode layer 411 and the upper electrode layer that is subsequently formed changes, so that
Capacitance between lower electrode layer 411 and upper electrode layer changes, to obtain environment in humidity.
With reference to figures 13 to Figure 15, Figure 13 is top view, and Figure 14 is cross-sectional views of the Figure 13 along line of cut AA1, is schemed
15 is cross-sectional views of the Figure 13 along line of cut BB1, in the described second sub- metal interconnecting layer 432, the second metal interconnecting layer
402nd, the second electric connection layer 422, pseudo- metal interconnecting layer 412 and the surface of second dielectric layer 104 form the 3rd dielectric layer 105；
The surface of the 3rd dielectric layer 105 above the sensor regions II forms the upper electrode layer electrically connected with the second electric connection layer 422
There is relative coincidence face, the upper electrode layer 423 and described the between 423, and the upper electrode layer 423 and lower electrode layer 411
There is relative coincidence face between two metal interconnecting layers 402.In the present embodiment, while upper electrode layer 423 are formed, described
The surface of the 3rd dielectric layer 104 above MOS device area I forms the 3rd sub- metal interconnecting layer electrically connected with polysilicon gate 112
433.Before the upper electrode layer 423 is formed, formed in the 3rd dielectric layer 104 above the sensor regions II it is some with
3rd conductive plunger 303 of the electrical connection of the second electric connection layer 422, and the 3rd conductive plunger 303 is electrically connected with upper electrode layer 423
Connect；Form the 3rd electrically connected with the second sub- metal interconnecting layer 432 in the 3rd dielectric layer 105 above MOS device area I simultaneously
Conductive plunger 303, the 3rd sub- metal interconnecting layer 433 is electrically connected with the second sub- metal interconnecting layer 432.The upper electrode layer
423 as capacitor electric pole plate, second electrically connected with the 3rd conductive plunger 303 by the 3rd conductive plunger 303
The second conductive plunger 302 and second conductive plunger that electric connection layer 422 is electrically connected with second electric connection layer 422
First electric connection layer 421 of 302 electrical connections so that upper electrode layer 423 is accessed in MOS signal processing circuits.The Top electrode
Layer 423 and lower electrode layer 411 between have relative coincidence face, the upper electrode layer 423 and second metal interconnecting layer 402 it
Between there is relative coincidence face so that having between upper electrode layer 423, the second metal interconnecting layer 402, the three of lower electrode layer 411
With respect to coincidence face, when environment moisture content changes, the phase of the dielectric layer between upper electrode layer 423 and lower electrode layer 411
Dielectric coefficient is changed, so that the capacitance between upper electrode layer 423 and lower electrode layer 411 changes.This enforcement
In example, on parallel to the surface direction of the substrate 100, the upper electrode layer 423 is shaped as pectination, the upper electrode layer
The 423 some discrete Part II for including Part I and Part I electrical connection and parallel distribution, adjacent second portions
Between expose the surface of the 3rd dielectric layer 105, the present embodiment is so that upper electrode layer 423 includes 2 Part II as an example.In other realities
In applying example, on parallel to substrate surface direction, the section shape of the upper electrode layer can also be square, circular or broken line
Shape.The upper electrode layer 423 is identical with the material of the 3rd sub- metal interconnecting layer 433, is copper, aluminum or tungsten, and using the work with along with
Skill step forms the sub- metal interconnecting layer 433 of the upper electrode layer 423 and the 3rd.
Unless otherwise noted, the schematic diagram that subsequent technique process is provided is the schematic diagram carried out on the basis of Figure 15.
With reference to Figure 16, in the surface of the 3rd dielectric layer 105, the surface of upper electrode layer 423 and the 3rd sub- metal interconnecting layer
433 surfaces form the 4th dielectric layer 106；Formed and polysilicon gate in the 4th dielectric layer 106 above the MOS device area I
4th conductive plunger 304 of 112 electrical connections；The surface of the 4th dielectric layer 106 above the MOS device area I is formed and the 4th
The top-level metallic interconnection layer 404 of the electrical connection of conductive plunger 304；Formation is covered in the surface of top-level metallic interconnection layer 404 and the 4th
The top layer dielectric layer 107 on the surface of dielectric layer 106.Relevant 4th dielectric layer 106, the 4th conductive plunger 304, top-level metallic interconnection layer
404 and the forming method of top layer dielectric layer 107 refer to preceding description, will not be described here.The present embodiment is forming described
Before top layer dielectric layer 107, the 4th dielectric layer 106 is yet forms both, in other embodiments, if MOS device area not necessarily forms
Four sub- metal interconnecting layers, then directly in the 3rd dielectric layer surface, the 3rd interest belong to interconnection layer surfaces and upper electrode layer surface shape
Into top layer dielectric layer.
With reference to Figure 17, photoresist layer 108 is formed on the surface of the top layer dielectric layer 107, the photoresist layer 108 has position
Annular opening 112 above the II of sensor regions.
The annular opening 112 surround photoresist layer 108 be projected on the surface of substrate 100 figure be the 4th figure, institute
State polysilicon zone of heating 122 be projected on the surface of substrate 100 figure be the 5th figure, the border of the 5th figure is by the 4th figure
Shape is covered, so as to prevent polysilicon zone of heating 122 to be exposed in follow-up isotropic etching process environments.The upper electrode layer
423 figures for being projected on the surface of substrate 100 are the 6th figure, and the 6th figure is covered by the 4th figure, so as to prevent upper electricity
Pole layer 423 is exposed in follow-up dry etching environment, it is to avoid upper electrode layer 423 is exposed in external environment.
Also, in the present embodiment, the annular opening 112 is located at the surface of pseudo- metal interconnecting layer 412 so that follow-up to carve
During erosion forms annular groove, pseudo- metal interconnecting layer 412 plays the electrical connection of the first metal interconnecting layer of protection 401 and first
The effect of layer 421, is beneficial to the support arm for being subsequently formed hanging structure.
The photoresist layer 108 be subsequent etching top layer dielectric layer 107, the 4th dielectric layer 106, the 3rd dielectric layer 105, the
The mask of the substrate 100 of second medium layer 104, first medium layer 103 and segment thickness, is to form hanging structure to prepare.
The size of the annular opening 112 is relevant with the area of insulation size being subsequently formed, if the size of annular opening 112
Excessive, then the volume shared by area of insulation being subsequently formed is larger, causes to form the chip area needed for CMOS humidity sensors
Greatly；If annular opening 112 is undersized, the small volume shared by area of insulation being subsequently formed causes polysilicon zone of heating
122 heats for producing easily are transferred to undesirable region, the response time delay of CMOS humidity sensors.
Also, if annular opening 112 is undersized, the size of the annular groove being accordingly subsequently formed is also less, when
When etching 100 sidewall surfaces of substrate that annular groove exposes using isotropic etching technique, etching gas reach the lining
The difficulty of the sidewall surfaces of bottom 100 increases.Meanwhile, if annular opening 112 is oversized, the annular groove being accordingly subsequently formed
Size it is also larger, when formed humidity-sensitive material layer when, the amount into the humidity-sensitive material of annular groove is larger, causes polysilicon to heat
The heat that layer 122 is produced is difficult to spread out, and the heat dispersion of CMOS humidity sensors is poor.
For this purpose, in the present embodiment, on parallel to the surface direction of substrate 100, the size of the annular opening 112 is 3 micro-
Rice is to 5 microns.
In the present embodiment, also there is son opening 113 in the photoresist layer 108, the sub- opening 113 is located at the second metal
The top of interconnection layer 402, and the size for being smaller in size than the second metal interconnecting layer 402 of the sub- opening 113.
Subsequently perform etching along the sub- opening 113, until exposing the surface of the second metal interconnecting layer 402.If son opening
113 it is undersized, then subsequently fill humidity-sensitive material layer ability it is excessively weak.
For this purpose, in the present embodiment, on parallel to the surface direction of substrate 100, the size of the sub- opening 113 is 10 microns
To 50 microns.
It is the cross-sectional view on the basis of Figure 17 with reference to Figure 18 and Figure 19, Figure 18, Figure 19 is Figure 13 along line of cut
Cross-sectional view on the basis of CC1 cuttings, with the photoresist layer 108 as mask, along (the ginseng of the annular opening 112
Examine Figure 17) top layer dielectric layer 107 that exposes is performed etching, until etching removes the substrate 100 of segment thickness, in the sensing
II tops in device area form annular groove 109；The top layer dielectric layer 107 for exposing along son opening 113 simultaneously is performed etching, until cruelly
Expose the surface of the second metal interconnecting layer 402, in the top of second metal interconnecting layer 402 through hole 110 is formed.
Specifically, using dry etch process, top layer dielectric layer 107, the 4th dielectric layer 106, the 3rd medium are sequentially etched
Layer 105, second dielectric layer 104 and first medium layer 103, form the annular groove 109；Using dry etch process, according to
Secondary top layer dielectric layer 107, the 4th dielectric layer 106 and the 3rd dielectric layer 105, form the through hole 110.
The dry etch process is to the second metal interconnecting layer 402, the first electric connection layer 421, the first metal interconnecting layer
401st, the etch rate very little of lower electrode layer 411, and to top layer dielectric layer 107, the 4th dielectric layer 106, the 3rd dielectric layer 105,
The etch rate of second dielectric layer 104 and first medium layer 103 is very big.
Because the pseudo- metal interconnecting layer 412 of sensor regions II is across MOS device area I and the boundary of sensor regions II, dry method
Etch rate very little of the etching technics to pseudo- metal interconnecting layer 412, therefore dry etch process will not be to pseudo- metal interconnecting layer 421
The second dielectric layer 104 of underface, the first metal interconnecting layer 401, the first electric connection layer 421 cause etching.
Also, avoid the second electric connection layer 422, the first metal interconnecting layer 401 and the first electric connection layer 421 to be exposed to
In etching environment, so as to the signal of telecommunication accuracy in improving polysilicon zone of heating 122 and upper electrode layer 413, it is to avoid second is electric
Articulamentum 422, the first metal interconnecting layer 402 and the first electric connection layer 421 are exposed to subsequent etching and remove the interconnection of the second metal
In the etching environment of layer 402.
The thickness of the substrate 100 that the employing dry etch process etching is removed and the size of the area of insulation being subsequently formed
Relevant, if substrate 100 is etched, the thickness of removal is too small, undersized, the follow-up shape of the area of insulation being accordingly subsequently formed
Into hanging structure it is too small with the distance between substrate 100, the heat in the polysilicon zone of heating 122 be difficult release；If lining
Bottom 100 be etched removal thickness it is excessive, then the thickness very little of corresponding remaining substrate 100, easily causes polysilicon zone of heating
122 be stressed effect it is too strong, cause polysilicon zone of heating 122 occur serious deformation.If also, substrate 100 is etched removal
Thickness it is excessive, then the substrate 100 of the corresponding follow-up sensor regions II when isotropic etching technique is carried out can be cut through.It is comprehensive
Above-mentioned factor consider, substrate 100 be etched removal thickness for the original depth of substrate 100 1/30 to 1/3, for example, substrate 100
Be etched removal thickness can be the original depth of substrate 100 1/10 or 1/5.In the present embodiment, the employing dry etching
The thickness of substrate 100 that technique etching is removed is 5 microns to 10 microns, for example, can be 6 microns or 8 microns；It can also be expected that
In the surface direction of substrate 100, the side wall dimensions of substrate 100 that the annular groove 109 exposes are 5 microns to 10 micro-
Rice.In the present embodiment, the thickness of dielectric layer is 8 microns to 12 microns, and the dielectric layer is：First medium layer 103, positioned at first
The second dielectric layer 104 on the surface of dielectric layer 103, the 3rd dielectric layer 105 positioned at the surface of second dielectric layer 104, positioned at the 3rd be situated between
4th dielectric layer 106 and the top layer dielectric layer 107 positioned at the surface of the 4th dielectric layer 106 on the surface of matter layer 105；Parallel to
In the surface direction of substrate 100, the size of the annular groove 109 is 3 microns to 5 microns.In the present embodiment, the annular groove
109 sidewall surfaces are perpendicular to the surface of substrate 100；In other embodiments, it is described in the surface direction of substrate 100
The section shape of annular groove 109 can also be inverted trapezoidal so that the top dimension of annular groove 109 is more than the bottom of annular groove 109
Portion's size, so that the etching gas of follow-up isotropic etching technique easily enter the bottom of annular groove 109, from
And the sidewall surfaces of substrate 100 exposed to annular groove 109 are performed etching.Because rear extended meeting fills wet sensitive into through hole 110
Material layer, and avoid the formation of humidity-sensitive material during humidity-sensitive material layer as far as possible and enter in annular groove 109, in the present embodiment,
Parallel in the surface direction of substrate 100, the size of the annular groove 109 is the 1/10 to 2/5 of the size of through hole 110.
In a specific embodiment, on parallel to the surface direction of substrate 100, the size of the annular groove 109 is 3
To 5 microns, the size of the through hole 110 is 10 microns to 50 microns to micron.When the size of the annular groove 109 is 4 microns,
When the size of the through hole 110 is 25 microns, the performance of the humidity-sensitive material layer that follow-up filling is formed is optimal, and can be prevented effectively from wet
The material of quick material layer is entered in annular groove 109.
It is the schematic diagram on the basis of Figure 18 with reference to Figure 20 and Figure 21, Figure 20, Figure 21 is the schematic diagram on the basis of Figure 19,
Using isotropic etching technique, perform etching along the sidewall surfaces of substrate 100 that the annular groove 109 exposes, in sensing
II tops in device area form hanging structure, have area of insulation 114 between the hanging structure and substrate 100.
In the present embodiment, using XeF2The isotropic etching technique is carried out, due to XeF2For dry etching, and XeF2
Etching technics is chemical etching, can avoid the problem of ion dam age that ion bom bardment brought and charge accumulated.Also,
XeF2Only substrate 100 is performed etching, and it is very little to the etch rate of dielectric layer, metal interconnecting layer or even can ignore not
Count, therefore the isotropic etching technique has no adverse effects to MOS device area I, therefore hanging structure is formed in the present embodiment
Technique it is completely compatible with standard CMOS process.
On parallel to the surface direction of substrate 100, the size of the area of insulation 114 is 10 microns to 50 microns, for example
For 15 microns, 20 microns, 25 microns or 35 microns.
In a specific embodiment, using XeF2The technological parameter for carrying out isotropic etching technique is：Circulation is carried out
XeF is passed through into etching cavity2With extraction XeF2Action, XeF in etching cavity2Pressure is 100Pa to 180Pa, and to etching
Within the chamber is passed through XeF2Maintain 10 seconds to 50 seconds afterwards, cycle-index is 5 to 15 times.For example, XeF in etching cavity2Pressure can be
120Pa, 140Pa or 150Pa, into etching cavity XeF is passed through2Maintain 15 seconds, 20 seconds or 30 seconds afterwards.Due to XeF2For each to same
Property etching technics, therefore during etching forms hanging structure, the isotropic etching technique both can etches polycrystalline silicon
Substrate 100 immediately below zone of heating 122, can also etch the substrate 100 positioned at device region I.With reference to Figure 22 and Figure 23, Figure 22 be
Schematic diagram on the basis of Figure 20, Figure 23 is the schematic diagram on the basis of Figure 21, and etching removes second metal interconnecting layer 402
(with reference to Figure 20,21).After the area of insulation 114 is formed, also including step：Wet etching is removed and is located under through hole 110
Second metal interconnecting layer 402 of side, forms the groove 116 positioned at the lower section of the through hole 110.In the present embodiment, the second metal is mutual
Even the material of layer 402 is aluminum, using the second metal interconnecting layer 402 described in hydrofluoric acid solution erosion removal.The chi of the groove 116
It is very little equivalently-sized with the second metal interconnecting layer 402.In other embodiments, it would however also be possible to employ tetramethyl ammonium hydroxide solution is carved
Etching off removes second metal interconnecting layer 402；Can with formed groove 116 after form the area of insulation 114.Due to puppet
Metal interconnecting layer 412 (with reference to Figure 20,21) be exposed to the etching environment, therefore remove second metal interconnection in etching
While layer 402, etching removes the pseudo- metal interconnecting layer 412.And second be located at immediately below the pseudo- metal interconnecting layer 412
Dielectric layer 104, the first electric connection layer 421, the first metal interconnecting layer 401 will not be etched.
In the present embodiment, the hanging structure has support arm, is adapted to function as supporting the effect of hanging structure；The support
Arm is laminated construction, is at least included：Second dielectric layer 104, first immediately below the pseudo- metal interconnecting layer 412 is electrically connected
The 421, first metal interconnecting layer 401 of layer and lower electrode layer 411, first medium layer 103.Due to the first metal interconnecting layer 401,
First electric connection layer 421 is covered by second dielectric layer 104, so as to reduce the first metal interconnecting layer 401 and the first electric connection layer
421 probability for being oxidized or corroding.
Due to full humidity-sensitive material layer subsequently can be also filled in groove 116, in order to improve the filling effect of humidity-sensitive material layer,
In the present embodiment, on parallel to the surface direction of substrate 100, the size of the groove 116 is 2 times to 5 of the size of through hole 110
Times.
In a specific embodiment, on parallel to the surface direction of substrate 100, the size of the through hole 110 is 10 micro-
To 50 microns, the size of the groove 116 is 20 microns to 200 microns to rice.
When the size of annular groove 109 is 4 microns, the size of through hole 110 is 25 microns, and the size of groove 116 is 80 micro-
Meter Shi, the humidity-sensitive material layer being subsequently formed is good to the filling effect of groove 116 and through hole 110, so that the wet sensitive for being formed
The ability of material layer sensing steam is optimum, and effectively avoids humidity-sensitive material layer from entering in annular groove 109, so that CMOS
The good heat dissipation effect of humidity sensor.
After second metal interconnecting layer 402 is removed, the photoresist layer 108 (referring to Figure 18) is removed.
With reference to Figure 24, Figure 24 is the schematic diagram on the basis of Figure 22, and using spin coating process the full ditch of filling is formed
The humidity-sensitive material layer 115 of groove 116 (referring to Figure 22) and through hole 110 (referring to Figure 22), the humidity-sensitive material layer 115 is also located at top
Layer dielectric layer 107 surface.Humidity-sensitive material layer 115 is of the capacitor dielectric between upper electrode layer 423 and lower electrode layer 411
Point, after the steam that humidity-sensitive material layer 114 is absorbed in external environment, the relative dielectric coefficient of humidity-sensitive material layer 115 can occur
Change, so that the capacitance of capacitor that electric pole plate 423 is constituted with bottom electrode plate 411 changes, it is electric by measurement
The change of capacitance, can obtain the moisture content in external environment, and the humidity for obtaining external environment.It is described in the present embodiment
The material of humidity-sensitive material layer 115 is polyimides, and using spin coating process the humidity-sensitive material layer 115 is formed.Specifically, it is first
First, using dropper to the appropriate poly- phthalein amino acid solution of the surface of top layer dielectric layer 107 drop, and ensure that poly- phthalein amino acid solution is introduced into annular
Groove 109, then, the surface of top layer dielectric layer 107 is uniformly coated in using the first rotating speed, while poly- phthalein amino acid by poly- phthalein amino acid
Into through hole 110 and groove 116, then spin coating process is entered using the second rotating speed, second rotating speed is more than first
Rotating speed, forms polyamides Asia sorrel.This have the advantage that：The full through hole 110 of poly- phthalein amino acid filling and groove 116 can be made,
And do not enter in annular groove 109 as far as possible.Then, heat treated is carried out to polyamides Asia sorrel, is converted into polyamides Asia sorrel wet
Quick material layer 115.First rotating speed is 1000 revs/min to 1600 revs/min, and second rotating speed is 5000 revs/min to 6500
Rev/min.In a specific embodiment, first rotating speed is 1250 revs/min, when second rotating speed is 5600 revs/min, ditch
The filling effect of the humidity-sensitive material layer 115 in groove 116 and through hole 110 is good, and the wet sensing performance of the humidity-sensitive material layer 115 for being formed
It is excellent.In order to improve the wet sensing performance of the humidity-sensitive material layer 115 of formation, prevent humidity-sensitive material layer 115 from breaking in particular during a heating process
Split, the process of heat treated is：First 200 degrees Celsius are risen to from room temperature with the speed of 20 degree mins Celsius, in 200 degrees Celsius of insulations
20 minutes；Then 300 degrees Celsius are risen to so as to 200 degrees Celsius with the speed of 5 degree mins Celsius, at 300 degrees Celsius 1 hour is incubated.
In a specific embodiment, on parallel to the surface direction of substrate 100, the size of the through hole 110 is 10 micro-
To 50 microns, the size of the groove 116 is 20 microns to 200 microns to rice, using the size of rational annular groove 109, groove
116 sizes and the size of through hole 110 so that the full groove 116 of the preferably filling of humidity-sensitive material layer 115 and through hole 110, and enter
Amount to annular groove 109 is very few, effectively raises the heat dispersion of CMOS humidity sensors.Spin coating process is
The technique that humidity-sensitive material layer 115 is formed in one of standard CMOS process, therefore the present embodiment is completely compatible with standard CMOS process,
Effectively reduce production cost.
With reference to Figure 25, etching removes the humidity-sensitive material layer 115 positioned at the surface of top layer dielectric layer 107.Etching is removed and is located at top
The humidity-sensitive material layer 115 on layer dielectric layer 107 surface so that humidity-sensitive material layer 115 be only filled with full groove 116 (referring to Figure 23) and
Through hole 110 (refers to Figure 23).Also, it is aforementioned during humidity-sensitive material layer 115 is formed using spin coating process, have few
The humidity-sensitive material layer 115 of amount is entered in annular groove 109, and the reactive ion etching process can also etch the removal entrance ring
Humidity-sensitive material layer 115 in connected in star 109.In one embodiment, using reactive ion etching process, reactive ion etching is adopted
Gas is O2、CF4Or N2.In the present embodiment, while cmos signal processing apparatus are made, using standard CMOS process
Making forms CMOS humidity sensors so that humidity sensor is integrated on same wafer with cmos signal processing apparatus.Simultaneously
In sensor regions, II defines hanging structure in the present embodiment so that humidity sensor is to the heat in polysilicon zone of heating 122
Utilization rate it is higher, so as to accelerate the response time of humidity sensor.
The embodiment of the present invention provides a kind of CMOS humidity sensors, with reference to reference to Figure 14 and referring to Figure 25, including：Substrate
100, the substrate 100 includes MOS device area I and sensor regions II, is formed with the MOS device area I section substrates 100
Polysilicon gate 112, on the sensor regions II section substrates 100 polysilicon zone of heating 122, shape on the substrate 100 are formed with
Into there is the first medium layer 103 that is covered in the surface of polysilicon gate 112 and the surface of polysilicon zone of heating 122；Positioned at the MOS devices
The first sub- metal interconnecting layer 431 on the surface of first medium floor 103 above part area I, the first sub- metal interconnecting layer 431 with it is many
Crystal silicon grid 112 are electrically connected；The of some electrically insulated from one another on the surface of first medium layer 103 above the sensor regions II
One metal interconnecting layer 401, the first electric connection layer 421 and lower electrode layer 411, and first metal interconnecting layer 401, first is electric
Articulamentum 421 and lower electrode layer 411 across the boundary of MOS device area I and sensor regions II, wherein, at least 2 mutual electricity
First metal interconnecting layer 401 of insulation is electrically connected with polysilicon zone of heating 122；Positioned at the table of the described first sub- metal interconnecting layer 431
The second dielectric layer on face, the surface of the first metal interconnecting layer 401, the surface of lower electrode layer 411 and the surface of first medium layer 103
104；The second sub- metal interconnecting layer 432 on the surface of second dielectric layer 104 above the MOS device area I, described second is sub
Metal interconnecting layer 432 is electrically connected with polysilicon gate 112；The surface of second dielectric layer 104 above the sensor regions II
Second electric connection layer 422, second electric connection layer 422 is electrically connected with the first electric connection layer 421；Positioned at second interest category
3rd dielectric layer 105 on the surface of interconnection layer 432, the surface of the second electric connection layer 422 and the surface of second dielectric layer 104；Positioned at institute
State the 3rd sub- metal interconnecting layer 433 on the surface of the 3rd dielectric layer 105 above MOS device area I, and the 3rd interest category interconnection
Layer 433 is electrically connected with polysilicon gate 112；The surface of the 3rd dielectric layer 105 above the sensor regions II it is electric with second
The upper electrode layer 423 of the electrical connection of articulamentum 422, and there is relative coincidence between the upper electrode layer 423 and lower electrode layer 411
Face；Positioned at the top on the surface of the 3rd sub- metal interconnecting layer 433, the surface of upper electrode layer 423 and the surface of the 3rd dielectric layer 105
Layer dielectric layer 107；Top layer dielectric layer 107, the 3rd dielectric layer 105, second dielectric layer 104 positioned at the sensor regions II,
One dielectric layer 103 and the internal ring connected in star 109 of section substrate 100, circular first metal interconnecting layer 401 of the annular groove 109,
First electric connection layer 421, lower electrode layer 411, the second electric connection layer 422 and upper electrode layer 423；Positioned at the sensor regions II
Area of insulation 114, the area of insulation 114 mutually runs through with annular groove 109, and the area of insulation 114 is located at substrate
Between 100 and polysilicon zone of heating 122；Positioned at the sensor regions II top layer dielectric layer 107 and segment thickness the 3rd
Through hole in dielectric layer 105, and the groove in the 3rd dielectric layer 105 of residual thickness, the groove is mutual with through hole
Run through, and there is relative coincidence face between the groove and lower electrode layer 411, have between the groove and upper electrode layer 423
With respect to coincidence face；The humidity-sensitive material layer 115 of the full groove of filling and through hole.It should be noted that annular not shown in Figure 14
Groove 109, area of insulation 114 and top layer dielectric layer 107.In the present embodiment, the dielectric layer 105 of top layer dielectric layer 107 and the 3rd
Between be also formed with the 4th dielectric layer 106.Also include：In first medium layer 103 above the sensor regions II first
Conductive plunger 301, first conductive plunger 301 is electrically connected with the metal interconnecting layer 401 of polysilicon zone of heating 122 and first；
Positioned at the sensor regions II top second dielectric layer 104 in the second conductive plunger 302, second conductive plunger 302 with
First electric connection layer 421 and the second electric connection layer 422 are electrically connected；Positioned at the 3rd dielectric layer 105 of sensor regions II tops
The 3rd interior conductive plunger 303, the 3rd conductive plunger 303 is electrically connected with the second electric connection layer 422 and upper electrode layer 423
Connect.The hanging structure has support arm, is adapted to function as supporting the effect of hanging structure；The support arm is laminated construction, extremely
Include less：Second dielectric layer 104, the first electric connection layer 421, the first metal interconnecting layer 401, lower electrode layer 411 and first are situated between
Matter layer 103.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, without departing from this
In the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (3)
1. a kind of CMOS humidity sensors, it is characterised in that include：
Substrate, the substrate includes MOS device area and sensor regions, and on the MOS device area section substrate polycrystalline is formed with
Si-gate, is formed with polysilicon zone of heating on the sensor regions section substrate, be formed with the substrate and be covered in polysilicon gate
Surface and the first medium layer of polysilicon heating layer surface；
First sub- metal interconnecting layer of the first medium layer surface above the MOS device area, the first interest category is mutual
Even layer is electrically connected with polysilicon gate；
First metal interconnecting layer of some electrically insulated from one another of the first medium layer surface above the sensor regions, first
Electric connection layer and lower electrode layer, and first metal interconnecting layer, the first electric connection layer and lower electrode layer are across MOS devices
Part area and the boundary of sensor regions, wherein, the first metal interconnecting layer and the polysilicon zone of heating of at least 2 electrically insulated from one another are electrically connected
Connect；
Belong to interconnection layer surfaces, the first metal interconnecting layer surface, lower electrode layer surface and first medium positioned at first interest
The second dielectric layer of layer surface；
Second sub- metal interconnecting layer of the second medium layer surface above the MOS device area, the second interest category is mutual
Even layer is electrically connected with polysilicon gate；
Second electric connection layer of the second medium layer surface above the sensor regions, second electric connection layer and first
Electric connection layer is electrically connected；
Belong to the 3rd Jie of interconnection layer surfaces, the second electric connection layer surface and second medium layer surface positioned at second interest
Matter layer；
3rd sub- metal interconnecting layer of the 3rd dielectric layer surface above the MOS device area, and the 3rd interest category
Interconnection layer is electrically connected with polysilicon gate；
The upper electrode layer electrically connected with the second electric connection layer of the 3rd dielectric layer surface above the sensor regions, and institute
Stating in relative coincidence face of have between upper electrode layer and lower electrode layer；
Belong to the top layer dielectric layer of interconnection layer surfaces, upper electrode layer surface and the 3rd dielectric layer surface positioned at the 3rd interest；
Top layer dielectric layer, the 3rd dielectric layer, second dielectric layer, first medium layer and section substrate positioned at the sensor regions
Interior annular groove, the annular groove is around the first metal interconnecting layer, the first electric connection layer, lower electrode layer, the second electrical connection
Layer and upper electrode layer；
Positioned at the area of insulation of the sensor regions, the area of insulation mutually runs through with annular groove, and the area of insulation
Between substrate and polysilicon zone of heating；Top layer dielectric layer and the 3rd Jie of segment thickness positioned at the sensor regions
Through hole in matter layer, and the groove in the 3rd dielectric layer of residual thickness, the groove mutually runs through with through hole, and institute
Stating in relative coincidence face of have between groove and lower electrode layer, there is relative coincidence face between the groove and upper electrode layer；
Hanging structure above sensor regions；
The humidity-sensitive material layer of the full groove of filling and through hole.
2. CMOS humidity sensors according to claim 1, it is characterised in that also include：On the sensor regions
The first conductive plunger in square first medium layer, first conductive plunger and polysilicon zone of heating and the first metal interconnecting layer
Electrical connection；The second conductive plunger in the second dielectric layer of sensor regions top, second conductive plunger and first
Electric connection layer and the second electric connection layer are electrically connected；In the 3rd dielectric layer of sensor regions top the 3rd is conductive slotting
Plug, the 3rd conductive plunger is electrically connected with the second electric connection layer and upper electrode layer.
3. CMOS humidity sensors according to claim 1, it is characterised in that the hanging structure has support arm, fit
In play a part of support hanging structure；The support arm is laminated construction, is at least included：Second dielectric layer, the first electrical connection
Layer, the first metal interconnecting layer, lower electrode layer and first medium layer.
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| CN104627947A (en) | 2015-05-20 |
| CN104627947B (en) | 2016-02-10 |
| CN105480934A (en) | 2016-04-13 |
| CN105366636A (en) | 2016-03-02 |
| CN105366636B (en) | 2017-03-22 |
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