CN104627947A

CN104627947A - CMOS (complementary metal oxide semiconductor) humidity sensor and forming method of CMOS humidity sensor

Info

Publication number: CN104627947A
Application number: CN201510066381.8A
Authority: CN
Inventors: 袁彩雷; 俞挺; 骆兴芳
Original assignee: Jiangxi Normal University
Current assignee: Jiangxi Normal University
Priority date: 2015-02-09
Filing date: 2015-02-09
Publication date: 2015-05-20
Anticipated expiration: 2035-02-09
Also published as: CN105366636A; CN105480934B; CN105366636B; CN105480934A; CN104627947B

Abstract

The invention discloses a CMOS (complementary metal oxide semiconductor) humidity sensor and a forming method of a CMOS humidity sensor, wherein the forming method of the CMOS humidity sensor comprises the steps: using a technique of forming a sub-metal interconnection layer in a MOS (metal oxide semiconductor) appliance and forming a lower electrode layer, a first metal interconnection layer, a first electrical connection layer, a second electrical connection layer and an upper electrode layer of a humidity sensor; and then forming an annular groove and a heat isolating zone in a sensor zone by applying an etching process in a compatible standard CMOS technique and an isotropic etching process; forming a through hole and a trench which are penetrated to each other in the sensor zone; and then forming a humidity sensitivity material filled with the through hole and the trench. The forming technique of the humidity sensor is completely compatible with the forming technique of the MOS appliance, the humidity sensor and the MOS appliance are integrated on the same one chip, thus the chip area is reduced, power consumption is lowered, and integration level and output are improved.

Description

CMOS humidity sensor and forming method thereof

Technical field

The present invention relates to field of semiconductor fabrication technology, particularly a kind of CMOS humidity sensor and forming method thereof.

Background technology

At present, all often need to measure ambient humidity and control in fields such as such as industrial and agricultural production, environmental protection, space flight, in the ambient parameter of routine, humidity is one of parameter of the most difficult Measurement accuracy.

Humidity sensor is, based on its functional material, the physical effect relevant to humidity or chemical reaction manufacture to occur, and it has function humidity physical quantity being converted to the signal of telecommunication.Humidity sensor can be divided into according to the difference of its operation principle: telescopic humidity sensor, utilizes the linear dimension of degreasing hair to change with the change of environment moisture content; Vaporation-type humidity sensor, i.e. wet and dry bulb humidity sensor, utilize dry bulb and the wet-bulb thermometer temperature difference when relative humidity variations change and obtain; Dew-point humidity sensor, utilizes cooling means to make the steam in gas reach capacity and condense, carrys out the relative humidity in measurement gas according to dew-point temperature; Electronic type humidity sensor, comprises resistance-type, condenser type and electrolytic.After capacitance type humidity sensor utilizes wet sensory material to absorb water, dielectric constant changes and changing capacitance, and it has the advantages such as highly sensitive, low in energy consumption, temperature drift is little, thus receives extensive concern.

The signal processing circuit of microsensor and surrounding is integrated, make processing on the same chip, to realize the performance of more function and Geng Gao, reduce the cost of sensor simultaneously, become a new focus and trend that MEMS (Micro-Electro-Mechanical System) develops.By the system integration, humidity sensor and signal processing circuit are close as much as possible, thus reduce parasitic parameter and external disturbance to a great extent; Single chip integrated humidity sensor can also reduce the integrity problem interconnected between different chip.

Therefore, CMOS (Complementary Metal Oxide Semiconductor) technology is utilized to be undertaken on sheet integrated by humidity sensor and signal processing circuit, and the technique forming humidity sensor can not cause harmful effect to signal processing circuit, is study hotspot and the focus of following humidity sensor.Therefore, need a kind of formation method that new humidity sensor is provided badly, simultaneously by humidity sensor and cmos signal processing apparatus on the same chip integrated, and form the technique of humidity sensor and can not cause harmful effect to cmos signal processing apparatus.

Summary of the invention

The problem that the present invention solves is to provide a kind of CMOS humidity sensor and forming method thereof, and the formation process of humidity sensor and the formation process compatibility of MOS device are high, reduces chip area, improves integrated level and output, reduction power consumption and production cost.

For solving the problem, the invention provides a kind of formation method of CMOS humidity sensor, comprise: the substrate comprising MOS device district and sensor regions is provided, described MOS device district section substrate is formed with polysilicon gate, described sensor regions section substrate is formed with polysilicon zone of heating, described substrate is formed with the first medium layer being covered in polycrystalline silicon gate surface and polysilicon heating layer surface; First medium floor surface above MOS device district forms the first sub-metal interconnecting layer be electrically connected with polysilicon gate, first medium layer surface simultaneously above described sensor regions forms the first metal interconnecting layer of some electrically insulated from one another, the first electric connection layer and lower electrode layer, and described first metal interconnecting layer, the first electric connection layer and lower electrode layer are across the boundary of MOS device district and sensor regions, wherein, the first metal interconnecting layer of at least 2 electrically insulated from one another is electrically connected with polysilicon zone of heating; Belong to interconnect layer surfaces at described first interest, the first metal interconnecting layer is surperficial, lower electrode layer is surperficial and first medium layer surface forms second dielectric layer; Second dielectric layer surface above described MOS device district forms the second sub-metal interconnecting layer be electrically connected with polysilicon gate, second dielectric layer surface simultaneously above described sensor regions forms the second metal interconnecting layer and the second electric connection layer, described second electric connection layer is electrically connected with the first electric connection layer, and described second metal interconnecting layer with there is between lower electrode layer relative coincidence face; Belong to interconnect layer surfaces, the second metal interconnecting layer surface, the second electric connection layer surface and second dielectric layer surface at described second interest and form the 3rd dielectric layer; The 3rd dielectric layer surface above described MOS device district forms the 3rd sub-metal interconnecting layer be electrically connected with polysilicon gate, the 3rd dielectric layer surface simultaneously above described sensor regions forms the upper electrode layer be electrically connected with the second electric connection layer, and described upper electrode layer with there is between lower electrode layer relative coincidence face, between described upper electrode layer with described second metal interconnecting layer, there is relative coincidence face; Belong to interconnect layer surfaces, upper electrode layer surface and the 3rd dielectric layer surface at described 3rd interest and form top layer dielectric layer; Etch the substrate of top layer dielectric layer, the 3rd dielectric layer, second dielectric layer, first medium layer and segment thickness successively, annular groove is formed in sensor regions, described annular groove is around the first metal interconnecting layer, the first electric connection layer, lower electrode layer, the second metal interconnecting layer, the second electric connection layer and upper electrode layer, etching removes the top layer dielectric layer, the 3rd dielectric layer and the second dielectric layer that are positioned at above the second metal interconnecting layer successively simultaneously, until expose the second metal interconnecting layer surface, above described second metal interconnecting layer, form through hole; Adopt isotropic etching technique, the substrate side wall surface being positioned at sensor regions exposed along described annular groove etches, etching removes the segment thickness substrate be positioned at below polysilicon zone of heating, above described sensor regions, form hanging structure, and between described hanging structure and the substrate of sensor regions, there is area of insulation; Etching removes described second metal interconnecting layer, below described through hole, form groove; Form the humidity-sensitive material layer of filling full described groove and through hole.

Optionally, be parallel on substrate surface direction, described annular groove is of a size of 1/10 to 2/5 of clear size of opening; Described groove is of a size of 2 times of the size of through hole to 5 times.

Optionally, be parallel on substrate surface direction, described annular groove is of a size of 3 microns to 5 microns; Described through hole is of a size of 10 microns to 50 microns.

Optionally, be parallel on substrate surface direction, the section shape of described upper electrode layer is square or pectination shape.

Optionally, before etching removes described second metal interconnecting layer, described second metal interconnecting layer sidewall is covered by the 3rd dielectric layer; Before etching removes described second metal interconnecting layer, described upper electrode layer sidewall is covered by top layer dielectric layer.

Optionally, while described second electric connection layer of formation, second dielectric layer surface above described sensor regions forms pseudo-metal interconnecting layer, electrically insulated from one another between described pseudo-metal interconnecting layer and the second electric connection layer, described pseudo-metal interconnecting layer is across the boundary of MOS device district and sensor regions, and described pseudo-metal interconnecting layer is positioned at directly over the first metal interconnecting layer, the first electric connection layer.

Optionally, in the process that place forms described annular groove and through hole, when the second metal interconnecting layer surface is exposed, described pseudo-metal interconnecting layer surface is exposed; Remove while described second metal interconnecting layer in etching, described pseudo-metal interconnecting layer is etched removal.

Optionally, described hanging structure has support arm, is suitable for playing the effect supporting hanging structure; Described support arm is laminated construction, at least comprises: be positioned at the second dielectric layer immediately below described pseudo-metal interconnecting layer, the first electric connection layer, the first metal interconnecting layer, lower electrode layer and first medium layer.

Optionally, also comprise step: before described first metal interconnecting layer of formation, form at least some the first conductive plungers be electrically connected with polysilicon zone of heating in first medium layer above described sensor regions, and described first metal interconnecting layer is electrically connected with the first conductive plunger; Before described second metal interconnecting layer of formation and the second electric connection layer, form some the second conductive plungers be electrically connected with the first electric connection layer in second dielectric layer above described sensor regions, and described second conductive plunger is electrically connected with the second electric connection layer be positioned at directly over the first electric connection layer; Before the described upper electrode layer of formation, form some the 3rd conductive plungers be electrically connected with the second electric connection layer in the 3rd dielectric layer above described sensor regions, and described 3rd conductive plunger is electrically connected with upper electrode layer.

Optionally, the material of described humidity-sensitive material layer is polyimides; Spin coating process and annealing in process is adopted to form described humidity-sensitive material layer.

Optionally, the processing step forming described humidity-sensitive material layer comprises: form the humidity-sensitive material layer of filling full described groove and through hole, and described humidity-sensitive material layer is also positioned at top layer dielectric layer surface; Etching removes the humidity-sensitive material layer of described top layer dielectric layer surface.

Optionally, the material of described second metal interconnecting layer is aluminium; Adopt wet corrosion technique etching to remove described second metal interconnecting layer, the liquid that wet corrosion technique adopts is hydrofluoric acid solution or tetramethyl ammonium hydroxide solution.

Optionally, XeF is adopted ₂carry out described isotropic etching technique; The technological parameter of described isotropic etching technique is: circulation is carried out passing into XeF in etching cavity ₂with extraction XeF ₂action, XeF in etching cavity ₂pressure is 100Pa to 180Pa, and passes into XeF in etching cavity ₂rear maintenance 10 seconds to 50 seconds, cycle-index is 5 to 15 times.

Optionally, described sensor regions is the region of humidity sensor to be formed; Described MOS device district is the region of MOS signal processor to be formed.

Optionally, the first oxide layer is also formed with between described polysilicon gate and substrate; Also be formed with the second oxide layer between described polysilicon zone of heating and substrate, wherein, the second oxide layer is formed in technique with the first oxide layer.

The present invention also provides a kind of CMOS humidity sensor, comprise: substrate, described substrate comprises MOS device district and sensor regions, described MOS device district section substrate is formed with polysilicon gate, described sensor regions section substrate is formed with polysilicon zone of heating, described substrate is formed with the first medium layer being covered in polycrystalline silicon gate surface and polysilicon heating layer surface; Be positioned at the first sub-metal interconnecting layer on the first medium floor surface above described MOS device district, described first sub-metal interconnecting layer is electrically connected with polysilicon gate; Be positioned at the first metal interconnecting layer of some electrically insulated from one another on the first medium layer surface above described sensor regions, the first electric connection layer and lower electrode layer, and described first metal interconnecting layer, the first electric connection layer and lower electrode layer are across the boundary of MOS device district and sensor regions, wherein, the first metal interconnecting layer of at least 2 electrically insulated from one another is electrically connected with polysilicon zone of heating; Be positioned at the second dielectric layer that described first interest belongs to interconnect layer surfaces, the first metal interconnecting layer surface, the surperficial and first medium layer surface of lower electrode layer; Be positioned at the second sub-metal interconnecting layer on the second dielectric layer surface above described MOS device district, described second sub-metal interconnecting layer is electrically connected with polysilicon gate; Be positioned at second electric connection layer on the second dielectric layer surface above described sensor regions, described second electric connection layer is electrically connected with the first electric connection layer; Be positioned at described second interest and belong to interconnect layer surfaces, the second electric connection layer surface and the 3rd dielectric layer on second dielectric layer surface; Be positioned at the 3rd sub-metal interconnecting layer of the 3rd dielectric layer surface above described MOS device district, and described 3rd sub-metal interconnecting layer is electrically connected with polysilicon gate; Be positioned at the upper electrode layer be electrically connected with the second electric connection layer of the 3rd dielectric layer surface above described sensor regions, and described upper electrode layer with there is between lower electrode layer relative coincidence face; Be positioned at described 3rd interest and belong to interconnect layer surfaces, upper electrode layer surface and the top layer dielectric layer of the 3rd dielectric layer surface; Be positioned at the top layer dielectric layer of described sensor regions, the 3rd dielectric layer, second dielectric layer, first medium layer and section substrate annular groove, described annular groove is around the first metal interconnecting layer, the first electric connection layer, lower electrode layer, the second electric connection layer and upper electrode layer; Be positioned at the area of insulation of described sensor regions, described area of insulation and annular groove run through mutually, and described area of insulation is between substrate and polysilicon zone of heating; Be positioned at the through hole of the top layer dielectric layer of described sensor regions and the 3rd dielectric layer of segment thickness, and be positioned at the groove of the 3rd dielectric layer of residual thickness, described groove and through hole run through mutually, and described groove with there is between lower electrode layer relative coincidence face, described groove with there is between upper electrode layer relative coincidence face; Fill the humidity-sensitive material layer of full described groove and through hole.

Optionally, also comprise: the first conductive plunger being positioned at first medium layer above described sensor regions, described first conductive plunger is electrically connected with polysilicon zone of heating and the first metal interconnecting layer; Be positioned at the second conductive plunger of second dielectric layer above described sensor regions, described second conductive plunger is electrically connected with the first electric connection layer and the second electric connection layer; Be positioned at the 3rd conductive plunger of the 3rd dielectric layer above described sensor regions, described 3rd conductive plunger is electrically connected with the second electric connection layer and upper electrode layer.

Optionally, described hanging structure has support arm, is suitable for playing the effect supporting hanging structure; Described support arm is laminated construction, at least comprises: second dielectric layer, the first electric connection layer, the first metal interconnecting layer, lower electrode layer and first medium layer.

Compared with prior art, technical scheme of the present invention has the following advantages:

In the technical scheme of the formation method of CMOS humidity sensor provided by the invention, the polysilicon zone of heating of humidity sensor is formed while the polysilicon gate forming MOS device, then, while the sub-metal interconnecting layer forming MOS device, metal interconnecting layer, the first electric connection layer, the second electric connection layer, lower electrode layer and the upper electrode layer needed for humidity sensor is formed; Then, adopt the etching technics in standard CMOS process to carry out etching and form annular groove, above the second metal interconnecting layer, form through hole simultaneously; Then the substrate adopting isotropic etching technique etched rings connected in star to expose, forms hanging structure in sensor regions; Then etch removal second metal interconnecting layer and form groove, form the humidity-sensitive material layer of filling full groove and through hole.In the present invention the formation process of humidity sensor and the formation process of MOS device completely compatible, by MOS device and humidity sensor on the same chip integrated, reduce chip area, improve integrated level and output, reduce power consumption and production cost.Further, the present invention is being parallel on substrate surface direction, annular groove is of a size of 1/10 to 2/5 of clear size of opening, make in formation humidity-sensitive material layer process, humidity-sensitive material layer only fills full through hole, and the amount entering the humidity-sensitive material layer in annular groove lacking very, thus be conducive to the heat dispersion improving CMOS humidity sensor.

Further, the present invention is being parallel on substrate surface direction, groove is of a size of 2 times of the size of through hole to 5 times, make in the process forming humidity-sensitive material layer, humidity-sensitive material layer fills full groove and through hole preferably, improve the wet sensing performance of the humidity-sensitive material layer formed, thus improve the wet-sensitive sensitivity of humidity sensor.

Further, the present invention is while formation second electric connection layer, second dielectric layer surface above sensor regions forms pseudo-metal interconnecting layer, described pseudo-metal interconnecting layer is across the boundary of MOS device district and sensor regions, and described pseudo-metal interconnecting layer is positioned at directly over the first metal interconnecting layer, the first electric connection layer.In the process forming annular groove; etching technics is very little to the etch rate of pseudo-metal interconnecting layer; therefore play the effect of protection below second dielectric layer, the first metal interconnecting layer and the first electric connection layer at described pseudo-metal interconnecting layer, be beneficial to the support arm forming hanging structure.

Simultaneously; due to the protective effect of pseudo-metal interconnecting layer; avoid the first metal interconnecting layer and the first electric connection layer is exposed in the etching process environment of annular groove; correspondingly avoid the first metal interconnecting layer and the first electric connection layer is exposed in external environment; thus make the first metal interconnecting layer and the first electric connection layer keep good electric property, improve the signal of telecommunication accuracy in polysilicon layer and upper electrode layer.

Present invention also offers the CMOS humidity sensor that a kind of structural behaviour is superior, MOS device and humidity sensor on the same chip integrated, chip area is little, and CMOS humidity sensor is low in energy consumption.

Accompanying drawing explanation

The structural representation of the CMOS humidity sensor forming process that Fig. 1 to Figure 25 provides for the embodiment of the present invention.

Detailed description of the invention

From background technology, the manufacture craft of prior art humidity sensor and CMOS technology poor compatibility, the CMOS technology being difficult to employing standard makes humidity sensor.

For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.

With reference to figure 1, provide substrate 100, described substrate 100 comprises MOS device district I and sensor regions II.

The material of described substrate 100 is silicon, germanium, SiGe, carborundum or GaAs, and described substrate 100 can also be the germanium on isolate supports, insulator or the SiGe on insulator.Described substrate 100 surface can also form some epitaxial interface layers or strained layer, to improve the electric property of CMOS humidity sensor.

In the present embodiment, described substrate 100 is silicon substrate.Described MOS device district I is the region of MOS signal processor to be formed, for follow-up formation PMOS transistor, nmos pass transistor or CMOS transistor provide signal processing circuit platform, for detecting or gather the signal of telecommunication in humidity sensor; Described sensor regions II is the region of humidity sensor to be formed, for follow-up formation humidity sensor provides workbench.Isolation structure can also be formed in described MOS device district I substrate 100, described isolation structure can be fleet plough groove isolation structure (STI, Shallow Trench Isolation), the packing material of isolation structure is the insulating materials such as silica, silicon nitride or silicon oxynitride.

Can also form some well regions in MOS device district I substrate 100, the type of described well region is determined according to the type of MOS device to be formed, and the doping type of described well region is N-type doping or the doping of P type.Such as, when part MOS device district I forms nmos pass transistor, then form P type trap zone in corresponding MOS device district I substrate 100, the Doped ions of described P type trap zone is B, Ga or In; When part MOS device district I forms PMOS transistor, then form N-type well region in corresponding MOS device district I substrate 100, the Doped ions of described N-type well region is P, As or Sb.

The present embodiment with a MOS device district I, a sensor regions II exemplarily, the quantity of corresponding follow-up formation humidity sensor is 1, be parallel in substrate 100 surface direction, described sensor regions II is of a size of 10 microns × 10 microns to 50 microns × 50 microns.In other embodiments, the quantity in MOS device district can for the arbitrary natural number being more than or equal to 1, and the quantity of sensor regions also can for the arbitrary natural number being more than or equal to 1, then the quantity of the humidity sensor of corresponding formation is identical with the quantity of sensor regions.

In the present embodiment, follow-up to form PMOS transistor exemplarily in MOS device district I.

With reference to figure 2, form oxide layer on described MOS device district I and sensor regions II surface; Polysilicon layer is formed on described oxide layer surface; The polysilicon layer of graphical described MOS device district I and oxide layer, formed and be positioned at first oxide layer 111 on MOS device district I section substrate 100 surface and be positioned at the polysilicon gate 112 on the first oxide layer 111 surface; The polysilicon layer of graphical described sensor regions II and oxide layer, formed and be positioned at second oxide layer 121 on II section substrate 100 surface, sensor regions and be positioned at the polysilicon zone of heating 122 on the second oxide layer 121 surface.

The material of described oxide layer is silica, adopts chemical vapor deposition method to form described oxide layer; The material of described polysilicon layer is the polysilicon of polysilicon or doping, adopts chemical vapor deposition method to form described polysilicon layer.

In the present embodiment, with in technique, carry out polysilicon layer and the oxide layer of described graphical MOS device district I and sensor regions II.

In the present embodiment, described MOS device district I section substrate 100 forms polysilicon gate 112, and between described polysilicon gate 112 and substrate 100, is formed with the first oxide layer 111; While the described polysilicon gate 112 of formation, described sensor regions II section substrate 100 forms polysilicon zone of heating 122, and is formed with the second oxide layer 121 between described polysilicon zone of heating 122 and substrate 100.

Described first oxide layer 111 and polysilicon gate 112 form the grid structure of MOS device.Described polysilicon zone of heating 122 is as the heating resistor of humidity sensor, joule's heat energy is produced in polysilicon zone of heating 122 when subsequent current flows through polysilicon zone of heating 122, thus the humidity-sensitive material layer of follow-up formation is heated, improve the sensitivity of humidity-sensitive material layer induction humidity, shorten the response time of humidity sensor.

On the direction being parallel to substrate 100 surface, the section shape of described polysilicon zone of heating 122 is square, square waveform, zig-zag, annular or spirality, and wherein, spirality can be square spiral.In the present embodiment, the shape of described polysilicon zone of heating 122 is zig-zag, and the thickness of polysilicon zone of heating 122 is 2 nanometer to 300 nanometers.

After the grid structure forming MOS device, also comprise step: the substrate 100 of grid structure both sides is adulterated, the source region of corresponding formation MOS device and drain region.

With reference to figure 3, form first medium floor 103 at described MOS device district I and sensor regions II substrate 100 surface, described first medium layer 103 is also covered in polysilicon gate 112 surface and polysilicon zone of heating 122 surface.

Described first medium layer 103 is not only covered in polysilicon gate 112 sidewall surfaces, polysilicon zone of heating 122 sidewall surfaces, is also covered in polysilicon gate 112 top surface, polysilicon zone of heating 122 top surface.The material of described first medium layer 103 is insulating materials, can be silica, silicon nitride or silicon oxynitride.

In the present embodiment, adopt chemical vapor deposition method to form described first medium layer 103, the material of first medium layer 103 is silica.

Continue with reference to figure 3, form some first conductive plungers 301 in the first medium layer 103 above described sensor regions II, described first conductive plunger 301 is electrically connected with polysilicon zone of heating 122.

In the present embodiment, the first conductive plunger 301 is formed in first medium floor 103 simultaneously above MOS device district I, the first conductive plunger 301 above MOS device district I is electrically connected with the transistor in MOS signal processor, such as be electrically connected with the source electrode of transistor, drain electrode or polysilicon gate 112, the first conductive plunger 301 above MOS device district I is also electrically connected with the first metal interconnecting layer of the follow-up formation of MOS device district I.

At least 2 the first conductive plungers 301 above the II of sensor regions are electrically connected with polysilicon zone of heating 122, electric current is provided to polysilicon zone of heating 122 by the first conductive plunger 301, to make to produce joule's heat energy in polysilicon zone of heating 122, the first conductive plunger 301 above the II of sensor regions is also electrically connected with the first metal interconnecting layer of the follow-up formation of sensor regions II.

In a specific embodiment, the processing step forming described first conductive plunger 301 comprises: form graph layer on described first medium layer 103 surface; With described graph layer for first medium layer 103 described in mask etching, some first conductive through holes are formed in described first medium layer 103, the first conductive through hole being positioned at MOS device district exposes the source electrode of transistor, drain electrode and polysilicon gate 112 surface, and the first conductive through hole bottom-exposed being positioned at sensor regions II goes out polysilicon zone of heating 122 surface; Form first conductive plunger 301 of filling full described first conductive through hole, and described first conductive plunger 301 top flushes with first medium layer 103 top.

The material of described first conductive plunger 301 is metal, and the material of such as the first conductive plunger 301 can be copper, aluminium or tungsten.

With reference to figure 4 to Fig. 6, Fig. 4 is top view, Fig. 5 is the cross-sectional view of Fig. 4 along line of cut AA1, Fig. 6 is the cross-sectional view of Fig. 4 along line of cut BB1, first medium layer 103 surface above described sensor regions II forms the first metal interconnecting layer 401, first electric connection layer 421 and lower electrode layer 411 of some electrically insulated from one another, wherein, the first metal interconnecting layer 401 of at least 2 electrically insulated from one another is electrically connected with polysilicon zone of heating 122.

Described lower electrode layer 411, first electric connection layer 421 is identical with the material of the first metal interconnecting layer 401, and utilization is formed with technique.The material of described first metal interconnecting layer 401 is metal, and such as the material of the first metal interconnecting layer 401 is copper, aluminium or tungsten; The material of described lower electrode layer 411 is metal, and the material of such as lower electrode layer 411 is copper, aluminium or tungsten.

And in the present embodiment, form the first metal interconnecting layer 401 above the II of sensor regions while, above MOS device district I, also form the first sub-metal interconnecting layer 431 be electrically connected with polysilicon gate 112.The the first sub-metal interconnecting layer 431 be positioned at above MOS device district I is electrically connected with polysilicon gate 112, and concrete makes the first sub-metal interconnecting layer 431 be electrically connected with polysilicon gate 112 by the first conductive plunger 301.

Described lower electrode layer 411 is the lower electrode plate of the capacitor of follow-up formation, and described lower electrode layer 411 is also positioned at MOS device district I part first medium floor 103 surface, namely described lower electrode layer 411 has a common boundary across MOS device district I and sensor regions II, thus make lower electrode layer 411 as a part for the support arm of follow-up formation, and described lower electrode layer 411 is accessed in MOS signal processing circuit.

The first metal interconnecting layer 401 be positioned at above the II of sensor regions is electrically connected with polysilicon zone of heating 122 by the first conductive plunger 301, and the first metal interconnecting layer 401 electrically insulated from one another be electrically connected with described polysilicon zone of heating 122, subsequent current is made to flow in polysilicon zone of heating 122 via one first metal interconnecting layer 401, then flow out via another first metal interconnecting layer 401, to make electric current flow through from polysilicon zone of heating 122, and then make to produce joule's heat energy in polysilicon zone of heating 122.Described first electric connection layer 421 is electrically connected with the upper electrode layer of follow-up formation, by the first electric connection layer 421, upper electrode layer is accessed in MOS signal processing circuit, and upper electrode layer and lower electrode layer 411 electrically insulated from one another.

In the present embodiment, first metal interconnecting layer 401 is also positioned at part first medium floor 103 surface of MOS device district I, namely the first metal interconnecting layer 401 has a common boundary across MOS device district I and sensor regions II, thus make described first metal interconnecting layer 401 as a part for the support arm of follow-up formation, can also the first metal interconnecting layer 401 be passed through, polysilicon zone of heating 122 is accessed in MOS signal processing circuit.

Same, first electric connection layer 421 is also across the boundary of MOS device district I and sensor regions II, thus make described first electric connection layer 421 as a part for the support arm of follow-up formation, electric pole plate can also be accessed in MOS signal processing circuit by the first electric connection layer 421.

Described first metal interconnecting layer 401, first electric connection layer 421, first sub-metal interconnecting layer 431 and lower electrode layer 411 is made by deposition, etching technics.

With reference to figure 7 to Fig. 9, Fig. 7 is top view, Fig. 8 is the cross-sectional view of Fig. 7 along line of cut AA1, Fig. 9 is the cross-sectional view of Fig. 7 along line of cut BB1, is formed and is covered in described first medium layer 103 surface, the first sub-metal interconnecting layer 431, first metal interconnecting layer 401 is surperficial, the first electric connection layer 421 is surperficial and the second dielectric layer 104 on lower electrode layer 411 surface; Form some second conductive plungers 302 in second dielectric layer 104 above the II of sensor regions, and described second conductive plunger 302 is electrically connected with the first electric connection layer 421; Form the second conductive plunger 302 in second dielectric layer 104 simultaneously above device region I, described second conductive plunger 302 is electrically connected with polysilicon gate 122.

The material of described second dielectric layer 104 is insulating materials, and chemical vapour deposition (CVD), physical vapour deposition (PVD) or atom layer deposition process can be adopted to form described second dielectric layer 104.Described second dielectric layer 104 top surface is higher than the first metal interconnecting layer 401 top surface.

Be positioned at the second conductive plunger 302 above the II of sensor regions and lower electrode layer 411, polysilicon zone of heating 122 electrically insulated from one another, and the second conductive plunger 302 be positioned at above the II of sensor regions is electrically connected with the first electric connection layer 421, the upper electrode layer of follow-up formation is made to access to MOS signal processing circuit subsequently through described first electric connection layer 421.

The formation method of described second conductive plunger 302 can with reference to the formation method of aforementioned first conductive plunger 301.

With reference to figures 10 to Figure 12, Figure 10 is top view, Figure 11 is the cross-sectional view of Figure 10 along line of cut AA1, Figure 12 is the cross-sectional view of Figure 10 along line of cut BB1, second dielectric layer 104 surface above described sensor regions II forms the second metal interconnecting layer 402 and the second electric connection layer 422, described second electric connection layer 422 is electrically connected with the first electric connection layer 421, and described second metal interconnecting layer 402 has relative coincidence face with between lower electrode layer 411.

There is relative coincidence face refer to: the figure that the second metal interconnecting layer 402 is projected on substrate 100 surface, the figure being projected on substrate 100 surface with lower electrode layer 411 have the part overlapped.

In the present embodiment, the second conductive plunger 302 being positioned at sensor regions II is electrically connected with the second electric connection layer 422, is realized the electrical connection of the first electric connection layer 421 and the second electric connection layer 422 by described second conductive plunger 302.

In the present embodiment, form the second sub-metal interconnecting layer 432 on second dielectric layer 104 surface of MOS device district I, and the second sub-metal interconnecting layer 432 above MOS device district I is electrically connected with polysilicon gate 112 simultaneously.

The present embodiment is while described second metal interconnecting layer 402 of formation and the second electric connection layer 422, second dielectric layer 104 surface also above the II of sensor regions forms pseudo-metal interconnecting layer 412, described pseudo-metal interconnecting layer 412 and the second electric connection layer 422 electrically insulated from one another, and described pseudo-metal interconnecting layer 412 is across the boundary of MOS device district I and sensor regions II.

And described pseudo-metal interconnecting layer 412 is positioned at directly over the first metal interconnecting layer 401, first electric connection layer 421.Formed in the technical process of annular groove in subsequent etching; can etch and expose pseudo-metal interconnecting layer 412 surface; and the etch rate of described etching technics to pseudo-metal interconnecting layer 412 is very little; therefore formed in etching in the process of annular groove; described pseudo-metal interconnecting layer 412 plays the effect of protection first metal interconnecting layer 401 and the first electric connection layer 421; prevent the first metal interconnecting layer 401 and the first electric connection layer 421 to be exposed in external environment, thus avoid the signal of telecommunication in the upper electrode layer of polysilicon zone of heating 122 and follow-up formation to be subject to external interference.And; due to rear extended meeting etching removal second metal interconnecting layer 401; the second dielectric layer 104 be positioned in the present embodiment immediately below pseudo-metal interconnecting layer 401 plays the effect of protection first metal interconnecting layer 401 and the first electric connection layer 421, prevents the first metal interconnecting layer 401 and the first electric connection layer 421 to be etched removal.

The second electric connection layer 422 be positioned in the present embodiment directly over the first electric connection layer 421 is electrically connected with the first electric connection layer 421, and is positioned at the second electric connection layer 422 and the first electric connection layer 421 electric insulation directly over the first metal interconnecting layer 401.

Described second metal interconnecting layer 402 is identical with the material of the second electric connection layer 422.In the present embodiment, the material of described second metal interconnecting layer 402 is aluminium.

Rear extended meeting etching removal second metal interconnecting layer 402, then humidity-sensitive material layer is filled, therefore the position of described second metal interconnecting layer 402 is the position of the part humidity-sensitive material layer of follow-up formation, described second metal interconnecting layer 402 has relative coincidence face with between lower electrode layer 411 for this reason, when in environment, moisture content changes, the relative dielectric coefficient of the dielectric layer between the upper electrode layer of lower electrode layer 411 and follow-up formation changes, thus the capacitance between lower electrode layer 411 and upper electrode layer is changed, to obtain the humidity in environment.

With reference to figures 13 to Figure 15, Figure 13 is top view, Figure 14 is the cross-sectional view of Figure 13 along line of cut AA1, Figure 15 is the cross-sectional view of Figure 13 along line of cut BB1, forms the 3rd dielectric layer 105 on described second sub-metal interconnecting layer 432, second metal interconnecting layer 402, second electric connection layer 422, pseudo-metal interconnecting layer 412 and second dielectric layer 104 surface; The 3rd dielectric layer 105 surface above described sensor regions II forms the upper electrode layer 423 be electrically connected with the second electric connection layer 422, and described upper electrode layer 423 has relative coincidence face with between lower electrode layer 411, between described upper electrode layer 423 with described second metal interconnecting layer 402, there is relative coincidence face.

In the present embodiment, while formation upper electrode layer 423, the 3rd dielectric layer 104 surface above described MOS device district I forms the 3rd sub-metal interconnecting layer 433 be electrically connected with polysilicon gate 112.

Before the described upper electrode layer 423 of formation, form some the 3rd conductive plungers 303 be electrically connected with the second electric connection layer 422 in the 3rd dielectric layer 104 above described sensor regions II, and described 3rd conductive plunger 303 is electrically connected with upper electrode layer 423; Form the 3rd conductive plunger 303 be electrically connected with the second sub-metal interconnecting layer 432 in the 3rd dielectric layer 105 simultaneously above MOS device district I, described 3rd sub-metal interconnecting layer 433 is electrically connected with the second sub-metal interconnecting layer 432.

Described upper electrode layer 423 is as the electric pole plate of capacitor, by the 3rd conductive plunger 303, the second electric connection layer 422 be electrically connected with described 3rd conductive plunger 303, the second conductive plunger 302 be electrically connected with described second electric connection layer 422, the first electric connection layer 421 of being electrically connected with described second conductive plunger 302, upper electrode layer 423 is accessed in MOS signal processing circuit.

Described upper electrode layer 423 has relative coincidence face with between lower electrode layer 411, between described upper electrode layer 423 with described second metal interconnecting layer 402, there is relative coincidence face, thus make, between upper electrode layer 423, second metal interconnecting layer 402, lower electrode layer 411 three, there is relative coincidence face, when environment moisture content changes, the relative dielectric coefficient of the dielectric layer between upper electrode layer 423 and lower electrode layer 411 changes, thus the capacitance between upper electrode layer 423 and lower electrode layer 411 is changed.

In the present embodiment, be parallel in described substrate 100 surface direction, the shape of described upper electrode layer 423 is pectination, described upper electrode layer 423 comprises Part I and Part I is electrically connected and the some discrete Part II of parallel distribution, expose the 3rd dielectric layer 105 surface between adjacent second portions, the present embodiment comprises 2 Part II for upper electrode layer 423.In other embodiments, be parallel on substrate surface direction, the section shape of described upper electrode layer also can be square, circular or fold-line-shaped.

Described upper electrode layer 423 is identical with the material of the 3rd sub-metal interconnecting layer 433, is copper, aluminium or tungsten, and utilization forms described upper electrode layer 423 and the 3rd sub-metal interconnecting layer 433 with processing step.

Unless otherwise noted, the schematic diagram that subsequent technique process provides is the schematic diagram carried out on Figure 15 basis.

With reference to Figure 16, on described 3rd dielectric layer 105 surface, upper electrode layer 423 surface and the 3rd sub-metal interconnecting layer 433 surface form the 4th dielectric layer 106; The 4th conductive plunger 304 be electrically connected with polysilicon gate 112 is formed in the 4th dielectric layer 106 above described MOS device district I; The 4th dielectric layer 106 surface above described MOS device district I forms the top-level metallic interconnection layer 404 be electrically connected with the 4th conductive plunger 304; Form the top layer dielectric layer 107 being covered in top-level metallic interconnection layer 404 surface and the 4th dielectric layer 106 surface.

About the formation method of the 4th dielectric layer 106, the 4th conductive plunger 304, top-level metallic interconnection layer 404 and top layer dielectric layer 107 with reference to aforementioned explanation, can not repeat them here.

The present embodiment is before the described top layer dielectric layer 107 of formation, yet forms both the 4th dielectric layer 106, in other embodiments, if MOS device district is without the need to forming the 4th sub-metal interconnecting layer, then directly belong to interconnect layer surfaces and upper electrode layer surface forms top layer dielectric layer at the 3rd dielectric layer surface, the 3rd interest.

With reference to Figure 17, form photoresist layer 108 on described top layer dielectric layer 107 surface, described photoresist layer 108 has the annular opening 112 be positioned at above the II of sensor regions.

The figure that the photoresist layer 108 that described annular opening 112 surrounds is projected on substrate 100 surface is the 4th figure, the figure that described polysilicon zone of heating 122 is projected on substrate 100 surface is the 5th figure, the border of described 5th figure is covered by the 4th figure, thus prevents polysilicon zone of heating 122 to be exposed in follow-up isotropic etching process environments.The figure that described upper electrode layer 423 is projected on substrate 100 surface is the 6th figure, and described 6th figure is covered by the 4th figure, thus prevents upper electrode layer 423 to be exposed in follow-up dry etching environment, avoids upper electrode layer 423 to be exposed in external environment.

And; in the present embodiment; described annular opening 112 is positioned at directly over pseudo-metal interconnecting layer 412; subsequent etching is made to be formed in the process of annular groove; pseudo-metal interconnecting layer 412 plays the effect of protection first metal interconnecting layer 401 and the first electric connection layer 421, is beneficial to the support arm of follow-up formation hanging structure.

Described photoresist layer 108 is the mask of the substrate 100 of subsequent etching top layer dielectric layer the 107, the 4th dielectric layer 106, the 3rd dielectric layer 105, second dielectric layer 104, first medium layer 103 and segment thickness, prepares for forming hanging structure.

The size of described annular opening 112 is relevant with the area of insulation size of follow-up formation, if annular opening 112 is oversize, then the volume shared by the area of insulation of follow-up formation is comparatively large, causes the chip area formed needed for CMOS humidity sensor large; If annular opening 112 is undersized, then the volume shared by the area of insulation of follow-up formation is little, and the heat causing polysilicon zone of heating 122 to produce easily is passed to undesirably region, the response time delay of CMOS humidity sensor.

And, if annular opening 112 is undersized, then the size of the annular groove of corresponding follow-up formation is also less, and when substrate 100 sidewall surfaces adopting isotropic etching technique etched rings connected in star to expose, the difficulty that etching gas arrives described substrate 100 sidewall surfaces increases.Simultaneously, if annular opening 112 is oversize, then the size of the annular groove of corresponding follow-up formation is also larger, when forming humidity-sensitive material layer, the amount entering the humidity-sensitive material of annular groove is larger, the heat causing polysilicon zone of heating 122 to produce not easily spreads out, and the heat dispersion of CMOS humidity sensor is poor.

For this reason, in the present embodiment, be parallel in substrate 100 surface direction, described annular opening 112 is of a size of 3 microns to 5 microns.

In the present embodiment, also have sub-opening 113 in described photoresist layer 108, described sub-opening 113 is positioned at the top of the second metal interconnecting layer 402, and the size of described sub-opening 113 is less than the size of the second metal interconnecting layer 402.

Follow-uply to etch along described sub-opening 113, until expose the second metal interconnecting layer 402 surface.If sub-opening 113 is undersized, then the ability of follow-up filling humidity-sensitive material layer is excessively weak.

For this reason, in the present embodiment, be parallel in substrate 100 surface direction, described sub-opening 113 is of a size of 10 microns to 50 microns.

With reference to Figure 18 and Figure 19, Figure 18 is the cross-sectional view on Figure 17 basis, Figure 19 is that Figure 13 is along the cross-sectional view on the basis that line of cut CC1 cuts, with described photoresist layer 108 for mask, the top layer dielectric layer 107 exposed along described annular opening 112 (with reference to Figure 17) etches, until etching removes the substrate 100 of segment thickness, above described sensor regions II, form annular groove 109; The top layer dielectric layer 107 simultaneously exposed along sub-opening 113 etches, until expose the second metal interconnecting layer 402 surface, above described second metal interconnecting layer 402, forms through hole 110.

Concrete, adopt dry etch process, etch top layer dielectric layer the 107, the 4th dielectric layer 106, the 3rd dielectric layer 105, second dielectric layer 104 and first medium layer 103 successively, form described annular groove 109; Adopt dry etch process, top layer dielectric layer 107, the 4th dielectric layer 106 and the 3rd dielectric layer 105, form described through hole 110 successively.

The etch rate of described dry etch process to the second metal interconnecting layer 402, first electric connection layer 421, first metal interconnecting layer 401, lower electrode layer 411 is very little, and very large to the etch rate of top layer dielectric layer 107, the 4th dielectric layer 106, the 3rd dielectric layer 105, second dielectric layer 104 and first medium layer 103.

Because the pseudo-metal interconnecting layer 412 of sensor regions II is across the boundary of MOS device district I and sensor regions II, the etch rate of dry etch process to pseudo-metal interconnecting layer 412 is very little, and therefore dry etch process can not cause etching to second dielectric layer 104, first metal interconnecting layer 401, first electric connection layer 421 immediately below pseudo-metal interconnecting layer 421.

And, avoiding the second electric connection layer 422, first metal interconnecting layer 401 and the first electric connection layer 421 is exposed in etching environment, thus the signal of telecommunication degree of accuracy improved in polysilicon zone of heating 122 and upper electrode layer 413, avoid the second electric connection layer 422, first metal interconnecting layer 402 and the first electric connection layer 421 to be exposed to subsequent etching and remove in the etching environment of the second metal interconnecting layer 402.

The thickness of the substrate 100 that described employing dry etch process etching is removed is relevant with the size of the area of insulation of follow-up formation, if substrate 100 is etched, the thickness removed is too small, then area of insulation undersized of corresponding follow-up formation, distance between the hanging structure of follow-up formation and substrate 100 is too small, and the heat in described polysilicon zone of heating 122 not easily discharges; If substrate 100 is etched, the thickness removed is excessive, then the thickness of corresponding remaining substrate 100 is very little, easily causes polysilicon zone of heating 122 to be subject to effect of stress excessively strong, causes polysilicon zone of heating 122 that serious deformation occurs.Further, if substrate 100 is etched, the thickness of removal is excessive, then the substrate 100 of the corresponding follow-up sensor regions II when carrying out isotropic etching technique can be worn by quarter.

Amid all these factors consider, substrate 100 be etched remove thickness be 1/30 to 1/3 of substrate 100 original depth, such as, substrate 100 be etched remove thickness can for substrate 100 original depth 1/10 or 1/5.

In the present embodiment, substrate 100 thickness that described employing dry etch process etching is removed is 5 microns to 10 microns, such as, can be 6 microns or 8 microns; Also can think, perpendicular in substrate 100 surface direction, substrate 100 side wall dimensions that described annular groove 109 exposes is 5 microns to 10 microns.

In the present embodiment, the thickness of dielectric layer is 8 microns to 12 microns, and described dielectric layer is: first medium layer 103, be positioned at first medium layer 103 surface second dielectric layer 104, be positioned at second dielectric layer 104 surface the 3rd dielectric layer 105, be positioned at the 4th dielectric layer 106 on the 3rd dielectric layer 105 surface and be positioned at the top layer dielectric layer 107 on the 4th dielectric layer 106 surface; Be parallel in substrate 100 surface direction, described annular groove 109 is of a size of 3 microns to 5 microns.

In the present embodiment, the sidewall surfaces of described annular groove 109 is perpendicular to substrate 100 surface; In other embodiments, perpendicular in substrate 100 surface direction, the section shape of described annular groove 109 can also be inverted trapezoidal, annular groove 109 top dimension is made to be greater than annular groove 109 bottom size, thus make the etching gas of follow-up isotropic etching technique more easily enter the bottom of annular groove 109, thus substrate 100 sidewall surfaces that annular groove 109 exposes is etched.

Because rear extended meeting fills humidity-sensitive material layer in through hole 110, and avoid the formation of humidity-sensitive material in humidity-sensitive material layer process as far as possible and enter in annular groove 109, in the present embodiment, be parallel in substrate 100 surface direction, described annular groove 109 is of a size of 1/10 to 2/5 of the size of through hole 110.

In a specific embodiment, be parallel in substrate 100 surface direction, described annular groove 109 is of a size of 3 microns to 5 microns, and described through hole 110 is of a size of 10 microns to 50 microns.When described annular groove 109 is of a size of 4 microns, when described through hole 110 is of a size of 25 microns, the performance of the humidity-sensitive material layer that follow-up filling is formed is best, and can effectively avoid the material of humidity-sensitive material layer to enter in annular groove 109.

With reference to Figure 20 and Figure 21, Figure 20 is the schematic diagram on Figure 18 basis, Figure 21 is the schematic diagram on Figure 19 basis, adopt isotropic etching technique, substrate 100 sidewall surfaces exposed along described annular groove 109 etches, above the II of sensor regions, form hanging structure, there is between described hanging structure and substrate 100 area of insulation 114.

In the present embodiment, adopt XeF ₂carry out described isotropic etching technique, due to XeF ₂for dry etching, and XeF ₂etching technics for chemically to etch, the ion dam age that Ions Bombardment can be avoided to bring and the problem of charge accumulated.Further, XeF ₂only substrate 100 is etched, and it is very little even negligible to the etch rate of dielectric layer, metal interconnecting layer, therefore described isotropic etching technique has no adverse effects to MOS device district I, and the technique and the standard CMOS process that therefore form hanging structure in the present embodiment are completely compatible.

Be parallel in substrate 100 surface direction, described area of insulation 114 is of a size of 10 microns to 50 microns, such as, be 15 microns, 20 microns, 25 microns or 35 microns.

In a specific embodiment, XeF is adopted ₂the technological parameter carrying out isotropic etching technique is: circulation is carried out passing into XeF in etching cavity ₂with extraction XeF ₂action, XeF in etching cavity ₂pressure is 100Pa to 180Pa, and passes into XeF in etching cavity ₂rear maintenance 10 seconds to 50 seconds, cycle-index is 5 to 15 times.

Such as, XeF in etching cavity ₂pressure can be 120Pa, 140Pa or 150Pa, in etching cavity, pass into XeF ₂rear maintenance 15 seconds, 20 seconds or 30 seconds.

Due to XeF ₂for isotropic etching technique, therefore formed in the process of hanging structure in etching, described isotropic etching technique both can substrate 100 immediately below etch polysilicon zone of heating 122, also can etch the substrate 100 being positioned at device region I.Reference Figure 22 and Figure 23, Figure 22 are the schematic diagram on Figure 20 basis, and Figure 23 is the schematic diagram on Figure 21 basis, and etching removes described second metal interconnecting layer 402 (with reference to Figure 20,21).

After the described area of insulation 114 of formation, also comprise step: wet etching removes the second metal interconnecting layer 402 be positioned at below through hole 110, form the groove 116 be positioned at below described through hole 110.In the present embodiment, the material of the second metal interconnecting layer 402 is aluminium, adopts the second metal interconnecting layer 402 described in hydrofluoric acid solution erosion removal.The size of described groove 116 and the measure-alike of the second metal interconnecting layer 402.

In other embodiments, tetramethyl ammonium hydroxide solution also can be adopted to etch and to remove described second metal interconnecting layer 402; Described area of insulation 114 can also be formed after formation groove 116.

Because pseudo-metal interconnecting layer 412 (with reference to Figure 20,21) is exposed in described etching environment, therefore while etching removes described second metal interconnecting layer 402, etching removes described pseudo-metal interconnecting layer 412.And second dielectric layer 104, first electric connection layer 421, first metal interconnecting layer 401 be positioned at immediately below described pseudo-metal interconnecting layer 412 all can not be etched.

In the present embodiment, described hanging structure has support arm, is suitable for playing the effect supporting hanging structure; Described support arm is laminated construction, at least comprises: be positioned at second dielectric layer 104, first electric connection layer 421, first metal interconnecting layer 401 immediately below described pseudo-metal interconnecting layer 412 and lower electrode layer 411, first medium layer 103.Because the first metal interconnecting layer 401, first electric connection layer 421 is covered by second dielectric layer 104, thus reduce the first metal interconnecting layer 401 and the first electric connection layer 421 is oxidized or corrosion probability.

Also can fill full humidity-sensitive material layer due to follow-up in groove 116, in order to improve the filling effect of humidity-sensitive material layer, in the present embodiment, be parallel in substrate 100 surface direction, described groove 116 is of a size of 2 times of the size of through hole 110 to 5 times.

In a specific embodiment, be parallel in substrate 100 surface direction, described through hole 110 is of a size of 10 microns to 50 microns, and described groove 116 is of a size of 20 microns to 200 microns.

When annular groove 109 is of a size of 4 microns, through hole 110 is of a size of 25 microns, when groove 116 is of a size of 80 microns, the filling effect of humidity-sensitive material layer to groove 116 and through hole 110 of follow-up formation is good, thus make the ability of the humidity-sensitive material layer induction steam formed optimum, and effectively avoid humidity-sensitive material layer to enter in annular groove 109, thus make the good heat dissipation effect of CMOS humidity sensor.

After described second metal interconnecting layer 402 of removal, remove described photoresist layer 108 (with reference to Figure 18).

With reference to Figure 24, Figure 24 is the schematic diagram on Figure 22 basis, adopt spin coating process to form the humidity-sensitive material layer 115 of the full described groove 116 (with reference to Figure 22) of filling and through hole 110 (with reference to Figure 22), described humidity-sensitive material layer 115 is also positioned at top layer dielectric layer 107 surface.

Humidity-sensitive material layer 115 is a part for the capacitor dielectric between upper electrode layer 423 and lower electrode layer 411, absorb the steam in external environment when humidity-sensitive material layer 114 after, the relative dielectric coefficient of humidity-sensitive material layer 115 can change, thus the capacitance of the capacitor making electric pole plate 423 and lower electrode plate 411 form changes, by measuring the change of capacitance, the moisture content in external environment can be obtained, and obtain the humidity of external environment.

In the present embodiment, the material of described humidity-sensitive material layer 115 is polyimides, adopts spin coating process to form described humidity-sensitive material layer 115.

Concrete, first, dropper is adopted to drip appropriate poly-phthalein amino acid solution to top layer dielectric layer 107 surface, and ensure that poly-phthalein amino acid solution does not enter annular groove 109, then, adopt the first rotating speed poly-phthalein amino acid to be coated in uniformly top layer dielectric layer 107 surface, simultaneously poly-phthalein amino acid and enter through hole 110 and groove 116, then adopt the second rotating speed to enter spin coating process, described second rotating speed is greater than the first rotating speed, forms the sub-sorrel of polyamides.The benefit done like this is: poly-phthalein amino acid can be made to fill full through hole 110 and groove 116, and do not enter in annular groove 109 as far as possible.Then, the sub-sorrel of polyamides is heated, make the sub-sorrel of polyamides be converted into humidity-sensitive material layer 115.Described first rotating speed is 1000 revs/min to 1600 revs/min, and described second rotating speed is 5000 revs/min to 6500 revs/min.In a specific embodiment, described first rotating speed is 1250 revs/min, and when described second rotating speed is 5600 revs/min, the filling effect of the humidity-sensitive material layer 115 in groove 116 and through hole 110 is good, and the wet sensing performance of the humidity-sensitive material layer 115 formed is excellent.

In order to improve the wet sensing performance of the humidity-sensitive material layer 115 of formation, prevent humidity-sensitive material layer 115 from breaking in particular during a heating process, the process of heating was: first rise to 200 degrees Celsius with the speed of 20 degrees Celsius/point from room temperature, 200 degrees Celsius of insulations 20 minutes; Then with the speed of 5 degrees Celsius/point thus 200 degrees Celsius rise to 300 degrees Celsius, 300 degrees Celsius insulation 1 hour.

In a specific embodiment, be parallel in substrate 100 surface direction, described through hole 110 is of a size of 10 microns to 50 microns, described groove 116 is of a size of 20 microns to 200 microns, adopt rational annular groove 109 size, groove 116 size and through hole 110 size, humidity-sensitive material layer 115 is made to fill preferably full groove 116 and through hole 110, and the amount entering to annular groove 109 lacking very, effectively raise the heat dispersion of CMOS humidity sensor.

Spin coating process is one of standard CMOS process, and the technique and the standard CMOS process that therefore form humidity-sensitive material layer 115 in the present embodiment are completely compatible, effectively reduce production cost.

With reference to Figure 25, etching removes the humidity-sensitive material layer 115 being positioned at top layer dielectric layer 107 surface.Etching removes the humidity-sensitive material layer 115 being positioned at top layer dielectric layer 107 surface, makes humidity-sensitive material layer 115 only fill full groove 116 (with reference to Figure 23) and through hole 110 (with reference to Figure 23).And, in the aforementioned process adopting spin coating process formation humidity-sensitive material layer 115, having a small amount of humidity-sensitive material layer 115 enters in annular groove 109, and described reactive ion etching process also can etch the humidity-sensitive material layer 115 entered described in removal in annular groove 109.

In one embodiment, adopt reactive ion etching process, the gas that reactive ion etching adopts is O ₂, CF ₄or N ₂.

In the present embodiment, while making cmos signal processing apparatus, utilize standard CMOS process to make and form CMOS humidity sensor, humidity sensor and cmos signal processing apparatus are integrated on same wafer.

Define hanging structure at sensor regions II in the present embodiment simultaneously, make the utilization rate of humidity sensor to the heat in polysilicon zone of heating 122 higher, thus accelerate the response time of humidity sensor.

The embodiment of the present invention provides a kind of CMOS humidity sensor, in conjunction with reference Figure 14 and with reference to Figure 25, comprising:

Substrate 100, described substrate 100 comprises MOS device district I and sensor regions II, described MOS device district I section substrate 100 is formed with polysilicon gate 112, described sensor regions II section substrate 100 is formed with polysilicon zone of heating 122, described substrate 100 is formed with the first medium layer 103 being covered in polysilicon gate 112 surface and polysilicon zone of heating 122 surface;

Be positioned at the first sub-metal interconnecting layer 431 on first medium floor 103 surface above described MOS device district I, described first sub-metal interconnecting layer 431 is electrically connected with polysilicon gate 112;

Be positioned at the first metal interconnecting layer 401, first electric connection layer 421 and lower electrode layer 411 of some electrically insulated from one another on first medium layer 103 surface above described sensor regions II, and described first metal interconnecting layer 401, first electric connection layer 421 and lower electrode layer 411 are across the boundary of MOS device district I and sensor regions II, wherein, the first metal interconnecting layer 401 of at least 2 electrically insulated from one another is electrically connected with polysilicon zone of heating 122;

Be positioned at described first sub-metal interconnecting layer 431 surface, the first metal interconnecting layer 401 is surperficial, lower electrode layer 411 is surperficial and the second dielectric layer 104 on first medium layer 103 surface;

Be positioned at the second sub-metal interconnecting layer 432 on second dielectric layer 104 surface above described MOS device district I, described second sub-metal interconnecting layer 432 is electrically connected with polysilicon gate 112;

Be positioned at second electric connection layer 422 on second dielectric layer 104 surface above described sensor regions II, described second electric connection layer 422 is electrically connected with the first electric connection layer 421;

Be positioned at the 3rd dielectric layer 105 on described second sub-metal interconnecting layer 432 surface, the second electric connection layer 422 surface and second dielectric layer 104 surface;

Be positioned at the 3rd sub-metal interconnecting layer 433 on the 3rd dielectric layer 105 surface above described MOS device district I, and described 3rd sub-metal interconnecting layer 433 is electrically connected with polysilicon gate 112;

Be positioned at the upper electrode layer 423 be electrically connected with the second electric connection layer 422 on the 3rd dielectric layer 105 surface above described sensor regions II, and between described upper electrode layer 423 with lower electrode layer 411, there is relative coincidence face;

Be positioned at the top layer dielectric layer 107 on described 3rd sub-metal interconnecting layer 433 surface, upper electrode layer 423 surface and the 3rd dielectric layer 105 surface;

Be positioned at the top layer dielectric layer 107 of described sensor regions II, the 3rd dielectric layer 105, second dielectric layer 104, first medium layer 103 and section substrate 100 annular groove 109, described annular groove 109 is around the first metal interconnecting layer 401, first electric connection layer 421, lower electrode layer 411, second electric connection layer 422 and upper electrode layer 423;

Be positioned at the area of insulation 114 of described sensor regions II, described area of insulation 114 runs through mutually with annular groove 109, and described area of insulation 114 is between substrate 100 and polysilicon zone of heating 122; Be positioned at the through hole of the top layer dielectric layer 107 of described sensor regions II and the 3rd dielectric layer 105 of segment thickness, and be positioned at the groove of the 3rd dielectric layer 105 of residual thickness, described groove and through hole run through mutually, and between described groove with lower electrode layer 411, there is relative coincidence face, between described groove with upper electrode layer 423, there is relative coincidence face;

Fill the humidity-sensitive material layer 115 of full described groove and through hole.

It should be noted that, not shown annular groove 109, area of insulation 114 and top layer dielectric layer 107 in Figure 14.

In the present embodiment, between top layer dielectric layer 107 and the 3rd dielectric layer 105, be also formed with the 4th dielectric layer 106.

Also comprise: the first conductive plunger 301 being positioned at first medium layer 103 above described sensor regions II, described first conductive plunger 301 is electrically connected with polysilicon zone of heating 122 and the first metal interconnecting layer 401; Be positioned at the second conductive plunger 302 of second dielectric layer 104 above described sensor regions II, described second conductive plunger 302 is electrically connected with the first electric connection layer 421 and the second electric connection layer 422; Be positioned at the 3rd conductive plunger 303 of the 3rd dielectric layer 105 above described sensor regions II, described 3rd conductive plunger 303 is electrically connected with the second electric connection layer 422 and upper electrode layer 423.

Described hanging structure has support arm, is suitable for playing the effect supporting hanging structure; Described support arm is laminated construction, at least comprises: second dielectric layer 104, first electric connection layer 421, first metal interconnecting layer 401, lower electrode layer 411 and first medium layer 103.

Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.

Claims

1. a formation method for CMOS humidity sensor, is characterized in that, comprising:

The substrate comprising MOS device district and sensor regions is provided, described MOS device district section substrate is formed with polysilicon gate, described sensor regions section substrate is formed with polysilicon zone of heating, described substrate is formed with the first medium layer being covered in polycrystalline silicon gate surface and polysilicon heating layer surface;

First medium floor surface above MOS device district forms the first sub-metal interconnecting layer be electrically connected with polysilicon gate, first medium layer surface simultaneously above described sensor regions forms the first metal interconnecting layer of some electrically insulated from one another, the first electric connection layer and lower electrode layer, and described first metal interconnecting layer, the first electric connection layer and lower electrode layer are across the boundary of MOS device district and sensor regions, wherein, the first metal interconnecting layer of at least 2 electrically insulated from one another is electrically connected with polysilicon zone of heating;

Belong to interconnect layer surfaces at described first interest, the first metal interconnecting layer is surperficial, lower electrode layer is surperficial and first medium layer surface forms second dielectric layer;

Second dielectric layer surface above described MOS device district forms the second sub-metal interconnecting layer be electrically connected with polysilicon gate, second dielectric layer surface simultaneously above described sensor regions forms the second metal interconnecting layer and the second electric connection layer, described second electric connection layer is electrically connected with the first electric connection layer, and described second metal interconnecting layer with there is between lower electrode layer relative coincidence face;

Belong to interconnect layer surfaces, the second metal interconnecting layer surface, the second electric connection layer surface and second dielectric layer surface at described second interest and form the 3rd dielectric layer;

The 3rd dielectric layer surface above described MOS device district forms the 3rd sub-metal interconnecting layer be electrically connected with polysilicon gate, the 3rd dielectric layer surface simultaneously above described sensor regions forms the upper electrode layer be electrically connected with the second electric connection layer, and described upper electrode layer with there is between lower electrode layer relative coincidence face, between described upper electrode layer with described second metal interconnecting layer, there is relative coincidence face;

Belong to interconnect layer surfaces, upper electrode layer surface and the 3rd dielectric layer surface at described 3rd interest and form top layer dielectric layer;

Etch the substrate of top layer dielectric layer, the 3rd dielectric layer, second dielectric layer, first medium layer and segment thickness successively, annular groove is formed in sensor regions, described annular groove is around the first metal interconnecting layer, the first electric connection layer, lower electrode layer, the second metal interconnecting layer, the second electric connection layer and upper electrode layer, etching removes the top layer dielectric layer, the 3rd dielectric layer and the second dielectric layer that are positioned at above the second metal interconnecting layer successively simultaneously, until expose the second metal interconnecting layer surface, above described second metal interconnecting layer, form through hole;

Adopt isotropic etching technique, the substrate side wall surface being positioned at sensor regions exposed along described annular groove etches, etching removes the segment thickness substrate be positioned at below polysilicon zone of heating, above described sensor regions, form hanging structure, and between described hanging structure and the substrate of sensor regions, there is area of insulation;

Etching removes described second metal interconnecting layer, below described through hole, form groove;

Form the humidity-sensitive material layer of filling full described groove and through hole.

2. the formation method of CMOS humidity sensor according to claim 1, is characterized in that, be parallel on substrate surface direction, described annular groove is of a size of 1/10 to 2/5 of clear size of opening; Described groove is of a size of 2 times of the size of through hole to 5 times.

3. the formation method of CMOS humidity sensor according to claim 2, is characterized in that, be parallel on substrate surface direction, described annular groove is of a size of 3 microns to 5 microns; Described through hole is of a size of 10 microns to 50 microns.

4. the formation method of CMOS humidity sensor according to claim 1, is characterized in that, is being parallel on substrate surface direction, and the section shape of described upper electrode layer is square or pectination shape.

5. the formation method of CMOS humidity sensor according to claim 1, is characterized in that, before etching removes described second metal interconnecting layer, described second metal interconnecting layer sidewall is covered by the 3rd dielectric layer; Before etching removes described second metal interconnecting layer, described upper electrode layer sidewall is covered by top layer dielectric layer.

6. the formation method of CMOS humidity sensor according to claim 1, it is characterized in that, while described second electric connection layer of formation, second dielectric layer surface above described sensor regions forms pseudo-metal interconnecting layer, electrically insulated from one another between described pseudo-metal interconnecting layer and the second electric connection layer, described pseudo-metal interconnecting layer is across the boundary of MOS device district and sensor regions, and described pseudo-metal interconnecting layer is positioned at directly over the first metal interconnecting layer, the first electric connection layer.

7. the formation method of CMOS humidity sensor according to claim 6, it is characterized in that, in the process that place forms described annular groove and through hole, when the second metal interconnecting layer surface is exposed, described pseudo-metal interconnecting layer surface is exposed; Remove while described second metal interconnecting layer in etching, described pseudo-metal interconnecting layer is etched removal.

8. the formation method of CMOS humidity sensor according to claim 7, is characterized in that, described hanging structure has support arm, is suitable for playing the effect supporting hanging structure; Described support arm is laminated construction, at least comprises: be positioned at the second dielectric layer immediately below described pseudo-metal interconnecting layer, the first electric connection layer, the first metal interconnecting layer, lower electrode layer and first medium layer.

9. the formation method of CMOS humidity sensor according to claim 6, is characterized in that, also comprise step:

Before described first metal interconnecting layer of formation, form at least some the first conductive plungers be electrically connected with polysilicon zone of heating in the first medium layer above described sensor regions, and described first metal interconnecting layer is electrically connected with the first conductive plunger;

Before described second metal interconnecting layer of formation and the second electric connection layer, form some the second conductive plungers be electrically connected with the first electric connection layer in second dielectric layer above described sensor regions, and described second conductive plunger is electrically connected with the second electric connection layer be positioned at directly over the first electric connection layer;

Before the described upper electrode layer of formation, form some the 3rd conductive plungers be electrically connected with the second electric connection layer in the 3rd dielectric layer above described sensor regions, and described 3rd conductive plunger is electrically connected with upper electrode layer.

10. the formation method of CMOS humidity sensor according to claim 1, is characterized in that, the material of described humidity-sensitive material layer is polyimides; Spin coating process and annealing in process is adopted to form described humidity-sensitive material layer.

The formation method of 11. CMOS humidity sensors according to claim 1, it is characterized in that, the processing step forming described humidity-sensitive material layer comprises: form the humidity-sensitive material layer of filling full described groove and through hole, and described humidity-sensitive material layer is also positioned at top layer dielectric layer surface; Etching removes the humidity-sensitive material layer of described top layer dielectric layer surface.

12. will go the formation method of the CMOS humidity sensor described in 1 according to right, it is characterized in that, the material of described second metal interconnecting layer is aluminium; Adopt wet corrosion technique etching to remove described second metal interconnecting layer, the liquid that wet corrosion technique adopts is hydrofluoric acid solution or tetramethyl ammonium hydroxide solution.

The formation method of 13. CMOS humidity sensors according to claim 1, is characterized in that, adopts XeF ₂carry out described isotropic etching technique; The technological parameter of described isotropic etching technique is: circulation is carried out passing into XeF in etching cavity ₂with extraction XeF ₂action, XeF in etching cavity ₂pressure is 100Pa to 180Pa, and passes into XeF in etching cavity ₂rear maintenance 10 seconds to 50 seconds, cycle-index is 5 to 15 times.

The formation method of 14. CMOS humidity sensors according to claim 1, is characterized in that, described sensor regions is the region of humidity sensor to be formed; Described MOS device district is the region of MOS signal processor to be formed.

The formation method of 15. CMOS humidity sensors according to claim 1, is characterized in that, be also formed with the first oxide layer between described polysilicon gate and substrate; Also be formed with the second oxide layer between described polysilicon zone of heating and substrate, wherein, the second oxide layer is formed in technique with the first oxide layer.

16. 1 kinds of CMOS humidity sensors, is characterized in that, comprising:

Substrate, described substrate comprises MOS device district and sensor regions, described MOS device district section substrate is formed with polysilicon gate, described sensor regions section substrate is formed with polysilicon zone of heating, described substrate is formed with the first medium layer being covered in polycrystalline silicon gate surface and polysilicon heating layer surface;

Be positioned at the first sub-metal interconnecting layer on the first medium floor surface above described MOS device district, described first sub-metal interconnecting layer is electrically connected with polysilicon gate;

Be positioned at the first metal interconnecting layer of some electrically insulated from one another on the first medium layer surface above described sensor regions, the first electric connection layer and lower electrode layer, and described first metal interconnecting layer, the first electric connection layer and lower electrode layer are across the boundary of MOS device district and sensor regions, wherein, the first metal interconnecting layer of at least 2 electrically insulated from one another is electrically connected with polysilicon zone of heating;

Be positioned at the second dielectric layer that described first interest belongs to interconnect layer surfaces, the first metal interconnecting layer surface, the surperficial and first medium layer surface of lower electrode layer;

Be positioned at the second sub-metal interconnecting layer on the second dielectric layer surface above described MOS device district, described second sub-metal interconnecting layer is electrically connected with polysilicon gate;

Be positioned at second electric connection layer on the second dielectric layer surface above described sensor regions, described second electric connection layer is electrically connected with the first electric connection layer;

Be positioned at described second interest and belong to interconnect layer surfaces, the second electric connection layer surface and the 3rd dielectric layer on second dielectric layer surface;

Be positioned at the 3rd sub-metal interconnecting layer of the 3rd dielectric layer surface above described MOS device district, and described 3rd sub-metal interconnecting layer is electrically connected with polysilicon gate;

Be positioned at the upper electrode layer be electrically connected with the second electric connection layer of the 3rd dielectric layer surface above described sensor regions, and described upper electrode layer with there is between lower electrode layer relative coincidence face;

Be positioned at described 3rd interest and belong to interconnect layer surfaces, upper electrode layer surface and the top layer dielectric layer of the 3rd dielectric layer surface;

Be positioned at the top layer dielectric layer of described sensor regions, the 3rd dielectric layer, second dielectric layer, first medium layer and section substrate annular groove, described annular groove is around the first metal interconnecting layer, the first electric connection layer, lower electrode layer, the second electric connection layer and upper electrode layer;

Be positioned at the area of insulation of described sensor regions, described area of insulation and annular groove run through mutually, and described area of insulation is between substrate and polysilicon zone of heating; Be positioned at the through hole of the top layer dielectric layer of described sensor regions and the 3rd dielectric layer of segment thickness, and be positioned at the groove of the 3rd dielectric layer of residual thickness, described groove and through hole run through mutually, and described groove with there is between lower electrode layer relative coincidence face, described groove with there is between upper electrode layer relative coincidence face;

Fill the humidity-sensitive material layer of full described groove and through hole.

17. CMOS humidity sensors according to claim 16, it is characterized in that, also comprise: the first conductive plunger being positioned at first medium layer above described sensor regions, described first conductive plunger is electrically connected with polysilicon zone of heating and the first metal interconnecting layer; Be positioned at the second conductive plunger of second dielectric layer above described sensor regions, described second conductive plunger is electrically connected with the first electric connection layer and the second electric connection layer; Be positioned at the 3rd conductive plunger of the 3rd dielectric layer above described sensor regions, described 3rd conductive plunger is electrically connected with the second electric connection layer and upper electrode layer.

18. CMOS humidity sensors according to claim 16, it is characterized in that, described hanging structure has support arm, is suitable for playing the effect supporting hanging structure; Described support arm is laminated construction, at least comprises: second dielectric layer, the first electric connection layer, the first metal interconnecting layer, lower electrode layer and first medium layer.