CN104617095A - Complementary metal oxide semiconductor (CMOS) gas sensor and forming method thereof - Google Patents
Complementary metal oxide semiconductor (CMOS) gas sensor and forming method thereof Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 111
- 239000004065 semiconductor Substances 0.000 title abstract description 5
- 229910044991 metal oxide Inorganic materials 0.000 title abstract description 4
- 150000004706 metal oxides Chemical class 0.000 title abstract description 4
- 230000000295 complement effect Effects 0.000 title abstract description 3
- 229910052751 metal Inorganic materials 0.000 claims abstract description 313
- 239000002184 metal Substances 0.000 claims abstract description 313
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 189
- 239000000758 substrate Substances 0.000 claims abstract description 132
- 238000010438 heat treatment Methods 0.000 claims abstract description 107
- 238000005530 etching Methods 0.000 claims abstract description 62
- 238000002161 passivation Methods 0.000 claims abstract description 47
- 230000008569 process Effects 0.000 claims abstract description 39
- 229920005591 polysilicon Polymers 0.000 claims description 180
- 230000015572 biosynthetic process Effects 0.000 claims description 69
- 239000000463 material Substances 0.000 claims description 33
- 229920002120 photoresistant polymer Polymers 0.000 claims description 26
- 238000009413 insulation Methods 0.000 claims description 20
- 238000012545 processing Methods 0.000 claims description 16
- 229910052760 oxygen Inorganic materials 0.000 claims description 15
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 11
- 238000004544 sputter deposition Methods 0.000 claims description 9
- 229910006404 SnO 2 Inorganic materials 0.000 claims description 8
- 238000012423 maintenance Methods 0.000 claims description 4
- 238000000605 extraction Methods 0.000 claims description 3
- 238000002955 isolation Methods 0.000 abstract description 6
- 238000001312 dry etching Methods 0.000 abstract description 2
- 239000000725 suspension Substances 0.000 abstract 2
- 230000010354 integration Effects 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 139
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 238000000137 annealing Methods 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 125000004429 atom Chemical group 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 230000035945 sensitivity Effects 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000010276 construction Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 125000004430 oxygen atom Chemical group O* 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910052718 tin Inorganic materials 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 239000003054 catalyst Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 206010067482 No adverse event Diseases 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 230000007613 environmental effect Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 230000009931 harmful effect Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910002091 carbon monoxide Inorganic materials 0.000 description 1
- 238000007084 catalytic combustion reaction Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000002360 explosive Substances 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 231100000331 toxic Toxicity 0.000 description 1
- 230000002588 toxic effect Effects 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- 150000003624 transition metals Chemical class 0.000 description 1
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
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- G—PHYSICS
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- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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Abstract
The invention discloses a complementary metal oxide semiconductor (CMOS) gas sensor and a forming method thereof. The method comprises the steps that: a polycrystalline silicon heating layer of the gas sensor is formed by using a process for forming a polycrystalline silicon gate of a metal oxide semiconductor (MOS) device; a sensor interconnection structure is formed by using a process of forming an MOS device interconnection structure; a gas sensitive layer is formed on the surface of a second top metal interconnection layer of the sensor interconnection structure; a passivation layer, a dielectric layer and a part of the thickness of a substrate around the gas sensitive are etched by using a dry etching process to form a trench surrounding the gas sensitive layer; and the substrate exposed out of the trench are etched by using an isotropic etching process to form a suspension structure above a sensor area, and a thermal isolation area is formed between the suspension structure and the sensor area. The forming process of the gas sensor is completely compatible with the forming process of the MOS device, and the gas sensor and the MOS device are integrated on the same chip, so that the size of the chip is reduced, the power consumption is reduced, and the integration and yield are enhanced.
Description
Technical field
The present invention relates to field of semiconductor fabrication technology, particularly a kind of CMOS gas sensor and forming method thereof.
Background technology
Gas sensor is that composition specific in gas is detected by certain principle by one, and certain signal detected is converted to the device of suitable electrical signal.Along with the mankind are to the pay attention to day by day of the problems such as environmental protection, pollution and public safety, and people are for the improving constantly of requirement of living standard, and gas sensor achieves and applies widely in industrial, the civilian and large major domain of environmental monitoring three.
Detect the difference of principle of gas according to gas sensor, gas sensor mainly comprises catalytic combustion type, electric chemical formula, heat-conducted, infrared absorption type and semiconductor-type gas sensor etc.Wherein, semiconductor-type gas sensor comprises resistance-type gas sensor and non-resistor gas sensor, because resistance-type gas sensor has highly sensitive, easy to operate, the advantage such as volume is little, with low cost, the response time is short and recovery time is short, resistance-type gas sensor is widely applied, such as to flammable explosive gas (as CH
4, H
2deng) and toxic and harmful (as CO, NO
xdeng) detection in play an important role.
General, need to provide signal processing circuit that gas sensor is normally worked, the method that prior art is commonly used is: individually form gas sensor and signal processor, then gas sensor and signal processor is carried out encapsulation combination.
Standard CMOS (Complementary Metal Oxide Semiconductor) technique according to compatibility carries out the making of gas sensor, then can by gas sensor and cmos signal processing apparatus on the same chip integrated, thus enhance product performance, reduce chip area, improve integrated, improve output, reduce production cost etc.Therefore, need a kind of formation method that new gas sensor is provided badly, simultaneously by gas sensor and cmos signal processing apparatus on the same chip integrated, and form the technique of gas sensor and can not cause harmful effect to cmos signal processing apparatus.
Summary of the invention
The problem that the present invention solves is to provide a kind of CMOS gas sensor and forming method thereof, and the formation process of gas sensor and the formation process compatibility of MOS device are high, reduces chip area, improves integrated level and output, reduction power consumption and production cost.
For solving the problem, the invention provides a kind of formation method of CMOS gas sensor, comprising: provide substrate, described substrate comprises MOS device district and sensor regions; Form polysilicon gate on described MOS device district section substrate surface, while the described polysilicon gate of formation, described sensor regions section substrate forms polysilicon zone of heating; Described MOS device district and sensor regions substrate form dielectric layer, and described dielectric layer is covered in polycrystalline silicon gate surface and polysilicon heating layer surface; MOS device interconnection structure and sensor-interconnect structure is formed in described dielectric layer; Wherein, described MOS device interconnection structure is positioned at above MOS device district, described MOS device interconnection structure is electrically connected with polysilicon gate, described MOS device interconnection structure at least comprises 2 layers of metal interconnecting layer, and the metal interconnecting layer in described MOS device district comprises the first top-level metallic interconnection layer, described first top-level metallic interconnection layer top flushes with dielectric layer top; The described sensor-interconnect structure of part is electrically connected with polysilicon zone of heating, described sensor-interconnect structure at least comprises 2 layers of metal interconnecting layer, the metal interconnecting layer of sensor regions comprises the second top-level metallic interconnection layer, and in described sensor-interconnect structure, have at least 1 floor metal interconnecting layer to be also positioned at above MOS device district, described second top-level metallic interconnection layer top flushes with dielectric layer top, and the second top-level metallic interconnection layer and polysilicon zone of heating electrically insulated from one another; Form passivation layer at described dielectric layer surface and the first top-level metallic interconnect layer surfaces, and described passivation layer exposes the second top-level metallic interconnect layer surfaces; Gas sensing layer is formed at described second top-level metallic interconnect layer surfaces; Adopt dry etch process, etching is positioned at the substrate of passivation layer, dielectric layer and segment thickness around described gas sensing layer successively, forms the groove around described gas sensing layer in sensor regions; Adopt isotropic etching technique, the substrate side wall surface being positioned at sensor regions exposed along described groove etches, etching removes the segment thickness substrate be positioned at below polysilicon zone of heating, hanging structure is formed above described sensor regions, and between described hanging structure and the substrate of sensor regions, there is area of insulation, wherein, hanging structure comprises polysilicon zone of heating, certain media layer, sensor-interconnect structure and gas sensing layer.
Optionally, the substrate thickness that described employing dry etch process etching is removed is 5 microns to 10 microns; Be parallel on described substrate surface direction, described groove is of a size of 3 microns to 5 microns.
Optionally, the processing step forming described groove comprises: form the second photoresist layer in described passivation layer surface and gas sensing layer surface, have the annular opening be positioned at above sensor regions in described second photoresist layer, described annular opening exposes the passivation layer surface around gas sensing layer; With described second photoresist layer for mask, the passivation layer exposed along described annular opening etches, until etching removes the substrate of segment thickness.
Optionally, XeF is adopted
2carry out described isotropic etching technique; The technological parameter of described isotropic etching technique is: circulation is carried out passing into XeF in etching cavity
2with extraction XeF
2action, XeF in etching cavity
2pressure is 100Pa to 180Pa, and passes into XeF in etching cavity
2rear maintenance 10 seconds to 50 seconds, cycle-index is 5 to 15 times.
Optionally, the processing step forming described passivation layer comprises: form passivation layer at described dielectric layer surface, the first top-level metallic interconnect layer surfaces and the second top-level metallic interconnect layer surfaces; Form the first photoresist layer in described passivation layer surface, described first photoresist layer exposes the passivation layer surface being positioned at the second top-level metallic upperside interconnection layer; With described first photoresist layer for mask, etching removes the passivation layer being positioned at described second top-level metallic interconnect layer surfaces.
Optionally, the material of described gas sensing layer is SnO
2or doped with the SnO of Pt
2; Adopting magnetron sputtering technique to form material is SnO
2gas sensing layer, technological parameter is: provide Sn target, and sputter gas is Ar and O
2, wherein, Ar and O
2gas flow ratio be 2:1 to 5:1, sputtering chamber pressure is 1Pa to 5Pa, and the operating voltage provided is 500V to 1000V, and the radio frequency source power provided is 100 watts to 200 watts, and the temperature of substrate 100 is 20 degrees Celsius to 50 degrees Celsius.
Optionally, the first oxide layer is also formed with between described polysilicon gate and substrate; Also be formed with the second oxide layer between described polysilicon zone of heating and substrate, wherein, the second oxide layer is formed in technique with the first oxide layer; The processing step forming described polysilicon gate and polysilicon zone of heating comprises: form oxide layer at the substrate surface of described MOS device district and sensor regions; Polysilicon layer is formed on described oxide layer surface; The polysilicon layer in graphical described MOS device district and oxide layer, formed and be positioned at first oxide layer on section substrate surface, MOS device district and be positioned at the polysilicon gate on the first oxide layer surface; The polysilicon layer of graphical described sensor regions and oxide layer, formed and be positioned at second oxide layer on section substrate surface, sensor regions and be positioned at the polysilicon zone of heating on the second oxide layer surface.
Optionally, the formation method of described dielectric layer, MOS device interconnection structure, sensor-interconnect structure comprises: form first medium layer at described substrate surface, and described first medium layer is covered in polycrystalline silicon gate surface and polysilicon heating layer surface; Some first metal interconnecting layers are formed on described first medium layer surface, a part the first metal interconnecting layer is positioned at above MOS device district, and the first metal interconnecting layer be positioned at above MOS device district is electrically connected with polysilicon gate, another part first metal interconnecting layer is positioned at above sensor regions, the first metal interconnecting layer be positioned at above sensor regions is electrically connected with polysilicon zone of heating respectively, and described the first metal interconnecting layer electrically insulated from one another be electrically connected with polysilicon zone of heating; Form the second dielectric layer being covered in described first medium layer surface and the first metal interconnecting layer surface; Some second metal interconnecting layers are formed on described second dielectric layer surface, a part the second metal interconnecting layer is positioned at above MOS device district, and the second metal interconnecting layer be positioned at above MOS device district is electrically connected with polysilicon gate, another part second metal interconnecting layer is positioned at above sensor regions, and part second metal interconnecting layer be positioned at above sensor regions is electrically connected with polysilicon zone of heating; Form the 3rd dielectric layer being covered in described second dielectric layer surface and the second metal interconnecting layer surface; Some 3rd metal interconnecting layers are formed at described 3rd dielectric layer surface, a part the 3rd metal interconnecting layer is positioned at above MOS device district, and the 3rd metal interconnecting layer be positioned at above MOS device district is electrically connected with polysilicon gate, another part the 3rd metal interconnecting layer is positioned at above sensor regions, the 3rd metal interconnecting layer be positioned at above sensor regions is electrically connected with part second metal interconnecting layer, and the 3rd metal interconnecting layer above sensor regions and electric insulation between polysilicon zone of heating; Form the 4th dielectric layer being covered in described 3rd dielectric layer surface and the 3rd metal interconnecting layer surface; In described MOS device district the 4th, dielectric layer surface forms the first top-level metallic interconnection layer, described first top-level metallic interconnection layer is electrically connected with polysilicon gate, described in the second top-level metallic interconnection layer forming some electrically insulated from one another at described sensor regions the 4th dielectric layer surface, the second top-level metallic interconnection layer is electrically connected with the 3rd metal interconnecting layer, wherein, described second top-level metallic interconnection layer utilizes with the first top-level metallic interconnection layer and is formed with technique; Form the top layer dielectric layer being covered in described 3rd dielectric layer surface, the first top-level metallic interconnect layer surfaces and the second top-level metallic interconnect layer surfaces, and described top layer dielectric layer flushes with the first top-level metallic interconnection layer, the second top-level metallic interconnection layer top.
Optionally, also comprise step: before described first metal interconnecting layer of formation, some first conductive plungers are formed in described first medium layer, a part the first conductive plunger is positioned at above MOS device district, and the first conductive plunger above MOS device district is electrically connected with the first metal interconnecting layer above polysilicon gate and MOS device district, another part first conductive plunger is positioned at above sensor regions, and the first conductive plunger above sensor regions is electrically connected with the first metal interconnecting layer above polysilicon zone of heating and sensor regions; Before described second metal interconnecting layer of formation, some second conductive plungers are formed in described second dielectric layer, a part the second conductive plunger is positioned at above MOS device district, and the second conductive plunger above MOS device district is electrically connected with the first metal interconnecting layer above MOS device district and the second metal interconnecting layer, another part second conductive plunger is positioned at above sensor regions, and the second conductive plunger above sensor regions is electrically connected with the first metal interconnecting layer above sensor regions and part second metal interconnecting layer; Before described 3rd metal interconnecting layer of formation, some 3rd conductive plungers are formed in described 3rd dielectric layer, a part the 3rd conductive plunger is positioned at above MOS device district, and the 3rd conductive plunger above MOS device district is electrically connected with the second metal interconnecting layer above MOS device district and the 3rd metal interconnecting layer, another part the 3rd conductive plunger is positioned at above sensor regions, and the 3rd conductive plunger above sensor regions is electrically connected with part second metal interconnecting layer above sensor regions and the 3rd metal interconnecting layer; Before the described first top-level metallic interconnection layer of formation and the second top-level metallic interconnection layer, some 4th conductive plungers are formed in described 4th dielectric layer, a part the 4th conductive plunger is positioned at above MOS device district, and the 4th conductive plunger above MOS device district is electrically connected with the 3rd metal interconnecting layer above MOS device district and the first top-level metallic interconnection layer, another part the 4th conductive plunger is positioned at above sensor regions, and the 4th conductive plunger above sensor regions is electrically connected with the 3rd metal interconnecting layer above sensor regions and the second top-level metallic interconnection layer.
Optionally, there is in described sensor-interconnect structure the second metal interconnecting layer of some electrically insulated from one another, the second metal interconnecting layer in described sensor-interconnect structure is also positioned at the second dielectric layer surface in MOS device district, wherein, part second metal interconnecting layer in sensor-interconnect structure is electrically connected with polysilicon zone of heating, and another part second metal interconnecting layer in sensor-interconnect structure is electrically connected with the second top-level metallic interconnection layer; The second metal interconnecting layer in described sensor-interconnect structure is the support arm of hanging structure.
Optionally, described sensor regions is the region of gas sensor to be formed; Described MOS device district is the region of MOS signal processor to be formed.
The present invention also provides a kind of CMOS gas sensor, comprising: substrate, and described substrate comprises MOS device district and sensor regions; Be positioned at the polysilicon gate on section substrate surface, described MOS device district; Be positioned at the polysilicon zone of heating on section substrate surface, described sensor regions; Be positioned at the dielectric layer on described MOS device district and sensor regions substrate, and described dielectric layer is covered in polycrystalline silicon gate surface and polysilicon heating layer surface; Be positioned at MOS device interconnection structure and the sensor-interconnect structure of described dielectric layer; Wherein, described MOS device interconnection structure is positioned at above MOS device district, described MOS device interconnection structure is electrically connected with polysilicon gate, described MOS device interconnection structure at least comprises 2 layers of metal interconnecting layer, and the metal interconnecting layer in described MOS device district comprises the first top-level metallic interconnection layer, described first top-level metallic interconnection layer top flushes with dielectric layer top; Described sensor-interconnect structure is positioned at above sensor regions, described sensor-interconnect structure is electrically connected with polysilicon zone of heating, described sensor-interconnect structure at least comprises 2 layers of metal interconnecting layer, the metal interconnecting layer of sensor regions comprises the second top-level metallic interconnection layer, and in described sensor-interconnect structure, having at least 1 floor metal interconnecting layer to be also positioned at above MOS device district, described second top-level metallic interconnection layer top flushes with dielectric layer top; Be positioned at the passivation layer of described dielectric layer surface and the first top-level metallic interconnect layer surfaces; Be positioned at the gas sensing layer of described second top-level metallic interconnect layer surfaces; Around described gas sensing layer and the groove be positioned at above sensor regions, described groove runs through passivation layer above sensor regions and dielectric layer, and described groove exposes the section substrate surface of sensor regions; By described groove around hanging structure, between described hanging structure and the substrate of sensor regions, there is area of insulation, and flush with bottom dielectric layer bottom described hanging structure.
Optionally, described dielectric layer comprises: the first medium floor being positioned at the substrate surface of MOS device district and sensor regions, the second dielectric layer being positioned at first medium floor surface, be positioned at second dielectric layer surface the 3rd dielectric layer, be positioned at the 4th dielectric layer of the 3rd dielectric layer surface and be positioned at the top layer dielectric layer of the 4th dielectric layer surface.
Optionally, described MOS device interconnection structure comprises 4 layers of metal interconnecting layer, and described MOS device interconnection structure comprises: the 3rd metal interconnecting layer of MOS device district the 3rd dielectric layer surface that is positioned at first metal interconnecting layer on first medium floor surface, MOS device district, is positioned at second metal interconnecting layer on second dielectric layer surface, MOS device district, is positioned at, be positioned at the first top-level metallic interconnection layer of MOS device district the 4th dielectric layer surface.
Optionally, described MOS device interconnection structure also comprises: the first conductive plunger being positioned at first medium layer, and described first conductive plunger is electrically connected with polysilicon gate and the first metal interconnecting layer; Be positioned at the second conductive plunger of second dielectric layer, described second conductive plunger is electrically connected with the first metal interconnecting layer and the second metal interconnecting layer; Be positioned at the 3rd conductive plunger of the 3rd dielectric layer, described 3rd conductive plunger is electrically connected with the second metal interconnecting layer and the 3rd metal interconnecting layer; Be positioned at the 4th conductive plunger of the 4th dielectric layer, described 4th conductive plunger is electrically connected with the 3rd metal interconnecting layer and the first top-level metallic interconnection layer.
Optionally, described sensor-interconnect structure comprises 4 layers of metal interconnecting layer, and described sensor-interconnect structure comprises: the 3rd metal interconnecting layer of sensor regions the 3rd dielectric layer surface that is positioned at first metal interconnecting layer on first medium layer surface, sensor regions, is positioned at second metal interconnecting layer on second dielectric layer surface, sensor regions, is positioned at, be positioned at the second top-level metallic interconnection layer of some electrically insulated from one another of sensor regions the 4th dielectric layer surface.
Optionally, described sensor-interconnect structure also comprises: the first conductive plunger being positioned at first medium layer, described first conductive plunger is electrically connected with polysilicon zone of heating and the first metal interconnecting layer, and the first metal interconnecting layer electrically insulated from one another be electrically connected with described polysilicon zone of heating; Be positioned at the second conductive plunger of second dielectric layer, described second conductive plunger is electrically connected with the first metal interconnecting layer and part second metal interconnecting layer; Be positioned at the 3rd conductive plunger of the 3rd dielectric layer, described 3rd conductive plunger is electrically connected with part second metal interconnecting layer and the 3rd metal interconnecting layer, and electric insulation between the 3rd metal interconnecting layer and polysilicon zone of heating; Be positioned at the 4th conductive plunger of the 4th dielectric layer, described 4th conductive plunger is electrically connected with the 3rd metal interconnecting layer and the second top-level metallic interconnection layer.
Optionally, there is in described sensor-interconnect structure the second metal interconnecting layer of some electrically insulated from one another, the second metal interconnecting layer in described sensor-interconnect structure is also positioned at the second dielectric layer surface in MOS device district, wherein, part second metal interconnecting layer in sensor-interconnect structure is electrically connected with polysilicon zone of heating, and another part second metal interconnecting layer in sensor-interconnect structure is electrically connected with the second top-level metallic interconnection layer; The second metal interconnecting layer in described sensor-interconnect structure is the support arm of hanging structure.
Compared with prior art, technical scheme of the present invention has the following advantages:
In the technical scheme of the formation method of CMOS gas sensor provided by the invention, while the polysilicon gate forming MOS device district, sensor regions section substrate forms polysilicon zone of heating; MOS device district and sensor regions substrate form dielectric layer, and dielectric layer is also covered in polycrystalline silicon gate surface and polysilicon heating layer surface; Then in dielectric layer, form MOS device interconnection structure and sensor-interconnect structure, wherein, MOS device interconnection structure to be positioned at above MOS device district and to be electrically connected with polysilicon gate, and sensor-interconnect structure to be positioned at above sensor regions and to be electrically connected with polysilicon zone of heating; Then form passivation layer at dielectric layer surface and the first top-level metallic interconnect layer surfaces, the second top-level metallic interconnect layer surfaces exposed at described passivation layer forms gas sensing layer; Then, adopt dry etch process, etching is positioned at the substrate of passivation layer, dielectric layer and segment thickness around gas sensing layer successively, forms the groove around gas sensing layer in sensor regions; Adopt isotropic etching technique, the substrate side wall surface being positioned at sensor regions exposed along described groove etches, etching removes the segment thickness substrate be positioned at below polysilicon zone of heating, hanging structure is formed above described sensor regions, and between described hanging structure and the substrate of sensor regions, there is area of insulation, wherein, hanging structure comprises polysilicon zone of heating, certain media layer, sensor-interconnect structure and gas sensing layer.In the present invention the formation process of gas sensor and the formation process of MOS device completely compatible, can by MOS device and gas sensor on the same chip integrated, reduce chip area, improve integrated level and output, reduce power consumption and production cost.
Further, adopting magnetron sputtering technique to form material in the present invention is SnO
2gas sensing layer, technological parameter is: provide Sn target, and sputter gas is Ar and O
2, wherein, Ar and O
2gas flow ratio be 2:1 to 5:1, sputtering chamber pressure is 1Pa to 5Pa, and the operating voltage provided is 500V to 1000V, and the radio frequency source power provided is 100 watts to 200 watts, and the temperature of substrate 100 is 20 degrees Celsius to 50 degrees Celsius.When adopting technological parameter provided by the invention to form gas sensing layer, Sn atom and O atom have enough energy, make Sn atom and O atom carry out sufficient travel motion on the second top-level metallic interconnection layer 423 surface, thus make the gas sensing layer thickness of formation evenly and there is larger specific area.
Further, the present invention is when adopting magnetron sputtering technique to form gas sensing layer, and the partial pressure of oxygen in sputtering chamber is moderate, concrete, Ar and O
2gas flow ratio be 2:1 to 5:1, avoid gas sensing layer to be oxidized too fully or degree of oxidation too low, the oxygen content in the gas sensing layer of the formation made is moderate, thus makes the sensitivity of gas sensing layer to gas larger.
Further, the substrate thickness that in the present invention, dry etch process etching is removed is 5 microns to 10 microns, make the moderate dimensions of the area of insulation of follow-up formation, avoid too small due to the distance between hanging structure and substrate and in the polysilicon zone of heating caused heat not easily to discharge; Further, the thickness of the substrate that isotropic etching technique etching can also be avoided to remove is blocked up, prevents polysilicon zone of heating to be subject to excessive effect of stress, avoids polysilicon zone of heating generation deformation.
Accordingly, the present invention's CMOS gas sensor of also providing a kind of structural behaviour superior.
Accompanying drawing explanation
The cross-sectional view of the CMOS gas sensor forming process that Fig. 1 to Figure 15 provides for one embodiment of the invention.
Embodiment
From background technology, the manufacture craft of prior art gas sensor and CMOS technology poor compatibility, the CMOS technology being difficult to employing standard makes gas sensor.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
The cross-sectional view of the CMOS gas sensor forming process that Fig. 1 to Figure 15 provides for one embodiment of the invention.
With reference to figure 1, provide substrate 100, described substrate 100 comprises MOS device district I and sensor regions II.
The material of described substrate 100 is silicon, germanium, SiGe, carborundum or GaAs, and described substrate 100 can also be the germanium on isolate supports, insulator or the SiGe on insulator.Described substrate 100 surface can also form some epitaxial interface layers or strained layer, to improve the electric property of CMOS gas sensor.
In the present embodiment, described substrate 100 is silicon substrate.Described MOS device district I is the region of MOS signal processor to be formed, and follow-up formation PMOS transistor, nmos pass transistor or CMOS transistor provide signal processing circuit platform, for detecting or gather the signal of telecommunication in gas sensor; Described sensor regions II is the region of gas sensor to be formed, for follow-up formation gas sensor provides workbench.Isolation structure can also be formed in described MOS device district I substrate 100, described isolation structure can be fleet plough groove isolation structure (STI, Shallow Trench Isolation), the packing material of isolation structure is the insulating material such as silica, silicon nitride or silicon oxynitride.
Can also form some well regions in MOS device district I substrate 100, the type of described well region is determined according to the type of MOS device to be formed, and the doping type of described well region is N-type doping or the doping of P type.Such as, when part MOS device district I forms nmos pass transistor, then form P type trap zone in corresponding MOS device district I substrate 100, the Doped ions of described P type trap zone is B, Ga or In; When part MOS device district I forms PMOS transistor, then form N-type well region in corresponding MOS device district I substrate 100, the Doped ions of described N-type well region is P, As or Sb.
The present embodiment with a MOS device district I, a sensor regions II exemplarily, the quantity of corresponding follow-up formation gas sensor is 1, be parallel in substrate 100 surface direction, described sensor regions I is of a size of 10 microns × 10 microns to 50 microns × 50 microns.In other embodiments, the quantity in MOS device district can for the arbitrary natural number being more than or equal to 1, and the quantity of sensor regions also can for the arbitrary natural number being more than or equal to 1, then the quantity of the gas sensor of corresponding formation is identical with the quantity of sensor regions.
In the present embodiment, follow-up to form PMOS transistor exemplarily in MOS device district I.
With reference to figure 2, form oxide layer 101 on substrate 100 surface of described MOS device district I and sensor regions II; Polysilicon layer 102 is formed on described oxide layer 101 surface.
The oxide layer 101 being arranged in MOS device district I is follow-up also for the formation of the gate dielectric layer of nmos pass transistor.The material of described oxide layer 101 is silica; Chemical vapour deposition (CVD), physical vapour deposition (PVD) or atom layer deposition process is adopted to form described oxide layer 101.
Be arranged in the follow-up polysilicon gate for the formation of PMOS transistor of polysilicon layer 102 of MOS device district I; Be positioned at the follow-up polysilicon zone of heating for the formation of gas sensor of polysilicon layer 102 of sensor regions II.The material of described polysilicon layer 102 is the polysilicon of polysilicon or doping, such as, and the polysilicon of doping P or B; Chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process is adopted to form described polysilicon layer 102.
In the present embodiment, the material of described oxide layer 101 is silica, adopts chemical vapor deposition method to form described oxide layer 101; The material of described polysilicon layer 102 is polysilicon, adopts chemical vapor deposition method to form described polysilicon layer 102.
With reference to figure 3, the polysilicon layer 102 (with reference to figure 2) of graphical described MOS device district I and oxide layer 101 (with reference to figure 2), formed and be positioned at first oxide layer 111 on MOS device district I section substrate 100 surface and be positioned at the polysilicon gate 112 on the first oxide layer 111 surface; The polysilicon layer 102 of graphical described sensor regions II and oxide layer 101, formed and be positioned at second oxide layer 121 on II section substrate 100 surface, sensor regions and be positioned at the polysilicon zone of heating 122 on the second oxide layer 121 surface.
In the present embodiment, with in technique, carry out polysilicon layer 102 and the oxide layer 101 of described graphical MOS device district I and sensor regions II.
Concrete, the polysilicon layer 102 of graphical MOS device district I and sensor regions II and the processing step of oxide layer 101 comprise: form graph layer on described polysilicon layer 102 surface, the material of described graph layer can be photoresist or hard mask material, and the region that described graph layer covers corresponds to the region of follow-up polysilicon gate 112 to be formed and polysilicon zone of heating 122; Then, with described graph layer for mask, etching removes described polysilicon layer 102 and oxide layer 101, until expose substrate 100 surface; Then, described graph layer is removed.
In the present embodiment, form polysilicon gate 112 on described MOS device district I section substrate 100 surface, and between described polysilicon gate 112 and substrate 100, be formed with the first oxide layer 111; While the described polysilicon gate 112 of formation, form polysilicon zone of heating 122 on described sensor regions II section substrate 100 surface, and be formed with the second oxide layer 121 between described polysilicon zone of heating 122 and substrate 100.
Described first oxide layer 111 and polysilicon gate 112 form the grid structure of MOS device.Described polysilicon zone of heating 122 is as the heating resistor of gas sensor, joule's heat energy is produced in polysilicon zone of heating 122 when subsequent current flows through polysilicon zone of heating 122, thus the gas sensing layer of follow-up formation is heated, improve the sensitivity of gas sensing layer induction gas, shorten the response time of gas sensor.
On the direction being parallel to substrate 100 surface, the section shape of described polysilicon zone of heating 112 is square, square waveform, sawtooth waveform, annular or spirality, and wherein, spirality can be square spiral.
In the present embodiment, the shape of described polysilicon zone of heating 122 is square, and the thickness of polysilicon zone of heating 122 is 2 nanometer to 300 nanometers.
After the grid structure forming MOS device, also comprise step: the substrate 100 of grid structure both sides is adulterated, the source region of corresponding formation MOS device and drain region.
With reference to figure 4, form first medium floor 103 at described MOS device district I and sensor regions II substrate 100 surface, and described first medium layer 103 is covered in polysilicon gate 112 surface and polysilicon zone of heating 122 surface.
Described first medium layer 103 is not only covered in polysilicon gate 112 sidewall surfaces, polysilicon zone of heating 122 sidewall surfaces, is also covered in polysilicon gate 112 top surface, polysilicon zone of heating 122 top surface.The material of described first medium layer 103 is insulating material, and the material of first medium layer 103 can be silica, silicon nitride or silicon oxynitride.
In the present embodiment, adopt chemical vapor deposition method to form described first medium layer 103, the material of first medium layer 103 is silica.
Rear extended meeting forms dielectric layer on MOS device district I and sensor regions II substrate 100, then in dielectric layer, form MOS device interconnection structure and sensor-interconnect structure, described MOS device interconnection structure is positioned at above MOS device district I, and described MOS device interconnection structure is electrically connected with polysilicon gate 112; Described sensor-interconnect structure is positioned at above the II of sensor regions, and described sensor-interconnect structure is electrically connected with polysilicon zone of heating 122, wherein, described MOS device interconnection structure at least comprises 2 layers of metal interconnecting layer, and described sensor-interconnect structure at least comprises 2 layers of metal interconnecting layer.
The present embodiment is follow-up comprises 4 layers of metal interconnecting layer with MOS device interconnection structure, and sensor-interconnect structure comprises 4 layers of interconnection structure exemplarily.
With reference to figure 5, in described first medium layer 103 formed some first conductive plungers 301, a part of first conductive plunger 301 be positioned at above MOS device district I, another part first conductive plunger 301 is positioned at above the II of sensor regions.
In the present embodiment, described first conductive plunger 301 top flushes with first medium layer 103 top; The first conductive plunger 301 above MOS device district I is electrically connected with the transistor in MOS device, such as be electrically connected with the source electrode of transistor, drain electrode or polysilicon gate 112, the first conductive plunger 301 above MOS device district I is also electrically connected with the first metal interconnecting layer of the follow-up formation of MOS device district I.
The first conductive plunger 301 above the II of sensor regions is electrically connected with polysilicon zone of heating 122, electric current is provided to polysilicon zone of heating 122 by the first conductive plunger 301, to make to produce joule's heat energy in polysilicon zone of heating 122, the first conductive plunger 301 above the II of sensor regions is also electrically connected with the first metal interconnecting layer of the follow-up formation of sensor regions II.
The processing step forming described first conductive plunger 301 comprises: form graph layer on described first medium layer 103 surface; With described graph layer for first medium layer 103 described in mask etching, multiple first conductive through hole is formed in described first medium layer 103, the the first conductive through hole bottom-exposed being positioned at MOS device district I goes out the source electrode of transistor, drain electrode and polysilicon gate 112 surface, and the first conductive through hole bottom-exposed being positioned at sensor regions II goes out polysilicon zone of heating 122 surface; Form first conductive plunger 301 of filling full described first conductive through hole, and described conductive plunger 301 top flushes with first medium layer 103 top.
The material of described first conductive plunger 301 is metal, and the material of such as the first conductive plunger 301 can be copper, aluminium or tungsten.
With reference to figure 6, form some first metal interconnecting layers 401 on described first medium layer 103 surface, described first metal interconnecting layer 401 is electrically connected with the first conductive plunger 301; Form the second dielectric layer 104 being covered in described first metal interconnecting layer 401 surface and first medium layer 103 surface.
In the present embodiment, a part the first metal interconnecting layer 401 is positioned at above MOS device district I, and the first metal interconnecting layer 401 above MOS device district I is electrically connected with polysilicon gate 112, concrete makes the first metal interconnecting layer 401 be electrically connected with polysilicon gate 112 by the first conductive plunger 301.Another part first metal interconnecting layer is positioned at above the II of sensor regions, and the first metal interconnecting layer 401 be positioned at above the II of sensor regions is electrically connected with polysilicon zone of heating 122 by the first conductive plunger 301, and described the first metal interconnecting layer 401 electrically insulated from one another be electrically connected with polysilicon zone of heating 122, thus make subsequent current flow in polysilicon zone of heating 122 via one first metal interconnecting layer 401, then flow out via another first metal interconnecting layer 401.
The material of described first metal interconnecting layer 401 is metal, and such as the material of the first metal interconnecting layer 401 is copper, aluminium or tungsten.
Described first metal interconnecting layer 401 is made by deposition, etching technics.Concrete, the processing step forming described first metal interconnecting layer 401 comprises: at described first medium layer 103 surface and the metal interconnected film of the first conductive plunger 301 surface deposition first; Graph layer is formed on described first metal interconnected film surface; With described graph layer for mask, etch described first metal interconnected film, form some first metal interconnecting layers 401 on described first medium layer 103 surface.
In the present embodiment, the first metal interconnecting layer 401 above described sensor regions II is only positioned at the top of sensor regions II.In other embodiments, the first metal interconnecting layer above sensor regions, except being positioned at except above sensor regions, can also be positioned at the first medium floor surface above part MOS device district.
The material of described second dielectric layer 104 is insulating material, and chemical vapour deposition (CVD), physical vapour deposition (PVD) or atom layer deposition process can be adopted to form described second dielectric layer 104.Described second dielectric layer 104 top surface is higher than the first metal interconnecting layer 401 top surface.
Then, in described second dielectric layer 104, the second conductive plunger 302 is formed.
A part described second conductive plunger 302 be positioned at above MOS device district I, described second conductive plunger 302 is electrically connected with the first metal interconnecting layer 401 above MOS device district I; Described in another part, the second conductive plunger 302 is positioned at above the II of sensor regions, and described second conductive plunger 302 is electrically connected with the first metal interconnecting layer 401 above the II of sensor regions.
The formation method of described second conductive plunger 302 can with reference to the formation method of aforementioned first conductive plunger 301.
With reference to figure 7, form the second metal interconnecting layer 402 of some electrically insulated from one another on described second dielectric layer 104 surface, described second metal interconnecting layer 402 of part is electrically connected with the second conductive plunger 302; Form the 3rd dielectric layer 105 being covered in described second metal interconnecting layer 402 surface and second dielectric layer 104 surface.
In the present embodiment, a part of second metal interconnecting layer 402 is positioned at above MOS device district I, and the second metal interconnecting layer 402 be positioned at above MOS device district I is electrically connected with polysilicon gate 112.Another part second metal interconnecting layer 402 is positioned at above the II of sensor regions, and part second metal interconnecting layer 402 be positioned at above the II of sensor regions is electrically connected with polysilicon zone of heating 122, described part second metal interconnecting layer 402 is electrically connected with the second conductive plunger 302 above the II of sensor regions, thus realize polysilicon zone of heating 122 and be electrically connected with part second metal interconnecting layer 402 in sensor-interconnect structure, the second top-level metallic interconnection layer of follow-up formation can be electrically connected with another part second metal interconnecting layer 402.
The formation method of described second metal interconnecting layer 402 can with reference to the formation method of aforementioned first metal interconnecting layer 401.In other embodiments, described second metal interconnecting layer 402 and the second conductive plunger 302 also can adopt Damascus technics to be formed.
In the present embodiment, the second metal interconnecting layer 402 part above the II of sensor regions is positioned at above the II of sensor regions, the second metal interconnecting layer 402 above the II of sensor regions also part is positioned at second dielectric layer 104 surface of MOS device district I, thus make follow-up when forming hanging structure, second metal interconnecting layer 402 as the support arm of hanging structure, can make stable being suspended on above the II of sensor regions of hanging structure.When the quantity of the second metal interconnecting layer 402 is 4, can think that hanging structure has 4 support arms.
The material of described 3rd dielectric layer 105 is insulating material, and in the present embodiment, the material of the 3rd dielectric layer 105 is silica.
With reference to figure 8, in described 3rd dielectric layer 105, form the 3rd conductive plunger 303; Form some 3rd metal interconnecting layers 403 on described 3rd dielectric layer 105 surface, described 3rd metal interconnecting layer 403 is electrically connected with the 3rd conductive plunger 303; Form the 4th dielectric layer 106 being covered in described 3rd metal interconnecting layer 403 surface and the 3rd dielectric layer 105 surface; The 4th conductive plunger 304 is formed in described 4th dielectric layer 106; The 4th dielectric layer 106 surface above described MOS device district I forms the first top-level metallic interconnection layer 413, and the 4th dielectric layer 106 surface above described sensor regions II forms the second top-level metallic interconnection layer 423 of some electrically insulated from one another; Form top layer dielectric layer 107 on described 4th dielectric layer 106 surface, the first top-level metallic interconnection layer 413 surface and the second top-level metallic interconnection layer 423 surface, and described top layer dielectric layer 107 top flushes with the first top-level metallic interconnection layer 413, second top-level metallic interconnection layer 423 top.
About the formation method of the 3rd conductive plunger 303, the 4th conductive plunger 304 can with reference to the formation method of aforementioned second conductive plunger 302, about the formation method of the 3rd metal interconnecting layer 403 can with reference to the formation method of aforementioned second metal interconnecting layer 402, about the formation method of the 4th dielectric layer 106 can with reference to the formation method of aforementioned 3rd dielectric layer 105.
A part the 3rd metal interconnecting layer 403 is positioned at above MOS device district I, and the 3rd metal interconnecting layer 403 be positioned at above MOS device district I is electrically connected with polysilicon gate 112.Another part the 3rd metal interconnecting layer 403 is positioned at above the II of sensor regions, the 3rd metal interconnecting layer 403 be positioned at above the II of sensor regions is electrically connected with part second metal interconnecting layer 402, and the 3rd metal interconnecting layer 403 above the II of sensor regions and electric insulation between polysilicon zone of heating 122.
A part the 3rd conductive plunger 303 is positioned at above MOS device district I, and the 3rd conductive plunger 303 above MOS device district I is electrically connected with the second metal interconnecting layer 402 above MOS device district I and the 3rd metal interconnecting layer 403.Another part the 3rd conductive plunger 303 is positioned at above the II of sensor regions, and the 3rd conductive plunger 303 above the II of sensor regions is electrically connected with part second metal interconnecting layer 402 above the II of sensor regions and the 3rd metal interconnecting layer 403, wherein, part second metal interconnecting layer 402 refers to the second metal interconnecting layer 402 be not electrically connected with polysilicon zone of heating 122.
A part the 4th conductive plunger 304 is positioned at above MOS device district I, and the 4th conductive plunger 304 above MOS device district I is electrically connected with the 3rd metal interconnecting layer 403 above MOS device district I and the first top-level metallic interconnection layer 413.Another part the 4th conductive plunger 304 is positioned at above the II of sensor regions, and the 4th conductive plunger 304 above the II of sensor regions is electrically connected with the 3rd metal interconnecting layer 403 above the II of sensor regions and the second top-level metallic interconnection layer 423.
In other embodiments, the formation process of described 3rd conductive plunger 303 and the 3rd metal interconnecting layer 403 can also be Damascus technics.
In the present embodiment, the 3rd metal interconnecting layer 403 above the II of sensor regions is only positioned at the top of sensor regions II.In other embodiments, the 3rd metal interconnecting layer 403 above the II of sensor regions can also be positioned at above MOS device district I.Described first top-level metallic interconnection layer 413 utilizes with the second top-level metallic interconnection layer 423 and is formed with technique.Concrete, the processing step forming described first top-level metallic interconnection layer 413 and the second top-level metallic interconnection layer 423 comprises: form top-level metallic interconnection film on the 4th dielectric layer 106 surface; Graph layer is formed on described top-level metallic interconnection film surface; With described graph layer for top-level metallic interconnection film described in mask etching, form the first top-level metallic interconnection layer 413 at MOS device district I, form the second top-level metallic interconnection layer 423 at sensor regions II.
In other embodiments, the first top-level metallic interconnection layer 413, second top-level metallic interconnection layer 423, the 4th conductive plunger 304 can adopt Damascus technics to be formed.
In the present embodiment, part second metal interconnecting layer 402 in sensor-interconnect structure is electrically connected with polysilicon zone of heating 122, and another part second metal interconnecting layer 402 in sensor-interconnect structure is electrically connected with the second top-level metallic interconnection layer 423.The present embodiment is 4 exemplarily with the quantity of the second top-level metallic interconnection layer 423, because Fig. 8 is cross-sectional view, therefore illustrate only 2 the second top-level metallic interconnection layers 423 in Fig. 8.Then, the passivation layer 108 being covered in described top layer dielectric layer 107 surface, the first top-level metallic interconnection layer 413 surface, the second top-level metallic interconnection layer 423 surface is formed.
Described passivation layer 108, for the protection of the first top-level metallic interconnection layer 413, second top-level metallic interconnection layer 423, avoids the first top-level metallic interconnection layer 413, second top-level metallic interconnection layer 423 oxidized or sustain damage.
In the present embodiment, MOS device district I and sensor regions II substrate 100 form dielectric layer, and described dielectric layer comprises: first medium layer 103, be positioned at first medium layer 103 surface second dielectric layer 104, be positioned at second dielectric layer 104 surface the 3rd dielectric layer 105, be positioned at the 4th dielectric layer 106 on the 3rd dielectric layer 105 surface and be positioned at the top layer dielectric layer 107 on the 4th dielectric layer 106 surface.
In the present embodiment, MOS device interconnection structure is positioned at above MOS device district, and MOS device interconnection structure is electrically connected with polysilicon gate 112, and MOS device interconnection structure comprises 4 layers of metal interconnecting layer.Concrete, MOS device interconnection structure comprises: the first metal interconnecting layer 401 being positioned at first medium floor 103 surface above MOS device district I, the second metal interconnecting layer 402 being positioned at second dielectric layer 104 surface, be positioned at the 3rd metal interconnecting layer 403 on the 3rd dielectric layer 105 surface, be positioned at the first top-level metallic interconnection layer 413 on the 4th dielectric layer 106 surface; MOS device interconnection structure also comprises: the first conductive plunger 301 being arranged in first medium floor 103 above MOS device district I, the second conductive plunger 302 being arranged in second dielectric layer 104, be arranged in the 3rd conductive plunger 303 of the 3rd dielectric layer 105 and be arranged in the 4th conductive plunger 304 of the 4th dielectric layer 106.
In other embodiments, MOS device interconnection structure can comprise 2 layers, 3 layers, 5 layers or 6 layers of arbitrary number of layers metal interconnecting layer.
In the present embodiment, sensor-interconnect structure is positioned at above the II of sensor regions, and the described sensor-interconnect structure of part is electrically connected with polysilicon zone of heating 122, and sensor-interconnect structure comprises 4 layers of metal interconnecting layer.Concrete, sensor-interconnect structure comprises: the first metal interconnecting layer 401 being positioned at first medium layer 103 surface above the II of sensor regions, the second metal interconnecting layer 402 being positioned at second dielectric layer 104 surface, be positioned at the 3rd metal interconnecting layer 403 on the 3rd dielectric layer 105 surface, be positioned at the second top-level metallic interconnection layer 423 on the 4th dielectric layer 106 surface; Sensor-interconnect structure also comprises: the first conductive plunger 301 being arranged in first medium layer 103 above the II of sensor regions, the second conductive plunger 302 being arranged in second dielectric layer 104, be arranged in the 3rd conductive plunger 303 of the 3rd dielectric layer 105 and be arranged in the 4th conductive plunger 304 of the 4th dielectric layer 106.
In other embodiments, sensor-interconnect structure can comprise 2 layers, 3 layers, 5 layers or 6 layers of arbitrary number of layers metal interconnecting layer, and the number of plies of the metal interconnecting layer of sensor-interconnect structure is equal with the number of plies of the metal interconnecting layer of MOS device interconnection structure.
In the present embodiment, 1 floor metal interconnecting layer is had at least to be also positioned at above MOS device district I in sensor-interconnect structure, thus make follow-up after formation hanging structure, described metal interconnecting layer in sensor-interconnect structure can as the support arm of hanging structure, thus play the effect supporting hanging structure, prevent hanging structure from dropping.Such as, one or more layers metal interconnecting layer being arranged in the first metal interconnecting layer 401, second metal interconnecting layer 402 above the II of sensor regions, the 3rd metal interconnecting layer 403 or the second top-level metallic interconnection layer 423 is positioned at above MOS device district I.
In the present embodiment, consider the equilibrium problem of hanging structure, above the substrate 100 being supported on sensor regions II making hanging structure more stable, the second metal interconnecting layer 402 in sensor-interconnect structure is also positioned at above MOS device district I, and the second metal interconnecting layer 402 part namely in sensor-interconnect structure is covered in second dielectric layer 104 surface of MOS device district I.
With reference to figure 9, form the first photoresist layer 109 on described passivation layer 108 surface, described first photoresist layer 109 exposes passivation layer 108 surface directly over the second top-level metallic interconnection layer 423.
Described first photoresist layer 109 is removed for subsequent etching and is positioned at the mask of the passivation layer 108 on the second top-level metallic interconnection layer 423 surface, the passivation layer 108 being positioned at the second top-level metallic interconnection layer 423 surface is etched removal, thus the second top-level metallic interconnection layer 423 surface is exposed, to form gas sensing layer on the second top-level metallic interconnection layer 423 surface.
In a specific embodiment, the processing step forming described first photoresist layer 109 comprises: form initial lithographic glue-line on described passivation layer 108 surface; Exposure technology and developing process are carried out to described initial lithographic glue-line, forms described first photoresist layer 109.
With reference to Figure 10, with described first photoresist layer 109 for mask, etching removes the passivation layer 108 directly over position second top-level metallic interconnection layer 423, and the second top-level metallic interconnection layer 423 surface is exposed.
Can adopt the dry etch process such as reactive ion etching process or plasma etch process, etching removes the passivation layer 108 be positioned at directly over the second top-level metallic interconnection layer 423.
With reference to Figure 11, form gas sensing layer 110 on described second top-level metallic interconnection layer 423 surface.
Gas sensing layer 110 is for adsorbing the gas in environment, when gas sensor is in running order, after gas sensing layer 110 adsorbed gas, resistance changes, when gas concentration is different, corresponding gas sensing layer 110 resistance value is different, can be known the concentration of gas in environment by the size of the resistance value detecting gas sensing layer 110.
The material of described gas sensing layer 110 can be SnO
2, ZnO
2, Ga
2o
3, TiO
2or Nb
2o
5.Different according to the type of required gas to be detected, select different gas sensitives as the material of gas sensing layer 110.
In order to improve selectivity and the sensitivity of gas sensing layer 110 pairs of gases, shorten the reaction time of gas sensor, catalyst material can also be added in gas sensing layer 110, catalyst material is difficult to the free energy of reaction changing gas sensing layer 110 adsorbed gas, but the activation energy of gas sensing layer 110 adsorbed gas can be reduced, thus accelerate the speed of gas absorption chemical reaction generation.Described catalyst material is noble metal or the transition metal such as Ag, Pt or Pd.
In the present embodiment, the material of described gas sensing layer 110 is the SnO being added with Pt
2.Sol-gal process or sputtering method is adopted to form described gas sensing layer 110.
In the present embodiment, adopt magnetron sputtering method to form described gas sensing layer 110, concrete, first adopting magnetron sputtering method to form material is SnO
2gas sensing layer 110, the technological parameter of magnetron sputtering method is: provide Sn target, and sputter gas is Ar and O
2, wherein, Ar and O
2gas flow ratio be 2:1 to 5:1, sputtering chamber pressure is 1Pa to 5Pa, and the operating voltage provided is 500V to 1000V, and the radio frequency source power provided is 100 watts to 200 watts, and the temperature of substrate 100 is 20 degrees Celsius to 50 degrees Celsius.
The specific area of gas sensing layer 110 is larger, and the sensitivity that corresponding gas sensing layer 110 responds to gas is higher.And adopt magnetron sputtering method formation material to be SnO
2gas sensing layer 110 time, gas sensing layer 110 has larger specific area.When sputtering chamber pressure is 3Pa to 4Pa, the operating voltage provided is 620V to 710V, the radio frequency source power provided be 140 watts to 160 watt-hours, adopt in magnetron sputtering formation gas sensing layer 110 process to provide and there is very high energy, Sn atom and O atom is made to have enough energy, thus make Sn atom and O atom carry out sufficient travel motion on the second top-level metallic interconnection layer 423 surface, thus make gas sensing layer 110 surface distributed even, make the SnO in gas sensing layer 110
2uniform particles nucleation, thus make the gas sensing layer 110 formed have larger specific area.
Further, in magnetron sputtering process, if partial pressure of oxygen is excessive in sputtering chamber, then the gas sensing layer 110 of formation can be made to be oxidized too abundant, the Lacking oxygen in gas sensing layer 110 is very few; If partial pressure of oxygen is too small in sputtering chamber, then the degree of oxidation of gas sensing layer 110 material formed is low.Oxidation is too fully or degree of oxidation is low all can cause the sensitivity of gas sensing layer 110 pairs of gases low, for this reason, in one embodiment, Ar and O
2gas flow ratio be 3:1 to 4:1, thus the degree making the gas sensing layer 110 of formation oxidized is moderate, and the sensitivity of gas sensing layer 110 pairs of gases is larger.
Then, magnetron sputtering method is adopted to be SnO at material
2gas sensing layer 110 surface form Pt film; Then, cineration technics is adopted to remove described first photoresist layer 109.
Finally, the gas sensing layer 110 that effects on surface is formed with Pt film carries out annealing in process, and described annealing in process can make Pt diffuse in gas sensing layer 110 on the one hand, can also improve the quality of the gas sensing layer 110 formed on the other hand further.
The annealing temperature of described annealing in process is 200 degrees Celsius to 300 degrees Celsius, and such as annealing temperature can be 240 degrees Celsius, 260 degrees Celsius or 280 degrees Celsius.
With reference to Figure 12, the second photoresist layer 111 is formed on described passivation layer 108 surface and gas sensing layer 110 surface, described second photoresist layer 111 has the annular opening 112 be positioned at above the II of sensor regions, and described annular opening 112 exposes passivation layer 108 surface around gas sensing layer 110.
Annealing temperature due to annealing in process is 200 degrees Celsius to 300 degrees Celsius, and the annealing in process of carrying out under described annealing temperature has no adverse effects to MOS device district I.
Described second photoresist layer 111 is the mask of the substrate 100 of subsequent etching passivation layer 108, dielectric layer and segment thickness, prepares for forming hanging structure.
The size of described annular opening 112 is relevant with the area of insulation size of follow-up formation, if annular opening 112 is oversize, then the volume shared by the area of insulation of follow-up formation is comparatively large, causes the chip area formed needed for CMOS gas sensor large; If annular opening 112 is undersized, then the volume shared by the area of insulation of follow-up formation is little, and the heat causing polysilicon zone of heating 122 to produce easily is passed to undesirably region, the response time delay of CMOS gas sensor.
And, if annular opening 112 is undersized, then the size of the groove of corresponding follow-up formation is also less, and when substrate 100 sidewall surfaces adopting isotropic etching technique etching groove to expose, the difficulty that etching gas arrives described substrate 100 sidewall surfaces increases.
For this reason, in the present embodiment, be parallel in substrate 100 surface direction, described annular opening 112 is of a size of 3 microns to 5 microns.
With reference to Figure 13, with described second photoresist layer 111 for mask, the passivation layer 108 exposed along described annular opening 112 (with reference to Figure 12) etches, until etching removes the substrate 100 of segment thickness.
Concrete, adopt dry etch process, etching is positioned at the substrate 100 of passivation layer 108, dielectric layer and segment thickness around described gas sensing layer 110 successively, forms the groove 113 around described gas sensing layer 110 at sensor regions II.
Described dry etch process is very little to the etch rate of metal interconnecting layer, and larger to the etch rate of dielectric layer.Because second metal interconnecting layer 402 of sensor regions II is across MOS device district I and sensor regions II, the etch rate of dry etch process to second metal interconnecting layer 402 of sensor regions II is very little, make dry etch process can not to the second dielectric layer 104 below the second metal interconnecting layer 402, 3rd dielectric layer 103, and polysilicon zone of heating 122 causes etching, and follow-up isotropic etching technique only etches substrate 100, therefore in fact the support arm of hanging structure is: at least by the second metal interconnecting layer 402, second dielectric layer 104, the laminated construction that first medium layer 103 forms, the support arm of hanging structure can also comprise polysilicon zone of heating 122.
The thickness of the substrate 100 that described employing dry etch process etching is removed is relevant with the size of the area of insulation of follow-up formation, if substrate 100 is etched, the thickness removed is too small, then area of insulation undersized of corresponding follow-up formation, distance between the hanging structure of follow-up formation and substrate 100 is too small, and the heat in described polysilicon zone of heating 122 not easily discharges; If substrate 100 is etched, the thickness removed is excessive, then the thickness of corresponding remaining substrate 100 is very little, easily causes polysilicon zone of heating 122 to be subject to effect of stress excessively strong, causes polysilicon zone of heating 122 that serious deformation occurs.Further, if substrate 100 is etched, the thickness of removal is excessive, then the substrate 100 of the corresponding follow-up sensor regions II when carrying out isotropic etching technique can be worn by quarter.
Amid all these factors consider, substrate 100 be etched remove thickness be 1/30 to 1/3 of substrate 100 original depth, such as, substrate 100 be etched remove thickness can for substrate 100 original depth 1/10 or 1/5.
In the present embodiment, substrate 100 thickness that described employing dry etch process etching is removed is 5 microns to 10 microns, such as, can be 6 microns or 8 microns; Also can think, perpendicular in substrate 100 surface direction, substrate 100 side wall dimensions that described groove 113 exposes is 5 microns to 10 microns.
In the present embodiment, the thickness of dielectric layer is 8 microns to 12 microns, and described dielectric layer is: first medium layer 103, be positioned at first medium layer 103 surface second dielectric layer 104, be positioned at second dielectric layer 104 surface the 3rd dielectric layer 105, be positioned at the 4th dielectric layer 106 on the 3rd dielectric layer 105 surface and be positioned at the top layer dielectric layer 107 on the 4th dielectric layer 106 surface; Be parallel in substrate 100 surface direction, described groove 113 is of a size of 3 microns to 5 microns.
In the present embodiment, the sidewall surfaces of described groove 113 is perpendicular to substrate 100 surface; In other embodiments, perpendicular in substrate 100 surface direction, the section shape of described groove 113 can also be inverted trapezoidal, groove 113 top dimension is made to be greater than groove 113 bottom size, thus make the etching gas of follow-up isotropic etching technique more easily enter the bottom of groove 113, thus substrate 100 sidewall surfaces that groove 113 exposes is etched.
With reference to Figure 14, adopt isotropic etching technique, substrate 100 sidewall surfaces exposed along described groove 113 etches, and forms hanging structure, have area of insulation 114 between described hanging structure and substrate 100 above the II of sensor regions.
Described hanging structure comprises: polysilicon zone of heating 122, certain media layer, sensor-interconnect structure and gas sensing layer 110.
Specific in the present embodiment, described hanging structure comprises: the second oxide layer 121, be positioned at the polysilicon zone of heating 122 on the second oxide layer 121 surface, be positioned at the first medium layer 103 on polysilicon zone of heating 122 surface, be positioned at the first conductive plunger 301 of first medium layer 103, be positioned at first metal interconnecting layer 401 on the first conductive plunger 301 surface and part first medium layer 103 surface, be positioned at the second dielectric layer 104 on the first metal interconnecting layer 401 surface and first medium layer 103 surface, be positioned at the second conductive plunger 302 of second dielectric layer 104, be positioned at second metal interconnecting layer 402 on the second conductive plunger 302 surface and part second dielectric layer 104 surface, be positioned at the 3rd dielectric layer 105 on the second metal interconnecting layer 402 surface and second dielectric layer 104 surface, be positioned at the 3rd conductive plunger 303 on the 3rd dielectric layer 105 surface, be positioned at the 4th dielectric layer 106 on the 3rd conductive plunger 303 surface and part the 3rd dielectric layer 105 surface, be positioned at the 4th conductive plunger 304 of the 4th dielectric layer 106, be positioned at the second top-level metallic interconnection layer 423 on the 4th conductive plunger 304 surface and part the 4th dielectric layer 106 surface, be positioned at the top layer dielectric layer 107 on the second top-level metallic interconnection layer 423 sidewall surfaces and the 4th dielectric layer 106 surface, and be positioned at the passivation layer 108 on top layer dielectric layer 107 surface.
The first metal interconnecting layer 401 in hanging structure partly or entirely sidewall surfaces cover by dielectric layer, the second metal interconnecting layer 402 in hanging structure partly or entirely sidewall surfaces cover by dielectric layer, the 3rd metal interconnecting layer 403 in hanging structure partly or entirely sidewall surfaces is covered by dielectric layer, thus reduces the first metal interconnecting layer 401, second metal interconnecting layer 402 and the 3rd metal interconnecting layer 403 is oxidized or the probability of corrosion.In other embodiments, the second top-level metallic interconnection layer 423 sidewall surfaces in hanging structure also can be covered by dielectric layer.
In the present embodiment, adopt XeF
2carry out described isotropic etching technique, due to XeF
2for dry etching, and XeF
2etching technics for chemically to etch, the ion dam age that Ions Bombardment can be avoided to bring and the problem of charge accumulated.Further, XeF
2only substrate 100 is etched, and it is very little even negligible to the etch rate of dielectric layer, metal interconnecting layer, therefore described isotropic etching technique has no adverse effects to MOS device district I, and the technique and the standard CMOS process that therefore form hanging structure in the present embodiment are completely compatible.
Be parallel in substrate 100 surface direction, described area of insulation 114 is of a size of 10 microns to 50 microns, such as, be 15 microns, 20 microns, 25 microns or 35 microns.
In a specific embodiment, XeF is adopted
2the technological parameter carrying out isotropic etching technique is: circulation is carried out passing into XeF in etching cavity
2with extraction XeF
2action, XeF in etching cavity
2pressure is 100Pa to 180Pa, and passes into XeF in etching cavity
2rear maintenance 10 seconds to 50 seconds, cycle-index is 5 to 15 times.
Such as, XeF in etching cavity
2pressure can be 120Pa, 140Pa or 150Pa, in etching cavity, pass into XeF
2rear maintenance 15 seconds, 20 seconds or 30 seconds.
Due to XeF
2for isotropic etching technique, therefore formed in the process of hanging structure in etching, described isotropic etching technique both can substrate 100 immediately below etch polysilicon zone of heating 122, also can etch the substrate 100 being positioned at device region I.
In the present embodiment, the second metal interconnecting layer 402 in sensor-interconnect structure is the support arm of hanging structure, because the second dielectric layer 104 below described second metal interconnecting layer 402, first medium layer 103 all can not be etched, therefore support arm is actually the laminated construction of the second metal interconnecting layer 402, second dielectric layer 104 and first medium layer 103, and described laminated construction can also comprise the first metal interconnecting layer 401 or polysilicon zone of heating 122.In other embodiments, one or more layers in the first metal interconnecting layer 402 in sensor-interconnect structure, the 3rd metal interconnecting layer 403 or the second top-level metallic interconnection layer 423 all can as the support arm of hanging structure.
With reference to Figure 15, remove described second photoresist layer 111 (with reference to Figure 14).
Adopt cineration technics, remove described second photoresist layer 111.
Follow-up also comprising carries out packaging technology.
Accordingly, please refer to Figure 15, the present invention also provides a kind of CMOS gas sensor, comprising:
Substrate 100, described substrate 100 comprises MOS device district I and sensor regions II;
Be positioned at the polysilicon gate 112 on described MOS device district I section substrate surface;
Be positioned at the polysilicon zone of heating 122 on II section substrate 100 surface, described sensor regions;
Be positioned at the dielectric layer on described MOS device district I and sensor regions II substrate 100, and described dielectric layer is covered in polysilicon gate 112 surface and polysilicon zone of heating 122 surface;
Be positioned at MOS device interconnection structure and the sensor-interconnect structure of described dielectric layer;
Wherein, described MOS device interconnection structure is positioned at above MOS device district I, described MOS device interconnection structure is electrically connected with polysilicon gate 112, described MOS device interconnection structure at least comprises 2 layers of metal interconnecting layer, and the metal interconnecting layer of described MOS device district I comprises the first top-level metallic interconnection layer 413, described first top-level metallic interconnection layer 413 top flushes with dielectric layer top;
Described sensor-interconnect structure is positioned at above the II of sensor regions, described sensor-interconnect structure is electrically connected with polysilicon zone of heating 122, described sensor-interconnect structure at least comprises 2 layers of metal interconnecting layer, the metal interconnecting layer of sensor regions comprises the second top-level metallic interconnection layer 423, and in described sensor-interconnect structure, having at least 1 floor metal interconnecting layer to be also positioned at above MOS device district I, described second top-level metallic interconnection layer 423 top flushes with dielectric layer top;
Be positioned at the passivation layer on described dielectric layer surface and the first top-level metallic interconnection layer 413 surface;
Be positioned at the gas sensing layer 110 on described second top-level metallic interconnection layer 423 surface;
Around described gas sensing layer 110 and the groove 113 be positioned at above the II of sensor regions, described groove 113 runs through passivation layer 108 above the II of sensor regions and dielectric layer, and described groove 113 exposes section substrate 100 surface of sensor regions II;
By described groove 113 around hanging structure, between the substrate 100 of described hanging structure and sensor regions II, there is area of insulation 114, and flush with bottom dielectric layer bottom described hanging structure.
In the present embodiment, described dielectric layer comprises: the first medium floor 103 being positioned at substrate 100 surface of MOS device district I and sensor regions II, the second dielectric layer 104 being positioned at first medium floor 103 surface, be positioned at second dielectric layer 104 surface the 3rd dielectric layer 105, be positioned at the 4th dielectric layer 106 on the 3rd dielectric layer 105 surface and be positioned at the top layer dielectric layer 107 on the 4th dielectric layer 106 surface.
Described MOS device interconnection structure comprises 4 layers of metal interconnecting layer, and described MOS device interconnection structure comprises: the first top-level metallic interconnection layer 413 being positioned at first metal interconnecting layer 401 on MOS device district I first medium floor 103 surface, being positioned at second metal interconnecting layer 402 on MOS device district I second dielectric layer 104 surface, being positioned at the 3rd metal interconnecting layer 403 on MOS device district I the 3rd dielectric layer 105 surface, being positioned at MOS device district I the 4th dielectric layer 106 surface.
Described MOS device interconnection structure also comprises: the first conductive plunger 301 being positioned at first medium layer 103, and described first conductive plunger 301 is electrically connected with polysilicon gate 112 and the first metal interconnecting layer 401; Be positioned at the second conductive plunger 302 of second dielectric layer 104, described second conductive plunger 302 is electrically connected with the first metal interconnecting layer 401 and the second metal interconnecting layer 402; Be positioned at the 3rd conductive plunger 303 of the 3rd dielectric layer 105, described 3rd conductive plunger 303 is electrically connected with the second metal interconnecting layer 402 and the 3rd metal interconnecting layer 403, and electric insulation between the 3rd metal interconnecting layer 403 and polysilicon zone of heating 122; Be positioned at the 4th conductive plunger 304 of the 4th dielectric layer 106, described 4th conductive plunger 304 is electrically connected with the 3rd metal interconnecting layer 403 and the first top-level metallic interconnection layer 413.
Described sensor-interconnect structure comprises 4 layers of metal interconnecting layer, and described sensor-interconnect structure comprises: the second top-level metallic interconnection layer 423 being positioned at first metal interconnecting layer 401 on II first medium layer 103 surface, sensor regions, being positioned at second metal interconnecting layer 402 on II second dielectric layer 104 surface, sensor regions, being positioned at the 3rd metal interconnecting layer 403 on sensor regions II the 3rd dielectric layer 105 surface, being positioned at some mutually insulateds on sensor regions II the 4th dielectric layer 106 surface.
In the present embodiment, the second metal interconnecting layer 402 in sensor-interconnect structure is also positioned at second dielectric layer 104 surface of MOS device district I, makes the second metal interconnecting layer 402 as the support arm of hanging structure, prevents hanging structure from dropping; In fact, support arm is the laminated construction of the second metal interconnecting layer 402, second dielectric layer 104, first metal interconnecting layer 401, first medium layer 103, and support arm can also comprise polysilicon zone of heating 122.There is in described sensor-interconnect structure the second metal interconnecting layer 402 of some electrically insulated from one another, the second metal interconnecting layer 402 in described sensor-interconnect structure is also positioned at second dielectric layer 104 surface of MOS device district I, wherein, part second metal interconnecting layer 402 in sensor-interconnect structure is electrically connected with polysilicon zone of heating 122, and another part second metal interconnecting layer 402 in sensor-interconnect structure is electrically connected with the second top-level metallic interconnection layer 423.
Described sensor-interconnect structure also comprises: the first conductive plunger 301 being positioned at first medium layer 103, described first conductive plunger 301 is electrically connected with polysilicon zone of heating 122 and the first metal interconnecting layer 401, and the first metal interconnecting layer 401 electrically insulated from one another be electrically connected with described polysilicon zone of heating 122; Be positioned at the second conductive plunger 302 of second dielectric layer 104, described second conductive plunger 302 is electrically connected with the first metal interconnecting layer 401 and part second metal interconnecting layer 402; Be positioned at the 3rd conductive plunger 303 of the 3rd dielectric layer 105, described 3rd conductive plunger 303 is electrically connected with part second metal interconnecting layer 402 and the 3rd metal interconnecting layer 403; Be positioned at the 4th conductive plunger 304 of the 4th dielectric layer 106, described 4th conductive plunger 304 is electrically connected with the 3rd metal interconnecting layer 403 and the second top-level metallic interconnection layer 423.In other embodiments, MOS device interconnection structure also can comprise 2 layers, 3 layers, 5 layers or 6 layers of metal interconnecting layer, and accordingly, the number of plies of the metal interconnecting layer of sensor-interconnect structure is identical with the number of plies of MOS device interconnection structure.
Due to the first metal interconnecting layer 401 electrically insulated from one another be electrically connected with polysilicon zone of heating 122, thus after making electric current flow into polysilicon zone of heating 122 via one first metal interconnecting layer 401, flow out via another first metal interconnecting layer 401, thus electric current is flow through from polysilicon zone of heating 122, and then make to produce joule electric current in polysilicon zone of heating 122.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (18)
1. a formation method for CMOS gas sensor, is characterized in that, comprising:
There is provided substrate, described substrate comprises MOS device district and sensor regions;
Form polysilicon gate on described MOS device district section substrate surface, while the described polysilicon gate of formation, described sensor regions section substrate forms polysilicon zone of heating;
Described MOS device district and sensor regions substrate form dielectric layer, and described dielectric layer is covered in polycrystalline silicon gate surface and polysilicon heating layer surface;
MOS device interconnection structure and sensor-interconnect structure is formed in described dielectric layer;
Wherein, described MOS device interconnection structure is positioned at above MOS device district, described MOS device interconnection structure is electrically connected with polysilicon gate, described MOS device interconnection structure at least comprises 2 layers of metal interconnecting layer, and the metal interconnecting layer in described MOS device district comprises the first top-level metallic interconnection layer, described first top-level metallic interconnection layer top flushes with dielectric layer top;
Described sensor-interconnect structure is positioned at above sensor regions, the described sensor-interconnect structure of part is electrically connected with polysilicon zone of heating, described sensor-interconnect structure at least comprises 2 layers of metal interconnecting layer, the metal interconnecting layer of sensor regions comprises the second top-level metallic interconnection layer, and in described sensor-interconnect structure, have at least 1 floor metal interconnecting layer to be also positioned at above MOS device district, described second top-level metallic interconnection layer top flushes with dielectric layer top, and the second top-level metallic interconnection layer and polysilicon zone of heating electrically insulated from one another;
Form passivation layer at described dielectric layer surface and the first top-level metallic interconnect layer surfaces, and described passivation layer exposes the second top-level metallic interconnect layer surfaces;
Gas sensing layer is formed at described second top-level metallic interconnect layer surfaces;
Adopt dry etch process, etching is positioned at the substrate of passivation layer, dielectric layer and segment thickness around described gas sensing layer successively, forms the groove around described gas sensing layer in sensor regions;
Adopt isotropic etching technique, the substrate side wall surface being positioned at sensor regions exposed along described groove etches, etching removes the segment thickness substrate be positioned at below polysilicon zone of heating, hanging structure is formed above described sensor regions, and between described hanging structure and the substrate of sensor regions, there is area of insulation, wherein, hanging structure comprises polysilicon zone of heating, certain media layer, sensor-interconnect structure and gas sensing layer.
2. the formation method of CMOS gas sensor according to claim 1, is characterized in that, the substrate thickness that described employing dry etch process etching is removed is 5 microns to 10 microns; Be parallel on described substrate surface direction, described groove is of a size of 3 microns to 5 microns.
3. the formation method of CMOS gas sensor according to claim 1, it is characterized in that, the processing step forming described groove comprises: form the second photoresist layer in described passivation layer surface and gas sensing layer surface, have the annular opening be positioned at above sensor regions in described second photoresist layer, described annular opening exposes the passivation layer surface around gas sensing layer; With described second photoresist layer for mask, the passivation layer exposed along described annular opening etches, until etching removes the substrate of segment thickness.
4. the formation method of CMOS gas sensor according to claim 1, is characterized in that, adopts XeF
2carry out described isotropic etching technique; The technological parameter of described isotropic etching technique is: circulation is carried out passing into XeF in etching cavity
2with extraction XeF
2action, XeF in etching cavity
2pressure is 100Pa to 180Pa, and passes into XeF in etching cavity
2rear maintenance 10 seconds to 50 seconds, cycle-index is 5 to 15 times.
5. the formation method of CMOS gas sensor according to claim 1, it is characterized in that, the processing step forming described passivation layer comprises: form passivation layer at described dielectric layer surface, the first top-level metallic interconnect layer surfaces and the second top-level metallic interconnect layer surfaces; Form the first photoresist layer in described passivation layer surface, described first photoresist layer exposes the passivation layer surface being positioned at the second top-level metallic upperside interconnection layer; With described first photoresist layer for mask, etching removes the passivation layer being positioned at described second top-level metallic interconnect layer surfaces.
6. the formation method of CMOS gas sensor according to claim 1, is characterized in that, the material of described gas sensing layer is SnO
2or doped with the SnO of Pt
2; Adopting magnetron sputtering technique to form material is SnO
2gas sensing layer, technological parameter is: provide Sn target, and sputter gas is Ar and O
2, wherein, Ar and O
2gas flow ratio be 2:1 to 5:1, sputtering chamber pressure is 1Pa to 5Pa, and the operating voltage provided is 500V to 1000V, and the radio frequency source power provided is 100 watts to 200 watts, and the temperature of substrate 100 is 20 degrees Celsius to 50 degrees Celsius.
7. the formation method of CMOS gas sensor according to claim 1, is characterized in that, is also formed with the first oxide layer between described polysilicon gate and substrate; Also be formed with the second oxide layer between described polysilicon zone of heating and substrate, wherein, the second oxide layer is formed in technique with the first oxide layer; The processing step forming described polysilicon gate and polysilicon zone of heating comprises: form oxide layer at the substrate surface of described MOS device district and sensor regions; Polysilicon layer is formed on described oxide layer surface; The polysilicon layer in graphical described MOS device district and oxide layer, formed and be positioned at first oxide layer on section substrate surface, MOS device district and be positioned at the polysilicon gate on the first oxide layer surface; The polysilicon layer of graphical described sensor regions and oxide layer, formed and be positioned at second oxide layer on section substrate surface, sensor regions and be positioned at the polysilicon zone of heating on the second oxide layer surface.
8. the formation method of CMOS gas sensor according to claim 1, is characterized in that, the formation method of described dielectric layer, MOS device interconnection structure, sensor-interconnect structure comprises:
Form first medium layer at described substrate surface, and described first medium layer is covered in polycrystalline silicon gate surface and polysilicon heating layer surface;
Some first metal interconnecting layers are formed on described first medium layer surface, a part the first metal interconnecting layer is positioned at above MOS device district, and the first metal interconnecting layer be positioned at above MOS device district is electrically connected with polysilicon gate, another part first metal interconnecting layer is positioned at above sensor regions, the first metal interconnecting layer be positioned at above sensor regions is electrically connected with polysilicon zone of heating respectively, and described the first metal interconnecting layer electrically insulated from one another be electrically connected with polysilicon zone of heating;
Form the second dielectric layer being covered in described first medium layer surface and the first metal interconnecting layer surface;
Some second metal interconnecting layers are formed on described second dielectric layer surface, a part the second metal interconnecting layer is positioned at above MOS device district, and the second metal interconnecting layer be positioned at above MOS device district is electrically connected with polysilicon gate, another part second metal interconnecting layer is positioned at above sensor regions, and part second metal interconnecting layer be positioned at above sensor regions is electrically connected with polysilicon zone of heating;
Form the 3rd dielectric layer being covered in described second dielectric layer surface and the second metal interconnecting layer surface;
Some 3rd metal interconnecting layers are formed at described 3rd dielectric layer surface, a part the 3rd metal interconnecting layer is positioned at above MOS device district, and the 3rd metal interconnecting layer be positioned at above MOS device district is electrically connected with polysilicon gate, another part the 3rd metal interconnecting layer is positioned at above sensor regions, the 3rd metal interconnecting layer be positioned at above sensor regions is electrically connected with part second metal interconnecting layer, and the 3rd metal interconnecting layer above sensor regions and electric insulation between polysilicon zone of heating;
Form the 4th dielectric layer being covered in described 3rd dielectric layer surface and the 3rd metal interconnecting layer surface;
In described MOS device district the 4th, dielectric layer surface forms the first top-level metallic interconnection layer, described first top-level metallic interconnection layer is electrically connected with polysilicon gate, described in the second top-level metallic interconnection layer forming some electrically insulated from one another at described sensor regions the 4th dielectric layer surface, the second top-level metallic interconnection layer is electrically connected with the 3rd metal interconnecting layer, wherein, described second top-level metallic interconnection layer utilizes with the first top-level metallic interconnection layer and is formed with technique;
Form the top layer dielectric layer being covered in described 3rd dielectric layer surface, the first top-level metallic interconnect layer surfaces and the second top-level metallic interconnect layer surfaces, and described top layer dielectric layer flushes with the first top-level metallic interconnection layer, the second top-level metallic interconnection layer top.
9. the formation method of CMOS gas sensor according to claim 8, is characterized in that, also comprise step:
Before described first metal interconnecting layer of formation, some first conductive plungers are formed in described first medium layer, a part the first conductive plunger is positioned at above MOS device district, and the first conductive plunger above MOS device district is electrically connected with the first metal interconnecting layer above polysilicon gate and MOS device district, another part first conductive plunger is positioned at above sensor regions, and the first conductive plunger above sensor regions is electrically connected with the first metal interconnecting layer above polysilicon zone of heating and sensor regions;
Before described second metal interconnecting layer of formation, some second conductive plungers are formed in described second dielectric layer, a part the second conductive plunger is positioned at above MOS device district, and the second conductive plunger above MOS device district is electrically connected with the first metal interconnecting layer above MOS device district and the second metal interconnecting layer, another part second conductive plunger is positioned at above sensor regions, and the second conductive plunger above sensor regions is electrically connected with the first metal interconnecting layer above sensor regions and part second metal interconnecting layer;
Before described 3rd metal interconnecting layer of formation, some 3rd conductive plungers are formed in described 3rd dielectric layer, a part the 3rd conductive plunger is positioned at above MOS device district, and the 3rd conductive plunger above MOS device district is electrically connected with the second metal interconnecting layer above MOS device district and the 3rd metal interconnecting layer, another part the 3rd conductive plunger is positioned at above sensor regions, and the 3rd conductive plunger above sensor regions is electrically connected with part second metal interconnecting layer above sensor regions and the 3rd metal interconnecting layer;
Before the described first top-level metallic interconnection layer of formation and the second top-level metallic interconnection layer, some 4th conductive plungers are formed in described 4th dielectric layer, a part the 4th conductive plunger is positioned at above MOS device district, and the 4th conductive plunger above MOS device district is electrically connected with the 3rd metal interconnecting layer above MOS device district and the first top-level metallic interconnection layer, another part the 4th conductive plunger is positioned at above sensor regions, and the 4th conductive plunger above sensor regions is electrically connected with the 3rd metal interconnecting layer above sensor regions and the second top-level metallic interconnection layer.
10. the formation method of CMOS gas sensor according to claim 8, it is characterized in that, there is in described sensor-interconnect structure the second metal interconnecting layer of some electrically insulated from one another, the second metal interconnecting layer in described sensor-interconnect structure is also positioned at the second dielectric layer surface in MOS device district, wherein, part second metal interconnecting layer in sensor-interconnect structure is electrically connected with polysilicon zone of heating, and another part second metal interconnecting layer in sensor-interconnect structure is electrically connected with the second top-level metallic interconnection layer; The second metal interconnecting layer in described sensor-interconnect structure is the support arm of hanging structure.
The formation method of 11. CMOS gas sensors according to claim 1, is characterized in that, described sensor regions is the region of gas sensor to be formed; Described MOS device district is the region of MOS signal processor to be formed.
12. 1 kinds of CMOS gas sensors, is characterized in that, comprising:
Substrate, described substrate comprises MOS device district and sensor regions;
Be positioned at the polysilicon gate on section substrate surface, described MOS device district;
Be positioned at the polysilicon zone of heating on section substrate surface, described sensor regions;
Be positioned at the dielectric layer on described MOS device district and sensor regions substrate, and described dielectric layer is covered in polycrystalline silicon gate surface and polysilicon heating layer surface;
Be positioned at MOS device interconnection structure and the sensor-interconnect structure of described dielectric layer;
Wherein, described MOS device interconnection structure is positioned at above MOS device district, described MOS device interconnection structure is electrically connected with polysilicon gate, described MOS device interconnection structure at least comprises 2 layers of metal interconnecting layer, and the metal interconnecting layer in described MOS device district comprises the first top-level metallic interconnection layer, described first top-level metallic interconnection layer top flushes with dielectric layer top;
Described sensor-interconnect structure is positioned at above sensor regions, described sensor-interconnect structure is electrically connected with polysilicon zone of heating, described sensor-interconnect structure at least comprises 2 layers of metal interconnecting layer, the metal interconnecting layer of sensor regions comprises the second top-level metallic interconnection layer, and in described sensor-interconnect structure, having at least 1 floor metal interconnecting layer to be also positioned at above MOS device district, described second top-level metallic interconnection layer top flushes with dielectric layer top;
Be positioned at the passivation layer of described dielectric layer surface and the first top-level metallic interconnect layer surfaces;
Be positioned at the gas sensing layer of described second top-level metallic interconnect layer surfaces;
Around described gas sensing layer and the groove be positioned at above sensor regions, described groove runs through passivation layer above sensor regions and dielectric layer, and described groove exposes the section substrate surface of sensor regions;
By described groove around hanging structure, between described hanging structure and the substrate of sensor regions, there is area of insulation, and flush with bottom dielectric layer bottom described hanging structure.
13. CMOS gas sensors according to claim 12, it is characterized in that, described dielectric layer comprises: the first medium floor being positioned at the substrate surface of MOS device district and sensor regions, the second dielectric layer being positioned at first medium floor surface, be positioned at second dielectric layer surface the 3rd dielectric layer, be positioned at the 4th dielectric layer of the 3rd dielectric layer surface and be positioned at the top layer dielectric layer of the 4th dielectric layer surface.
14. CMOS gas sensors according to claim 13, it is characterized in that, described MOS device interconnection structure comprises 4 layers of metal interconnecting layer, and described MOS device interconnection structure comprises: the 3rd metal interconnecting layer of MOS device district the 3rd dielectric layer surface that is positioned at first metal interconnecting layer on first medium floor surface, MOS device district, is positioned at second metal interconnecting layer on second dielectric layer surface, MOS device district, is positioned at, be positioned at the first top-level metallic interconnection layer of MOS device district the 4th dielectric layer surface.
15. CMOS gas sensors according to claim 14, is characterized in that, described MOS device interconnection structure also comprises: the first conductive plunger being positioned at first medium layer, and described first conductive plunger is electrically connected with polysilicon gate and the first metal interconnecting layer; Be positioned at the second conductive plunger of second dielectric layer, described second conductive plunger is electrically connected with the first metal interconnecting layer and the second metal interconnecting layer; Be positioned at the 3rd conductive plunger of the 3rd dielectric layer, described 3rd conductive plunger is electrically connected with the second metal interconnecting layer and the 3rd metal interconnecting layer; Be positioned at the 4th conductive plunger of the 4th dielectric layer, described 4th conductive plunger is electrically connected with the 3rd metal interconnecting layer and the first top-level metallic interconnection layer.
16. CMOS gas sensors according to claim 13, it is characterized in that, described sensor-interconnect structure comprises 4 layers of metal interconnecting layer, and described sensor-interconnect structure comprises: the 3rd metal interconnecting layer of sensor regions the 3rd dielectric layer surface that is positioned at first metal interconnecting layer on first medium layer surface, sensor regions, is positioned at second metal interconnecting layer on second dielectric layer surface, sensor regions, is positioned at, be positioned at the second top-level metallic interconnection layer of some electrically insulated from one another of sensor regions the 4th dielectric layer surface.
17. CMOS gas sensors according to claim 16, it is characterized in that, described sensor-interconnect structure also comprises: the first conductive plunger being positioned at first medium layer, described first conductive plunger is electrically connected with polysilicon zone of heating and the first metal interconnecting layer, and the first metal interconnecting layer electrically insulated from one another be electrically connected with described polysilicon zone of heating; Be positioned at the second conductive plunger of second dielectric layer, described second conductive plunger is electrically connected with the first metal interconnecting layer and part second metal interconnecting layer; Be positioned at the 3rd conductive plunger of the 3rd dielectric layer, described 3rd conductive plunger is electrically connected with part second metal interconnecting layer and the 3rd metal interconnecting layer, and electric insulation between the 3rd metal interconnecting layer and polysilicon zone of heating; Be positioned at the 4th conductive plunger of the 4th dielectric layer, described 4th conductive plunger is electrically connected with the 3rd metal interconnecting layer and the second top-level metallic interconnection layer.
18. CMOS gas sensors according to claim 16, it is characterized in that, there is in described sensor-interconnect structure the second metal interconnecting layer of some electrically insulated from one another, the second metal interconnecting layer in described sensor-interconnect structure is also positioned at the second dielectric layer surface in MOS device district, wherein, part second metal interconnecting layer in sensor-interconnect structure is electrically connected with polysilicon zone of heating, and another part second metal interconnecting layer in sensor-interconnect structure is electrically connected with the second top-level metallic interconnection layer; The second metal interconnecting layer in described sensor-interconnect structure is the support arm of hanging structure.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710082871.6A CN106847753A (en) | 2015-01-29 | 2015-01-29 | The forming method of the gas sensor of CMOS technique compatible |
| CN201710082872.0A CN106803506A (en) | 2015-01-29 | 2015-01-29 | CMOS gas sensors |
| CN201710082873.5A CN107068681A (en) | 2015-01-29 | 2015-01-29 | The material of gas sensing layer is Nb2O5CMOS gas sensors |
| CN201710082875.4A CN106816439A (en) | 2015-01-29 | 2015-01-29 | The material of gas sensing layer is Ga2O3CMOS gas sensors |
| CN201710084866.9A CN106876394A (en) | 2015-01-29 | 2015-01-29 | Gas sensing layer is SnO2CMOS gas sensors forming method |
| CN201510046466.XA CN104617095B (en) | 2015-01-29 | 2015-01-29 | CMOS gas sensors and forming method thereof |
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| CN201710082875.4A Division CN106816439A (en) | 2015-01-29 | 2015-01-29 | The material of gas sensing layer is Ga2O3CMOS gas sensors |
| CN201710082872.0A Division CN106803506A (en) | 2015-01-29 | 2015-01-29 | CMOS gas sensors |
| CN201710082873.5A Division CN107068681A (en) | 2015-01-29 | 2015-01-29 | The material of gas sensing layer is Nb2O5CMOS gas sensors |
| CN201710082871.6A Division CN106847753A (en) | 2015-01-29 | 2015-01-29 | The forming method of the gas sensor of CMOS technique compatible |
| CN201710084866.9A Division CN106876394A (en) | 2015-01-29 | 2015-01-29 | Gas sensing layer is SnO2CMOS gas sensors forming method |
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| CN201710082871.6A Pending CN106847753A (en) | 2015-01-29 | 2015-01-29 | The forming method of the gas sensor of CMOS technique compatible |
| CN201710082872.0A Pending CN106803506A (en) | 2015-01-29 | 2015-01-29 | CMOS gas sensors |
| CN201710082875.4A Pending CN106816439A (en) | 2015-01-29 | 2015-01-29 | The material of gas sensing layer is Ga2O3CMOS gas sensors |
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| CN201710082872.0A Pending CN106803506A (en) | 2015-01-29 | 2015-01-29 | CMOS gas sensors |
| CN201710082875.4A Pending CN106816439A (en) | 2015-01-29 | 2015-01-29 | The material of gas sensing layer is Ga2O3CMOS gas sensors |
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| CN106876394A (en) | 2017-06-20 |
| CN106816439A (en) | 2017-06-09 |
| CN107068681A (en) | 2017-08-18 |
| CN106803506A (en) | 2017-06-06 |
| CN106847753A (en) | 2017-06-13 |
| CN104617095B (en) | 2017-06-16 |
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