CN106803506A - CMOS gas sensors - Google Patents

CMOS gas sensors Download PDF

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Publication number
CN106803506A
CN106803506A CN201710082872.0A CN201710082872A CN106803506A CN 106803506 A CN106803506 A CN 106803506A CN 201710082872 A CN201710082872 A CN 201710082872A CN 106803506 A CN106803506 A CN 106803506A
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China
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layer
metal interconnecting
sensor
mos device
dielectric layer
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俞挺
袁彩雷
骆兴芳
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Jiangxi Normal University
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Jiangxi Normal University
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Priority to CN201710082872.0A priority Critical patent/CN106803506A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
    • G01N27/02—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance
    • G01N27/04—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance
    • G01N27/12—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance of a solid body in dependence upon absorption of a fluid; of a solid body in dependence upon reaction with a fluid, for detecting components in the fluid
    • G01N27/125—Composition of the body, e.g. the composition of its sensitive layer
    • G01N27/127—Composition of the body, e.g. the composition of its sensitive layer comprising nanoparticles
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects

Abstract

A kind of CMOS gas sensors, wherein CMOS gas sensors include：Substrate；Positioned at the polysilicon gate on section substrate surface；Positioned at the polysilicon zone of heating on section substrate surface；Dielectric layer on substrate；MOS device interconnection structure and sensor-interconnect structure in the dielectric layer；Positioned at the dielectric layer surface and the passivation layer of the first top-level metallic interconnection layer surfaces；Positioned at the gas sensing layer of the second top-level metallic interconnection layer surfaces；Around the gas sensing layer and the groove above sensor regions；By the circular hanging structure of the groove, there is area of insulation between the hanging structure and the substrate of sensor regions, and the hanging structure bottom flushes with dielectric layer bottom.The formation process of gas sensor of the present invention is completely compatible with the formation process of MOS device, and gas sensor and MOS device is integrated on the same chip, reduces chip area, reduces power consumption, improves integrated level and yield.

Description

CMOS gas sensors
Technical field
The present invention relates to field of semiconductor fabrication technology, more particularly to a kind of CMOS gas sensors.
Background technology
Gas sensor is that one kind detects specific composition in gas by certain principle, and handle is detected Certain signal be converted into the device of appropriate electrical signal.With the day the problems such as mankind are to environmental protection, pollution and public safety Benefit is paid attention to, and people, for the continuous improvement of the requirement of living standard, gas sensor is in industrial, civilian and environmental monitoring three Achieved in big major domain and be widely applied.
The difference of the principle of gas is detected according to gas sensor, gas sensor mainly includes catalytic combustion type, electrification Formula, heat-conducted, infrared absorption type and semiconductor-type gas sensor etc..Wherein, semiconductor-type gas sensor includes resistance Formula gas sensor and non-resistor gas sensor, because resistance-type gas sensor has, sensitivity is high, easy to operate, body The advantages of accumulating short small, with low cost, response time and short recovery time so that resistance-type gas sensor has obtained extensively should With for example to flammable explosive gas (such as CH4, H2Deng) and toxic and harmful (such as CO, NOxDeng) detection in play it is important Effect.
It is general, it is desirable to provide signal processing circuit makes the gas sensor normal work, the conventional method of prior art be： Gas sensor and signal processor are formed separately, then gas sensor and signal processor is sealed Dress combination.
Enter according to compatible standard CMOS (Complementary Metal Oxide Semiconductor) technique The making of promoting the circulation of qi body sensor, then can be integrated on the same chip by gas sensor and cmos signal processing apparatus, so that Enhance product performance, reduce chip area, improve integrated, raising yield, reduce production cost etc..Therefore, offer one is provided badly The forming method of new gas sensor is planted, while gas sensor and cmos signal processing apparatus are integrated in into same chip On, and formed gas sensor technique cmos signal processing apparatus will not be had undesirable effect.
The content of the invention
The problem that the present invention is solved is to provide a kind of CMOS gas sensors and forming method thereof, the formation of gas sensor Technique is high with the formation process compatibility of MOS device, reduces chip area, improves integrated level and yield, reduces power consumption and production Cost.
To solve the above problems, the present invention provides a kind of forming method of CMOS gas sensors, including：Substrate is provided, The substrate includes MOS device area and sensor regions；Polysilicon gate is formed on the MOS device area section substrate surface, While forming the polysilicon gate, polysilicon zone of heating is formed on the sensor regions section substrate；In the MOS device Dielectric layer is formed in area and sensor regions substrate, and the dielectric layer is covered in polycrystalline silicon gate surface and polysilicon zone of heating Surface；MOS device interconnection structure and sensor-interconnect structure are formed in the dielectric layer；Wherein, the MOS device interconnection Structure is located at MOS device area top, and the MOS device interconnection structure is electrically connected with polysilicon gate, the MOS device interconnection structure At least include 2 layers of metal interconnecting layer, and the metal interconnecting layer in the MOS device area includes the first top-level metallic interconnection layer, institute The first top-level metallic interconnection layer top is stated to be flushed with dielectric layer top；The part sensor-interconnect structure and polysilicon zone of heating Electrical connection, the sensor-interconnect structure at least includes 2 layers of metal interconnecting layer, and the metal interconnecting layer of sensor regions includes second At least 1 floor metal interconnecting layer is also located at MOS device area top in top-level metallic interconnection layer, and the sensor-interconnect structure, The second top-level metallic interconnection layer top flushes with dielectric layer top, and the second top-level metallic interconnection layer and polysilicon zone of heating Electrically insulated from one another；Passivation layer, and the passivation layer are formed in the dielectric layer surface and the first top-level metallic interconnection layer surfaces Expose the second top-level metallic interconnection layer surfaces；Gas sensing layer is formed in the second top-level metallic interconnection layer surfaces；Using dry method Etching technics, the substrate of the passivation layer, dielectric layer and segment thickness that are sequentially etched around the gas sensing layer, in sensor Area forms the groove around the gas sensing layer；Using isotropic etching technique, along the groove expose positioned at sensor The substrate sidewall surfaces in area are performed etching, segment thickness substrate of the etching removal below polysilicon zone of heating, in the biography Sensor area top is formed has area of insulation between hanging structure, and the hanging structure and the substrate of sensor regions, wherein, hang Hollow structure includes polysilicon zone of heating, certain media layer, sensor-interconnect structure and gas sensing layer.
Optionally, the substrate thickness for using dry etch process to etch removal is 5 microns to 10 microns；Parallel to On the substrate surface direction, the size of the groove is 3 microns to 5 microns.
Optionally, the processing step for forming the groove includes：Formed in the passivation layer surface and air-sensitive layer surface Second photoresist layer, has the annular opening above sensor regions in second photoresist layer, the annular opening is sudden and violent Expose the passivation layer surface around gas sensing layer；With second photoresist layer as mask, along the annular opening expose it is blunt Change layer to perform etching, until the substrate of etching removal segment thickness.
Optionally, using XeF2Carry out the isotropic etching technique；The technique ginseng of the isotropic etching technique Number is：Circulation is carried out to being passed through XeF in etching cavity2With extraction XeF2Action, XeF in etching cavity2Pressure be 100Pa extremely 180Pa, and to being passed through XeF in etching cavity2Maintain 10 seconds to 50 seconds afterwards, cycle-index is 5 to 15 times.
Optionally, the processing step for forming the passivation layer includes：Interconnected in the dielectric layer surface, the first top-level metallic Layer surface and the second top-level metallic interconnection layer surfaces form passivation layer；The first photoresist layer is formed in the passivation layer surface, First photoresist layer exposes the passivation layer surface positioned at the second top-level metallic upperside interconnection layer；With first photoresist Layer is mask, passivation layer of the etching removal positioned at the second top-level metallic interconnection layer surfaces.
Optionally, the material of the gas sensing layer is SnO2Or doped with the SnO of Pt2；Material is formed using magnetron sputtering technique It is SnO2Gas sensing layer, technological parameter is：Sn targets are provided, sputter gas are Ar and O2, wherein, Ar and O2Gas flow ratio Be worth is 2:1 to 5:1, sputtering chamber pressure be 1Pa to 5Pa, there is provided operating voltage be 500V to 1000V, there is provided radio frequency source Power is 100 watts to 200 watts, and the temperature of substrate 100 is 20 degrees Celsius to 50 degrees Celsius.
Optionally, the first oxide layer is also formed between the polysilicon gate and substrate；The polysilicon zone of heating and lining The second oxide layer is also formed between bottom, wherein, the second oxide layer is formed with the first oxide layer in the technique along with；Form institute State polysilicon gate includes with the processing step of polysilicon zone of heating：In the MOS device area and the substrate surface shape of sensor regions Into oxide layer；Polysilicon layer is formed in the oxidation layer surface；The polysilicon layer in the graphical MOS device area and oxidation Layer, forms the first oxide layer and the polysilicon positioned at the first oxidation layer surface positioned at MOS device area section substrate surface Grid；The polysilicon layer and oxide layer of the graphical sensor regions, form second positioned at sensor regions section substrate surface Oxide layer and the polysilicon zone of heating positioned at the second oxidation layer surface.
Optionally, the dielectric layer, MOS device interconnection structure, the forming method of sensor-interconnect structure include：Described Substrate surface forms first medium layer, and first medium layer is covered in polycrystalline silicon gate surface and polysilicon zone of heating table Face；Some first metal interconnecting layers are formed in the first medium layer surface, a part of first metal interconnecting layer is located at MOS device Area top, and the first metal interconnecting layer above MOS device area electrically connects with polysilicon gate, the metal of another part first is mutual Even layer is located at sensor regions top, and the first metal interconnecting layer above sensor regions is electrically connected with polysilicon zone of heating respectively Connect, and the first metal interconnecting layer electrically insulated from one another electrically connected with polysilicon zone of heating；Formation is covered in described first and is situated between Matter layer surface and the second dielectric layer on the first metal interconnecting layer surface；Some second gold medals are formed in the second medium layer surface Category interconnection layer, a part of second metal interconnecting layer is located at MOS device area top, and the second metal above MOS device area Interconnection layer is electrically connected with polysilicon gate, and the metal interconnecting layer of another part second is located at sensor regions top, and positioned at sensor regions The metal interconnecting layer of part second of top is electrically connected with polysilicon zone of heating；Formation be covered in the second medium layer surface and 3rd dielectric layer on the second metal interconnecting layer surface；Some 3rd metal interconnecting layers, one are formed in the 3rd dielectric layer surface The metal interconnecting layer of part the 3rd is located at MOS device area top, and the 3rd metal interconnecting layer and polycrystalline above MOS device area Si-gate is electrically connected, and the metal interconnecting layer of another part the 3rd is located at sensor regions top, the 3rd metal above sensor regions Interconnection layer is electrically connected with the metal interconnecting layer of part second, and the 3rd metal interconnecting layer and polysilicon zone of heating above sensor regions Between be electrically insulated；Formation is covered in the 4th dielectric layer on the 3rd dielectric layer surface and the 3rd metal interconnecting layer surface； The dielectric layer surface of MOS device area the 4th forms the first top-level metallic interconnection layer, the first top-level metallic interconnection layer with it is many Crystal silicon grid are electrically connected, and in the sensor regions the 4th, dielectric layer surface forms the second top-level metallic interconnection of some electrically insulated from one another Layer the second top-level metallic interconnection layer is electrically connected with the 3rd metal interconnecting layer, wherein, the second top-level metallic interconnection layer and First top-level metallic interconnection layer utilizes the technique along with to be formed；Formation is covered in the 3rd dielectric layer surface, the first top layer gold The top layer dielectric layer of category interconnection layer surfaces and the second top-level metallic interconnection layer surfaces, and the top layer dielectric layer and the first top layer Metal interconnecting layer, the second top-level metallic interconnection layer top flush.
Optionally, also including step：Before first metal interconnecting layer is formed, formed in first medium layer Some first conductive plungers, a part of first conductive plunger is located at MOS device area top, and first leading above MOS device area Electric plug is electrically connected with the first metal interconnecting layer above polysilicon gate and MOS device area, the conductive plunger of another part first Positioned at sensor regions top, and the first conductive plunger above sensor regions and polysilicon zone of heating and sensor regions top The first metal interconnecting layer electrical connection；Before second metal interconnecting layer is formed, if being formed in the second dielectric layer Dry second conductive plunger, a part of second conductive plunger is located at MOS device area top, and the second conduction above MOS device area Connector is electrically connected with the first metal interconnecting layer and the second metal interconnecting layer above MOS device area, and another part second is conductive Connector is located at sensor regions top, and the second conductive plunger above sensor regions and the first metal interconnection above sensor regions Layer and the electrical connection of the metal interconnecting layer of part second；Before the 3rd metal interconnecting layer is formed, in the 3rd dielectric layer Interior to form some 3rd conductive plungers, a part of 3rd conductive plunger is located at MOS device area top, and above MOS device area 3rd conductive plunger is electrically connected with the second metal interconnecting layer and the 3rd metal interconnecting layer above MOS device area, another part 3rd conductive plunger is located at sensor regions top, and the 3rd conductive plunger above sensor regions and the part above sensor regions Second metal interconnecting layer and the 3rd metal interconnecting layer are electrically connected；Forming the first top-level metallic interconnection layer and the second top Before layer metal interconnecting layer, some 4th conductive plungers, a part of 4th conductive plunger position are formed in the 4th dielectric layer In MOS device area top, and the 4th conductive plunger above MOS device area and the 3rd metal interconnecting layer above MOS device area And the first top-level metallic interconnection layer electrical connection, the conductive plunger of another part the 4th is located at sensor regions top, and sensor regions 4th conductive plunger of top is electrically connected with the 3rd metal interconnecting layer and the second top-level metallic interconnection layer above sensor regions.
Optionally, the second metal interconnecting layer with some electrically insulated from one another, the biography in the sensor-interconnect structure The second metal interconnecting layer in sensor interconnection structure is also located at the second medium layer surface in MOS device area, wherein, sensor-interconnect The metal interconnecting layer of part second in structure is electrically connected with polysilicon zone of heating, the another part second in sensor-interconnect structure Metal interconnecting layer is electrically connected with the second top-level metallic interconnection layer；The second metal interconnecting layer in the sensor-interconnect structure is outstanding The support arm of hollow structure.
Optionally, the sensor regions are the region of gas sensor to be formed；The MOS device area is MOS to be formed The region of signal processor.
The present invention also provides a kind of CMOS gas sensors, including：Substrate, the substrate includes MOS device area and biography Sensor area；Positioned at the polysilicon gate on the MOS device area section substrate surface；Positioned at the sensor regions section substrate surface Polysilicon zone of heating；Dielectric layer in the MOS device area and sensor regions substrate, and the dielectric layer be covered in it is many Crystal silicon grid surface and polysilicon heating layer surface；MOS device interconnection structure and sensor in the dielectric layer is mutual Link structure；Wherein, the MOS device interconnection structure is located at MOS device area top, the MOS device interconnection structure and polysilicon Grid electrically connect, the MOS device interconnection structure at least include 2 layers of metal interconnecting layer, and the MOS device area metal interconnecting layer Include the first top-level metallic interconnection layer, the first top-level metallic interconnection layer top flushes with dielectric layer top；The sensing Device interconnection structure is located at sensor regions top, and the sensor-interconnect structure is electrically connected with polysilicon zone of heating, the sensor Interconnection structure at least includes 2 layers of metal interconnecting layer, and the metal interconnecting layer of sensor regions includes the second top-level metallic interconnection layer, and At least 1 floor metal interconnecting layer is also located at MOS device area top in the sensor-interconnect structure, and second top-level metallic is mutual Even layer top flushes with dielectric layer top；Positioned at the passivation of the dielectric layer surface and the first top-level metallic interconnection layer surfaces Layer；Positioned at the gas sensing layer of the second top-level metallic interconnection layer surfaces；Around the gas sensing layer and above sensor regions Groove, passivation layer and dielectric layer of the groove above sensor regions, and the groove exposes the portion of sensor regions Divide substrate surface；Have by the circular hanging structure of the groove, between the hanging structure and the substrate of sensor regions heat-insulated Region, and the hanging structure bottom flushes with dielectric layer bottom.
Optionally, the dielectric layer includes：First medium floor positioned at MOS device area and the substrate surface of sensor regions, Second dielectric layer positioned at first medium layer surface, the 3rd dielectric layer positioned at second medium layer surface, positioned at the 3rd dielectric layer 4th dielectric layer on surface and the top layer dielectric layer positioned at the 4th dielectric layer surface.
Optionally, the MOS device interconnection structure includes 4 layers of metal interconnecting layer, and the MOS device interconnection structure includes： The first metal interconnecting layer positioned at MOS device area first medium layer surface, positioned at MOS device area second medium layer surface second Metal interconnecting layer, the 3rd metal interconnecting layer positioned at the dielectric layer surface of MOS device area the 3rd, positioned at the medium of MOS device area the 4th First top-level metallic interconnection layer of layer surface.
Optionally, the MOS device interconnection structure also includes：The first conductive plunger in first medium layer, it is described First conductive plunger is electrically connected with polysilicon gate and the first metal interconnecting layer；In second dielectric layer second is conductive slotting Plug, second conductive plunger is electrically connected with the first metal interconnecting layer and the second metal interconnecting layer；In the 3rd dielectric layer The 3rd conductive plunger, the 3rd conductive plunger electrically connects with the second metal interconnecting layer and the 3rd metal interconnecting layer；It is located at The 4th conductive plunger in 4th dielectric layer, the 4th conductive plunger is mutual with the 3rd metal interconnecting layer and the first top-level metallic Even layer electrical connection.
Optionally, the sensor-interconnect structure includes 4 layers of metal interconnecting layer, and the sensor-interconnect structure includes：Position The first metal interconnecting layer in sensor regions first medium layer surface, the second metal positioned at sensor regions second medium layer surface Interconnection layer, the 3rd metal interconnecting layer positioned at the dielectric layer surface of sensor regions the 3rd, positioned at the dielectric layer surface of sensor regions the 4th Some electrically insulated from one another the second top-level metallic interconnection layer.
Optionally, the sensor-interconnect structure also includes：The first conductive plunger in first medium layer, described the One conductive plunger is electrically connected with polysilicon zone of heating and the first metal interconnecting layer, and electrically connected with the polysilicon zone of heating First metal interconnecting layer electrically insulated from one another；The second conductive plunger in second dielectric layer, second conductive plunger and One metal interconnecting layer and the metal interconnecting layer of part second are electrically connected；The 3rd conductive plunger in the 3rd dielectric layer, it is described 3rd conductive plunger is electrically connected with the metal interconnecting layer of part second and the 3rd metal interconnecting layer, and the 3rd metal interconnecting layer with it is many It is electrically insulated between crystal silicon zone of heating；The 4th conductive plunger in the 4th dielectric layer, the 4th conductive plunger and the 3rd gold medal Category interconnection layer and the electrical connection of the second top-level metallic interconnection layer.
Optionally, the second metal interconnecting layer with some electrically insulated from one another, the biography in the sensor-interconnect structure The second metal interconnecting layer in sensor interconnection structure is also located at the second medium layer surface in MOS device area, wherein, sensor-interconnect The metal interconnecting layer of part second in structure is electrically connected with polysilicon zone of heating, the another part second in sensor-interconnect structure Metal interconnecting layer is electrically connected with the second top-level metallic interconnection layer；The second metal interconnecting layer in the sensor-interconnect structure is outstanding The support arm of hollow structure.
Compared with prior art, technical scheme has advantages below：
In the technical scheme of the forming method of the CMOS gas sensors that the present invention is provided, many of MOS device area are being formed While crystal silicon grid, polysilicon zone of heating is formed on the section substrate of sensor regions；In MOS device area and sensor regions substrate Dielectric layer is formed, and dielectric layer is also covered in polycrystalline silicon gate surface and polysilicon heating layer surface；Then the shape in dielectric layer Into MOS device interconnection structure and sensor-interconnect structure, wherein, MOS device interconnection structure be located at MOS device area top and with Polysilicon gate is electrically connected, and sensor-interconnect structure is located at sensor regions top and is electrically connected with polysilicon zone of heating；Then it is being situated between Matter layer surface and the first top-level metallic interconnection layer surfaces form passivation layer, in the second top-level metallic that the passivation layer exposes Interconnection layer surfaces form gas sensing layer；Then, using dry etch process, it is sequentially etched the passivation layer around gas sensing layer, is situated between The substrate of matter layer and segment thickness, the groove around gas sensing layer is formed in sensor regions；Using using isotropic etching work Skill, performs etching along the substrate sidewall surfaces positioned at sensor regions that the groove exposes, and etching removal adds positioned at polysilicon Segment thickness substrate below thermosphere, forms hanging structure, and the hanging structure and sensor above the sensor regions There is area of insulation between the substrate in area, wherein, hanging structure includes polysilicon zone of heating, certain media layer, sensor-interconnect Structure and gas sensing layer.The formation process of gas sensor and the formation process of MOS device are completely compatible in the present invention, can be by MOS device is integrated on the same chip with gas sensor, reduces chip area, improves integrated level and yield, reduces work( Consumption and production cost.
Further, it is SnO to use magnetron sputtering technique to form material in the present invention2Gas sensing layer, technological parameter is：There is provided Sn targets, sputter gas are Ar and O2, wherein, Ar and O2Gas flow ratio be 2:1 to 5:1, sputtering chamber pressure is 1Pa To 5Pa, there is provided operating voltage be 500V to 1000V, there is provided RF source power be 100 watts to 200 watts, the temperature of substrate 100 Spend is 20 degrees Celsius to 50 degrees Celsius.When the technological parameter provided using the present invention forms gas sensing layer, Sn atoms and O atom have Enough energy, make Sn atoms and O atom carry out sufficient travel motion on the surface of the second top-level metallic interconnection layer 423, so that So that the gas sensing layer thickness for being formed is uniform and with larger specific surface area.
Also, when gas sensing layer is formed using magnetron sputtering technique, the partial pressure of oxygen in sputtering chamber is moderate, specifically for the present invention , Ar and O2Gas flow ratio be 2:1 to 5:1, it is to avoid gas sensing layer oxidation excessively abundant or degree of oxidation is too low, the shape for making Into gas sensing layer in oxygen content it is moderate so that sensitivity of the gas sensing layer to gas is larger.
Further, the substrate thickness of dry etch process etching removal is 5 microns to 10 microns in the present invention so that after The moderate dimensions of the continuous area of insulation for being formed, it is to avoid due to the distance between hanging structure and substrate it is too small caused by polysilicon Heat in zone of heating is difficult release；Also, isotropic etching technique can also be avoided to etch the thickness mistake of the substrate of removal Thickness, prevents polysilicon zone of heating to be subject to excessive stress, it is to avoid polysilicon zone of heating is deformed upon.
Accordingly, the present invention also provides a kind of structural behaviour superior CMOS gas sensors.
Brief description of the drawings
The cross-section structure of the CMOS gas sensor forming processes that Fig. 1 to Figure 15 is provided for one embodiment of the invention is illustrated Figure.
Specific embodiment
From background technology, manufacture craft and the CMOS technology poor compatibility of prior art gas sensor, it is difficult to adopt Gas sensor is made with the CMOS technology of standard.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention Specific embodiment be described in detail.
The cross-section structure of the CMOS gas sensor forming processes that Fig. 1 to Figure 15 is provided for one embodiment of the invention is illustrated Figure.
With reference to Fig. 1, there is provided substrate 100, the substrate 100 includes MOS device area I and sensor regions II.
The material of the substrate 100 is silicon, germanium, SiGe, carborundum or GaAs, and the substrate 100 can also be exhausted The germanium on silicon, insulator on edge body or the SiGe on insulator.The surface of the substrate 100 can also form some extensions Boundary layer or strained layer, to improve the electric property of CMOS gas sensors.
In the present embodiment, the substrate 100 is silicon substrate.The MOS device area I is MOS signal processors to be formed Region, be subsequently formed PMOS transistor, nmos pass transistor or CMOS transistor and signal processing circuit platform be provided, for detecting Or the electric signal in collection gas sensor；The sensor regions II is the region of gas sensor to be formed, to be subsequently formed Gas sensor provides workbench.Isolation structure, the isolation structure can also be formed in the MOS device area I substrates 100 Can be fleet plough groove isolation structure (STI, Shallow Trench Isolation), the packing material of isolation structure is oxidation The insulating materials such as silicon, silicon nitride or silicon oxynitride.
Some well regions can also be formed in MOS device area I substrates 100, the type of the well region is according to MOS to be formed The type of device determines that the doping type of the well region is that n-type doping or p-type are adulterated.For example, on part MOS device area I shape During into nmos pass transistor, then P type trap zone is formed in corresponding MOS device area I substrates 100, the Doped ions of the P type trap zone are B, Ga or In；When forming PMOS transistor on part MOS device area I, then N is formed in corresponding MOS device area I substrates 100 Type well region, the Doped ions of the N-type well region are P, As or Sb.
The present embodiment is with a MOS device area I, a sensor regions II as an example, being accordingly subsequently formed gas sensing The quantity of device is 1, and on parallel to the surface direction of substrate 100, the size of the sensor regions I is 10 microns × 10 microns to 50 Micron × 50 microns.In other embodiments, the quantity in MOS device area can be any natural number more than or equal to 1, sensor The quantity in area can also be any natural number more than or equal to 1, the then quantity of the gas sensor being correspondingly formed and sensor regions Quantity it is identical.
In the present embodiment, subsequently PMOS transistor is formed as an example with MOS device area I.
With reference to Fig. 2, oxide layer 101 is formed on the surface of substrate 100 of the MOS device area I and sensor regions II；Described The surface of oxide layer 101 forms polysilicon layer 102.
Oxide layer 101 positioned at MOS device area I subsequently is additionally operable to form the gate dielectric layer in nmos pass transistor.The oxygen The material for changing layer 101 is silica；The oxygen is formed using chemical vapor deposition, physical vapour deposition (PVD) or atom layer deposition process Change layer 101.
It is subsequently used for forming the polysilicon gate in PMOS transistor positioned at the polysilicon layer 102 of MOS device area I；Positioned at biography The polysilicon layer 102 of sensor area II is subsequently used for being formed the polysilicon zone of heating of gas sensor.The material of the polysilicon layer 102 The polysilicon for polysilicon or doping is expected, for example, the polysilicon of doping P or B；Using chemical vapor deposition method, physical vapor Depositing operation or atom layer deposition process form the polysilicon layer 102.
In the present embodiment, the material of the oxide layer 101 is silica, and the oxygen is formed using chemical vapor deposition method Change layer 101；The material of the polysilicon layer 102 is polysilicon, and the polysilicon layer is formed using chemical vapor deposition method 102。
With reference to Fig. 3, the polysilicon layer 102 (referring to Fig. 2) and oxide layer 101 of the graphical MOS device area I (are referred to Fig. 2), formed positioned at first oxide layer 111 on the surface of MOS device area I section substrates 100 and positioned at the table of the first oxide layer 111 The polysilicon gate 112 in face；The polysilicon layer 102 and oxide layer 101 of the graphical sensor regions II, form and are located at sensor Second oxide layer 121 and the polysilicon zone of heating positioned at the surface of the second oxide layer 121 on the surface of area II section substrates 100 122。
In the present embodiment, in the technique along with, the polycrystalline of the graphical MOS device area I and sensor regions II is carried out Silicon layer 102 and oxide layer 101.
Specifically, the polysilicon layer 102 and the processing step of oxide layer 101 of graphical MOS device area I and sensor regions II Including：Graph layer is formed on the surface of the polysilicon layer 102, the material of the graph layer can be photoresist or hard mask material Material, the region of the graph layer covering corresponds to the region of follow-up polysilicon gate to be formed 112 and polysilicon zone of heating 122； Then, with the graph layer as mask, etching removes the polysilicon layer 102 and oxide layer 101, until exposing substrate 100 surfaces；Then, the graph layer is removed.
In the present embodiment, polysilicon gate 112, and the polycrystalline are formed on the surface of MOS device area I section substrates 100 The first oxide layer 111 is formed between Si-gate 112 and substrate 100；While polysilicon gate 112 are formed, in the biography The surface of sensor area II section substrates 100 forms polysilicon zone of heating 122, and between the polysilicon zone of heating 122 and substrate 100 It is formed with the second oxide layer 121.
First oxide layer 111 and polysilicon gate 112 constitute the grid structure of MOS device.The polysilicon zone of heating 122 as gas sensor adding thermal resistance, produced in polysilicon zone of heating 122 when subsequent current flows through polysilicon zone of heating 122 Raw joule's heat energy, so as to be heated to the gas sensing layer being subsequently formed, improves the sensitivity of gas sensing layer sensing gas, shortens gas The response time of sensor.
On parallel to the direction on the surface of substrate 100, the section shape of the polysilicon zone of heating 112 is square, square wave Shape, zig-zag, annular or spirality, wherein, spirality can be square spiral.
In the present embodiment, being shaped as the polysilicon zone of heating 122 is square, and the thickness of polysilicon zone of heating 122 is received for 2 Rice is to 300 nanometers.
After the grid structure for forming MOS device, also including step：Substrate 100 to grid structure both sides is mixed It is miscellaneous, it is correspondingly formed source region and the drain region of MOS device.
With reference to Fig. 4, first medium floor 103 is formed in the MOS device area I and the surface of sensor regions II substrate 100, and The first medium layer 103 is covered in the surface of polysilicon gate 112 and the surface of polysilicon zone of heating 122.
The first medium layer 103 is not only covered in the sidewall surfaces of polysilicon gate 112, the side wall table of polysilicon zone of heating 122 Face, is also covered in the top surface of polysilicon gate 112, the top surface of polysilicon zone of heating 122.The material of the first medium layer 103 Expect to be insulating materials, the material of first medium layer 103 can be silica, silicon nitride or silicon oxynitride.
In the present embodiment, the first medium layer 103 is formed using chemical vapor deposition method, first medium layer 103 Material is silica.
Extended meeting afterwards forms dielectric layer on MOS device area I and sensor regions II substrate 100, then the shape in dielectric layer Into MOS device interconnection structure and sensor-interconnect structure, the MOS device interconnection structure is located at MOS device area I tops, and The MOS device interconnection structure is electrically connected with polysilicon gate 112；The sensor-interconnect structure is located at sensor regions II tops, And the sensor-interconnect structure is electrically connected with polysilicon zone of heating 122, wherein, the MOS device interconnection structure at least includes 2 Layer metal interconnecting layer, the sensor-interconnect structure at least includes 2 layers of metal interconnecting layer.
The present embodiment is follow-up to include 4 layers of metal interconnecting layer with MOS device interconnection structure, and sensor-interconnect structure includes 4 layers Interconnection structure is as an example.
With reference to Fig. 5, some first conductive plungers 301 are formed in first medium layer 103, a part first is conductive to insert Plug 301 positioned at MOS device area I top, the first conductive plunger of another part 301 be located at sensor regions II top.
In the present embodiment, the top of first conductive plunger 301 flushes with the top of first medium layer 103；MOS device area I First conductive plunger 301 of top is electrically connected with the transistor in MOS device, such as source electrode, drain electrode or polycrystalline with transistor Si-gate 112 is electrically connected, the first metal that the first conductive plunger 301 above MOS device area I is also subsequently formed with MOS device area I Interconnection layer is electrically connected.
The first conductive plunger 301 above the II of sensor regions is electrically connected with polysilicon zone of heating 122, conductive slotting by first Plug 301 provides electric current to polysilicon zone of heating 122, so as to joule's heat energy is produced in polysilicon zone of heating 122, on the II of sensor regions The first metal interconnecting layer that first conductive plunger 301 of side is also subsequently formed with sensor regions II is electrically connected.
The processing step for forming first conductive plunger 301 includes：Figure is formed on 103 surface of first medium layer Layer；First medium layer 103 described in the graph layer as mask etching, multiple first is formed in first medium layer 103 Conductive through hole, source electrode, drain electrode and the polysilicon gate 112 of transistor are gone out positioned at the first conductive through hole bottom-exposed of MOS device area I Surface, the first conductive through hole bottom-exposed positioned at sensor regions II goes out the surface of polysilicon zone of heating 122；Form filling full described Flushed with the top of first medium layer 103 at the top of first conductive plunger 301 of the first conductive through hole, and the conductive plunger 301.
The material of first conductive plunger 301 is metal, and such as material of the first conductive plunger 301 can be copper, aluminium Or tungsten.
With reference to Fig. 6, some first metal interconnecting layers 401, first metal are formed on 103 surface of first medium layer Interconnection layer 401 is electrically connected with the first conductive plunger 301；Formation is covered in the surface of the first metal interconnecting layer 401 and first The second dielectric layer 104 on the surface of dielectric layer 103.
In the present embodiment, a part of first metal interconnecting layer 401 is located at MOS device area I tops, and MOS device area I tops The first metal interconnecting layer 401 electrically connected with polysilicon gate 112, specifically make the first metal mutual by the first conductive plunger 301 Even layer 401 is electrically connected with polysilicon gate 112.The metal interconnecting layer of another part first is located at sensor regions II tops, and positioned at biography The first metal interconnecting layer 401 above sensor area II is electrically connected by the first conductive plunger 301 with polysilicon zone of heating 122, and The electrically insulated from one another of the first metal interconnecting layer 401 electrically connected with polysilicon zone of heating 122 so that subsequent current via One first metal interconnecting layer 401 is flowed into polysilicon zone of heating 122, is then flowed out via another first metal interconnecting layer 401.
The material of first metal interconnecting layer 401 is metal, and such as material of the first metal interconnecting layer 401 is copper, aluminium Or tungsten.
First metal interconnecting layer 401 is made by deposition, etching technics.Specifically, it is mutual to form first metal Even the processing step of layer 401 includes：In the first medium 103 surface of layer and the surface of the first conductive plunger 301 deposition first Metal interconnection film；Graph layer is formed on the first metal interconnection film surface；With the graph layer as mask, etching described first Metal interconnection film, some first metal interconnecting layers 401 are formed on 103 surface of first medium layer.
In the present embodiment, the first metal interconnecting layer 401 above the sensor regions II is only located at the upper of sensor regions II Side.In other embodiments, the first metal interconnecting layer above sensor regions may be located in addition to positioned at sensor regions top First medium layer surface above the MOS device area of part.
The material of the second dielectric layer 104 is insulating materials, can use chemical vapor deposition, physical vapour deposition (PVD) or original Sublayer depositing operation forms the second dielectric layer 104.The top surface of the second dielectric layer 104 is higher than the first metal interconnecting layer 401 top surfaces.
Then, the second conductive plunger 302 is formed in the second dielectric layer 104.
A part of second conductive plunger 302 positioned at MOS device area I top, second conductive plunger 302 with The first metal interconnecting layer 401 above MOS device area I is electrically connected；The second conductive plunger 302 is located at sensor described in another part Area II tops, second conductive plunger 302 is electrically connected with the first metal interconnecting layer 401 above the II of sensor regions.
The forming method of second conductive plunger 302 refers to the forming method of foregoing first conductive plunger 301.
With reference to Fig. 7, the second metal interconnecting layer 402 of some electrically insulated from one another is formed on the surface of the second dielectric layer 104, Part second metal interconnecting layer 402 is electrically connected with the second conductive plunger 302；Formation is covered in second metal interconnecting layer 402 surfaces and the 3rd dielectric layer 105 on the surface of second dielectric layer 104.
In the present embodiment, a part of second metal interconnecting layer 402 is located at MOS device area I tops, and positioned at MOS device area I Second metal interconnecting layer 402 of top is electrically connected with polysilicon gate 112.The second metal interconnecting layer of another part 402 is located at sensing Device area II tops, and the second metal interconnecting layer of part 402 above the II of sensor regions is electrically connected with polysilicon zone of heating 122 Connect, the second metal interconnecting layer of the part 402 is electrically connected with the second conductive plunger 302 above the II of sensor regions, so as to realize Polysilicon zone of heating 122 is electrically connected with the second metal interconnecting layer of part 402 in sensor-interconnect structure, second for being subsequently formed Top-level metallic interconnection layer can be electrically connected with the second metal interconnecting layer of another part 402.
The forming method of second metal interconnecting layer 402 refers to the forming method of foregoing first metal interconnecting layer 401. In other embodiments, the conductive plunger 302 of second metal interconnecting layer 402 and second can also use Damascus technics shape Into.
In the present embodiment, the part of the second metal interconnecting layer 402 above the II of sensor regions is located at sensor regions II tops, passes The second metal interconnecting layer 402 also part above sensor area II is located at the surface of second dielectric layer 104 of MOS device area I, so that Obtain subsequently when hanging structure is formed, the second metal interconnecting layer 402 can be as the support arm of hanging structure so that hanging structure Stable is suspended on sensor regions II tops.When the quantity of the second metal interconnecting layer 402 is 4, it is believed that hanging structure has There are 4 support arms.
The material of the 3rd dielectric layer 105 is insulating materials, and in the present embodiment, the material of the 3rd dielectric layer 105 is oxygen SiClx.
With reference to Fig. 8, the 3rd conductive plunger 303 is formed in the 3rd dielectric layer 105；In the 3rd dielectric layer 105 Surface forms some 3rd metal interconnecting layers 403, and the 3rd metal interconnecting layer 403 is electrically connected with the 3rd conductive plunger 303；Shape Into the 4th dielectric layer 106 for being covered in the surface of the 3rd metal interconnecting layer 403 and the surface of the 3rd dielectric layer 105；Described The 4th conductive plunger 304 is formed in 4th dielectric layer 106；The surface shape of the 4th dielectric layer 106 above the MOS device area I Into the first top-level metallic interconnection layer 413, the surface of the 4th dielectric layer 106 above the sensor regions II forms some mutual electricity Second top-level metallic interconnection layer 423 of insulation；In the surface of the 4th dielectric layer 106, the table of the first top-level metallic interconnection layer 413 Face and the surface of the second top-level metallic interconnection layer 423 form top layer dielectric layer 107, and the top of the top layer dielectric layer 107 and the One top-level metallic interconnection layer 413, the top of the second top-level metallic interconnection layer 423 flush.
Forming method about the 3rd conductive plunger 303, the 4th conductive plunger 304 refers to foregoing second conductive plunger 302 forming method, the forming method about the 3rd metal interconnecting layer 403 refers to the shape of foregoing second metal interconnecting layer 402 Into method, the forming method about the 4th dielectric layer 106 refers to the forming method of foregoing 3rd dielectric layer 105.
The metal interconnecting layer 403 of a part the 3rd is located at MOS device area I tops, and the above MOS device area I the 3rd Metal interconnecting layer 403 is electrically connected with polysilicon gate 112.The metal interconnecting layer 403 of another part the 3rd is located at sensor regions II tops, The 3rd metal interconnecting layer 403 above the II of sensor regions is electrically connected with the second metal interconnecting layer of part 402, and sensor regions It is electrically insulated between the 3rd metal interconnecting layer 403 and polysilicon zone of heating 122 above II.
The conductive plunger 303 of a part the 3rd is located at MOS device area I tops, and the 3rd conductive inserting above MOS device area I Plug 303 is electrically connected with the second metal interconnecting layer 402 and the 3rd metal interconnecting layer 403 above MOS device area I.Another part 3rd conductive plunger 303 is located at sensor regions II tops, and the 3rd conductive plunger 303 above the II of sensor regions and sensor regions Part the second metal interconnecting layer 402 and the 3rd metal interconnecting layer 403 above II are electrically connected, wherein, the metal of part second is mutual Even layer 402 refers to the second metal interconnecting layer 402 not electrically connected with polysilicon zone of heating 122.
The conductive plunger 304 of a part the 4th is located at MOS device area I tops, and the 4th conductive inserting above MOS device area I Plug 304 is electrically connected with the 3rd metal interconnecting layer 403 and the first top-level metallic interconnection layer 413 above MOS device area I.It is another The conductive plunger 304 of part the 4th is located at sensor regions II tops, and the 4th conductive plunger 304 and sensing above the II of sensor regions The 3rd metal interconnecting layer 403 and the second top-level metallic interconnection layer 423 above device area II are electrically connected.
In other embodiments, the formation process of the 3rd conductive plunger 303 and the 3rd metal interconnecting layer 403 can be with It is Damascus technics.
In the present embodiment, the 3rd metal interconnecting layer 403 above the II of sensor regions is only located at the top of sensor regions II. In other embodiment, the 3rd metal interconnecting layer 403 above the II of sensor regions may be located on MOS device area I tops.Described One top-level metallic interconnection layer 413 is formed with the second top-level metallic interconnection layer 423 using the technique along with.Specifically, forming described The processing step of the first top-level metallic interconnection layer 413 and the second top-level metallic interconnection layer 423 includes：In the table of the 4th dielectric layer 106 Face forms top-level metallic interconnection film；Graph layer is formed on the top-level metallic interconnection film surface；Carved by mask of the graph layer The top-level metallic interconnection film is lost, I forms the first top-level metallic interconnection layer 413 in MOS device area, II forms the in sensor regions Two top-level metallic interconnection layers 423.
In other embodiments, the first top-level metallic interconnection layer 413, the second top-level metallic interconnection layer the 423, the 4th are conductive inserts Plug 304 can be formed using Damascus technics.
In the present embodiment, the second metal interconnecting layer of part 402 and the electricity of polysilicon zone of heating 122 in sensor-interconnect structure Connection, the second metal interconnecting layer of another part 402 in sensor-interconnect structure is electrically connected with the second top-level metallic interconnection layer 423 Connect.The present embodiment with the quantity of the second top-level metallic interconnection layer 423 as 4 as an example, because Fig. 8 is cross-sectional view, Therefore 2 the second top-level metallic interconnection layers 423 be illustrate only in Fig. 8.Then, formed and be covered in the table of the top layer dielectric layer 107 Face, the surface of the first top-level metallic interconnection layer 413, the passivation layer 108 on the surface of the second top-level metallic interconnection layer 423.
The passivation layer 108 is used to protect the first top-level metallic interconnection layer 413, the second top-level metallic interconnection layer 423, it is to avoid First top-level metallic interconnection layer 413, the second top-level metallic interconnection layer 423 are oxidized or sustain damage.
In the present embodiment, dielectric layer, the dielectric layer bag are formed on MOS device area I and sensor regions II substrate 100 Include：First medium layer 103, positioned at first medium layer 103 surface second dielectric layer 104, positioned at the surface of second dielectric layer 104 3rd dielectric layer 105, the 4th dielectric layer 106 positioned at the surface of the 3rd dielectric layer 105 and positioned at the surface of the 4th dielectric layer 106 Top layer dielectric layer 107.
In the present embodiment, MOS device interconnection structure is located at MOS device area top, and MOS device interconnection structure and polysilicon Grid 112 are electrically connected, and MOS device interconnection structure includes 4 layers of metal interconnecting layer.Specifically, MOS device interconnection structure includes：It is located at First metal interconnecting layer 401 on the surface of MOS device area I tops first medium floor 103, positioned at the surface of second dielectric layer 104 the Two metal interconnecting layers 402, the 3rd metal interconnecting layer 403 positioned at the surface of the 3rd dielectric layer 105, positioned at the table of the 4th dielectric layer 106 The first top-level metallic interconnection layer 413 in face；MOS device interconnection structure also includes：Positioned at MOS device area I tops first medium floor The first conductive plunger 301 in 103, the second conductive plunger 302 in second dielectric layer 104, positioned at the 3rd dielectric layer 105 In the 3rd conductive plunger 303 and the 4th conductive plunger 304 in the 4th dielectric layer 106.
In other embodiments, MOS device interconnection structure can include 2 layers, 3 layers, 5 layers or 6 layers any amount layer metal Interconnection layer.
In the present embodiment, sensor-interconnect structure is located at sensor regions II tops, and the part sensor-interconnect structure Electrically connected with polysilicon zone of heating 122, sensor-interconnect structure includes 4 layers of metal interconnecting layer.Specifically, sensor-interconnect structure Including：Positioned at sensor regions II top first medium layer 103 surface the first metal interconnecting layer 401, positioned at second dielectric layer 104 Second metal interconnecting layer 402 on surface, the 3rd metal interconnecting layer 403 positioned at the surface of the 3rd dielectric layer 105, positioned at the 4th medium The second top-level metallic interconnection layer 423 on 106 surface of layer；Sensor-interconnect structure also includes：Positioned at sensor regions II tops first The first conductive plunger 301 in dielectric layer 103, the second conductive plunger 302 in second dielectric layer 104, positioned at the 3rd be situated between The 3rd conductive plunger 303 in matter layer 105 and the 4th conductive plunger 304 in the 4th dielectric layer 106.
In other embodiments, sensor-interconnect structure can include that 2 layers, 3 layers, 5 layers or 6 layers any amount layer metal are mutual The number of plies of even layer, and the metal interconnecting layer of sensor-interconnect structure and the number of plies phase of the metal interconnecting layer of MOS device interconnection structure Deng.
In the present embodiment, at least 1 floor metal interconnecting layer is also located at MOS device area I tops in sensor-interconnect structure, from And cause that subsequently after hanging structure is formed, the metal interconnecting layer in sensor-interconnect structure can be used as hanging structure Support arm, so as to play a part of support hanging structure, prevent hanging structure from dropping.For example, being located at sensor regions II tops The first metal interconnecting layer 401, the second metal interconnecting layer 402, the 3rd metal interconnecting layer 403 or the second top-level metallic interconnection layer One or more layers metal interconnecting layer in 423 is located at MOS device area I tops.
In the present embodiment, it is contemplated that the equilibrium problem of hanging structure so that hanging structure it is more stable be supported on sensor The top of substrate 100 of area II, the second metal interconnecting layer 402 in sensor-interconnect structure is also located at MOS device area I tops, i.e., The part of the second metal interconnecting layer 402 in sensor-interconnect structure is covered in the surface of second dielectric layer 104 of MOS device area I.
With reference to Fig. 9, the first photoresist layer 109 is formed on the surface of the passivation layer 108, first photoresist layer 109 is sudden and violent Expose the surface of passivation layer 108 directly over the second top-level metallic interconnection layer 423.
First photoresist layer 109 is passivation of the subsequent etching removal positioned at the surface of the second top-level metallic interconnection layer 423 The mask of layer 108 so that the passivation layer 108 positioned at the surface of the second top-level metallic interconnection layer 423 is etched removal, so that second The surface of top-level metallic interconnection layer 423 is exposed, to form gas sensing layer on the surface of the second top-level metallic interconnection layer 423.
In a specific embodiment, the processing step for forming first photoresist layer 109 includes：In the passivation layer 108 surfaces form initial lithographic glue-line；It is exposed technique and developing process to the initial lithographic glue-line, forms described the One photoresist layer 109.
With reference to Figure 10, with first photoresist layer 109 as mask, etching removal position the second top-level metallic interconnection layer 423 The passivation layer 108 of surface, is exposed the surface of the second top-level metallic interconnection layer 423.
Can be located at using the dry etch process such as reactive ion etching process or plasma etch process, etching removal Passivation layer 108 directly over second top-level metallic interconnection layer 423.
With reference to Figure 11, gas sensing layer 110 is formed on the surface of the second top-level metallic interconnection layer 423.
Gas sensing layer 110 is used to adsorb the gas in environment, and when gas sensor is in running order, gas sensing layer 110 is inhaled Resistance changes after attached gas, and the resistance value of corresponding gas sensing layer 110 is different when gas concentration is different, by detecting gas sensing layer The concentration for being sized to know gas in environment of 110 resistance value.
The material of the gas sensing layer 110 can be SnO2、ZnO2、Ga2O3、TiO2Or Nb2O5.According to required gas to be detected The type of body is different, selects different gas sensitives as the material of gas sensing layer 110.
In order to improve selectivity and sensitivity of the gas sensing layer 110 to gas, shorten the reaction time of gas sensor, may be used also So that to catalyst material is added in gas sensing layer 110, catalyst material is difficult to change the reaction freedom of the adsorbed gas of gas sensing layer 110 Can, but the activation energy of the adsorbed gas of gas sensing layer 110 can be reduced, so as to accelerate the speed that gas absorption chemical reaction occurs. The catalyst material is noble metal or the transition metal such as Ag, Pt or Pd.
In the present embodiment, the material of the gas sensing layer 110 is the SnO for being added with Pt2.Using sol-gal process or sputtering method Form the gas sensing layer 110.
In the present embodiment, the gas sensing layer 110 is formed using magnetron sputtering method, specifically, using magnetron sputtering method first Formation material is SnO2Gas sensing layer 110, the technological parameter of magnetron sputtering method is：Sn targets are provided, sputter gas are Ar and O2, Wherein, Ar and O2Gas flow ratio be 2:1 to 5:1, sputtering chamber pressure be 1Pa to 5Pa, there is provided operating voltage be 500V to 1000V, there is provided RF source power be 100 watts to 200 watts, the temperature of substrate 100 is 20 degrees Celsius to 50 degrees Celsius.
The specific surface area of gas sensing layer 110 is bigger, and the sensitivity of the sensing gas of corresponding gas sensing layer 110 is higher.And use magnetic control It is SnO that sputtering method forms material2Gas sensing layer 110 when, gas sensing layer 110 have larger specific surface area.When sputtering chamber pressure For 3Pa to 4Pa, there is provided operating voltage be 620V to 710V, there is provided RF source power for 140 watts to 160 watt-hours, using magnetic Control sputtering is provided with energy very high during forming gas sensing layer 110 so that Sn atoms and O atom have enough energy Amount, so that Sn atoms and O atom carry out sufficient travel motion on the surface of the second top-level metallic interconnection layer 423, so that Obtain the surface distributed of gas sensing layer 110 uniform, make the SnO in gas sensing layer 1102Particle homogeneous nucleation, so that the gas sensing layer for being formed 110 have bigger specific surface area.
Also, in magnetron sputtering process, if partial pressure of oxygen is excessive in sputtering chamber, the oxygen of gas sensing layer 110 to be formed can be made Change excessively fully, the Lacking oxygen in gas sensing layer 110 is very few；If partial pressure of oxygen is too small in sputtering chamber, the material of gas sensing layer 110 for being formed The degree of oxidation of material is low.Oxidation excessively fully or degree of oxidation is low can cause sensitivity of the gas sensing layer 110 to gas low, is This, in one embodiment, Ar and O2Gas flow ratio be 3:1 to 4:1, so that the gas sensing layer 110 for being formed is oxidized Degree it is moderate, sensitivity of the gas sensing layer 110 to gas is larger.
Then, it is SnO in material to use magnetron sputtering method2The surface of gas sensing layer 110 formed Pt films；Then, using ashing Technique removes first photoresist layer 109.
Finally, the gas sensing layer 110 that Pt films are formed with to surface makes annealing treatment, and on the one hand the annealing can make Pt is diffused into gas sensing layer 110, on the other hand can also further improve the quality of the gas sensing layer 110 of formation.
The annealing temperature of the annealing is 200 degrees Celsius to 300 degrees Celsius, and such as annealing temperature can be taken the photograph for 240 Family name's degree, 260 degrees Celsius or 280 degrees Celsius.
With reference to Figure 12, the second photoresist layer 111 is formed on the surface of the passivation layer 108 and the surface of gas sensing layer 110, it is described Second photoresist layer 111 has the annular opening 112 above the II of sensor regions, and the annular opening 112 exposes air-sensitive The surface of passivation layer 108 around layer 110.
Because the annealing temperature for making annealing treatment is 200 degrees Celsius to 300 degrees Celsius, what is carried out under the annealing temperature moves back Fire treatment has no adverse effects to MOS device area I.
Second photoresist layer 111 is the substrate 100 of subsequent etching passivation layer 108, dielectric layer and segment thickness Mask, prepares to form hanging structure.
The size of the annular opening 112 is relevant with the area of insulation size being subsequently formed, if the size of annular opening 112 Excessive, then the volume shared by area of insulation being subsequently formed is larger, causes the chip area needed for forming CMOS gas sensors Greatly；If annular opening 112 is undersized, the small volume shared by area of insulation being subsequently formed causes polysilicon zone of heating 122 heats for producing easily are transferred to undesirable region, the response time delay of CMOS gas sensors.
Also, if annular opening 112 is undersized, the size of the groove being accordingly subsequently formed is also smaller, works as use During 100 sidewall surfaces of substrate that isotropic etching technique etching groove exposes, etching gas reach the side wall of substrate 100 The difficulty on surface increases.
Therefore, in the present embodiment, on parallel to the surface direction of substrate 100, the size of the annular opening 112 is 3 micro- Rice is to 5 microns.
With reference to Figure 13, with second photoresist layer 111 as mask, exposed along the annular opening 112 (referring to Figure 12) The passivation layer 108 for going out is performed etching, until the substrate 100 of etching removal segment thickness.
Specifically, using dry etch process, being sequentially etched the passivation layer 108, medium around the gas sensing layer 110 The substrate 100 of layer and segment thickness, in sensor regions, II forms the groove 113 around the gas sensing layer 110.
The dry etch process is and larger to the etch rate of dielectric layer to the etch rate very little of metal interconnecting layer. Because second metal interconnecting layer 402 of sensor regions II is across MOS device area I and sensor regions II, dry etch process is to passing The etch rate very little of second metal interconnecting layer 402 of sensor area II so that dry etch process will not be interconnected to the second metal The second dielectric layer 104 of the lower section of layer 402, the 3rd dielectric layer 103 and polysilicon zone of heating 122 cause etching, and follow-up each Only substrate 100 is performed etching to isotropic etch process, therefore the support arm of actually hanging structure is：At least by the second metal The laminated construction of interconnection layer 402, the composition of second dielectric layer 104, first medium layer 103, the support arm of hanging structure can also be wrapped Include polysilicon zone of heating 122.
The thickness of the substrate 100 of the use dry etch process etching removal and the size of the area of insulation being subsequently formed Relevant, if substrate 100 is etched, the thickness of removal is too small, undersized, the follow-up shape of the area of insulation being accordingly subsequently formed Into hanging structure it is too small with the distance between substrate 100, the heat in the polysilicon zone of heating 122 be difficult release；If lining Bottom 100 be etched removal thickness it is excessive, then the thickness very little of corresponding remaining substrate 100, easily causes polysilicon zone of heating 122 be stressed effect it is too strong, cause polysilicon zone of heating 122 occur serious deformation.If also, substrate 100 is etched removal Thickness it is excessive, then the substrate 100 of the corresponding follow-up sensor regions II when isotropic etching technique is carried out can be cut through.
Amid all these factors consider, substrate 100 be etched removal thickness for the original depth of substrate 100 1/30 to 1/3, For example, substrate 100 is etched, the thickness of removal can be the 1/10 or 1/5 of the original depth of substrate 100.
In the present embodiment, the thickness of substrate 100 for using dry etch process to etch removal is 5 microns to 10 microns, It for example can be 6 microns or 8 microns；It can also be expected that in the surface direction of substrate 100, the groove 113 exposes The side wall dimensions of substrate 100 be 5 microns to 10 microns.
In the present embodiment, the thickness of dielectric layer is 8 microns to 12 microns, and the dielectric layer is：First medium layer 103, position In the first medium layer second dielectric layer 104 on 103 surfaces, the 3rd dielectric layer 105 positioned at the surface of second dielectric layer 104, it is located at 4th dielectric layer 106 and the top layer dielectric layer 107 positioned at the surface of the 4th dielectric layer 106 on the surface of the 3rd dielectric layer 105； Parallel in the surface direction of substrate 100, the size of the groove 113 is 3 microns to 5 microns.
In the present embodiment, the sidewall surfaces of the groove 113 are perpendicular to the surface of substrate 100；In other embodiments, hanging down Directly in the surface direction of substrate 100, the section shape of the groove 113 can also be inverted trapezoidal so that the top dimension of groove 113 More than the bottom size of groove 113, so that the etching gas of follow-up isotropic etching technique are easier to enter groove 113 Bottom, so as to the sidewall surfaces of substrate 100 that are exposed to groove 113 are performed etching.
With reference to Figure 14, using isotropic etching technique, enter along the sidewall surfaces of substrate 100 that the groove 113 exposes Row etching, forms hanging structure above the II of sensor regions, has area of insulation 114 between the hanging structure and substrate 100.
The hanging structure includes：Polysilicon zone of heating 122, certain media layer, sensor-interconnect structure and gas sensing layer 110。
In specific to the present embodiment, the hanging structure includes：Second oxide layer 121, positioned at the surface of the second oxide layer 121 Polysilicon zone of heating 122, positioned at the surface of polysilicon zone of heating 122 first medium layer 103, positioned at first medium layer 103 in The first conductive plunger 301, positioned at the surface of the first conductive plunger 301 and part first medium layer 103 surface the first metal Interconnection layer 401, positioned at the surface of the first metal interconnecting layer 401 and first medium layer 103 surface second dielectric layer 104, be located at The second conductive plunger 302 in second dielectric layer 104, positioned at the surface of the second conductive plunger 302 and part second dielectric layer 104 Second metal interconnecting layer 402 on surface, the positioned at the surface of the second metal interconnecting layer 402 and the surface of second dielectric layer 104 the 3rd Dielectric layer 105, the 3rd conductive plunger 303 positioned at the surface of the 3rd dielectric layer 105, positioned at the surface of the 3rd conductive plunger 303 and 4th dielectric layer 106, the 4th conductive plunger 304, position in the 4th dielectric layer 106 on the surface of the 3rd dielectric layer of part 105 The second top-level metallic interconnection layer 423 in the surface of the 4th conductive plunger 304 and the surface of the 4th dielectric layer of part 106, positioned at The top layer dielectric layer 107 on the sidewall surfaces of two top-level metallic interconnection layer 423 and the surface of the 4th dielectric layer 106 and positioned at top layer The passivation layer 108 on the surface of dielectric layer 107.
The part or all of sidewall surfaces of the first metal interconnecting layer 401 in hanging structure are covered by dielectric layer, hanging knot The part or all of sidewall surfaces of the second metal interconnecting layer 402 in structure are covered by dielectric layer, the 3rd metal in hanging structure The part or all of sidewall surfaces of interconnection layer 403 are covered by dielectric layer, so that it is mutual to reduce the first metal interconnecting layer 401, the second metal The probability that even metal interconnecting layer 403 of layer 402 and the 3rd is oxidized or corrodes.In other embodiments, in hanging structure The sidewall surfaces of two top-level metallic interconnection layer 423 can also be covered by dielectric layer.
In the present embodiment, using XeF2The isotropic etching technique is carried out, due to XeF2It is dry etching, and XeF2 Etching technics can avoid the problem of ion dam age that Ions Bombardment is brought and charge accumulated chemically to etch.Also, XeF2Only substrate 100 is performed etching, and it is very small to the etch rate of dielectric layer, metal interconnecting layer or even can ignore not Count, therefore the isotropic etching technique has no adverse effects to MOS device area I, therefore hanging structure is formed in the present embodiment Technique it is completely compatible with standard CMOS process.
On parallel to the surface direction of substrate 100, the size of the area of insulation 114 is 10 microns to 50 microns, for example It is 15 microns, 20 microns, 25 microns or 35 microns.
In a specific embodiment, using XeF2The technological parameter for carrying out isotropic etching technique is：Circulation is carried out To being passed through XeF in etching cavity2With extraction XeF2Action, XeF in etching cavity2Pressure is 100Pa to 180Pa, and to etching XeF is passed through in chamber2Maintain 10 seconds to 50 seconds afterwards, cycle-index is 5 to 15 times.
For example, XeF in etching cavity2Pressure can be 120Pa, 140Pa or 150Pa, to being passed through XeF in etching cavity2Afterwards Maintain 15 seconds, 20 seconds or 30 seconds.
Due to XeF2It is isotropic etching technique, therefore during etching forms hanging structure, it is described each to same Property etching technics both can be immediately below etches polycrystalline silicon zone of heating 122 substrate 100, can also etch the substrate positioned at device region I 100。
In the present embodiment, the second metal interconnecting layer 402 in sensor-interconnect structure is the support arm of hanging structure, due to Second dielectric layer 104, the first medium layer 103 of the lower section of second metal interconnecting layer 402 will not be etched, therefore support arm It is actually the laminated construction of the second metal interconnecting layer 402, second dielectric layer 104 and first medium layer 103, the lamination knot Structure can also include the first metal interconnecting layer 401 or polysilicon zone of heating 122.In other embodiments, sensor-interconnect structure In the first metal interconnecting layer 402, the 3rd metal interconnecting layer 403 or the second top-level metallic interconnection layer 423 in one layer or many Layer can be as the support arm of hanging structure.
With reference to Figure 15, second photoresist layer 111 (referring to Figure 14) is removed.
Using cineration technics, second photoresist layer 111 is removed.
It is follow-up also to include being packaged technique.
Accordingly, Figure 15 is refer to, the present invention also provides a kind of CMOS gas sensors, including：
Substrate 100, the substrate 100 includes MOS device area I and sensor regions II；
Positioned at the polysilicon gate 112 on the MOS device area I section substrates surface；
Positioned at the polysilicon zone of heating 122 on the surface of sensor regions II section substrates 100；
Dielectric layer on the MOS device area I and sensor regions II substrate 100, and the dielectric layer is covered in The surface of polysilicon gate 112 and the surface of polysilicon zone of heating 122；
MOS device interconnection structure and sensor-interconnect structure in the dielectric layer；
Wherein, the MOS device interconnection structure is located at MOS device area I tops, the MOS device interconnection structure and polycrystalline Si-gate 112 is electrically connected, the MOS device interconnection structure at least include 2 layers of metal interconnecting layer, and the MOS device area I metal Interconnection layer includes the first top-level metallic interconnection layer 413, and the top of the first top-level metallic interconnection layer 413 is neat with dielectric layer top It is flat；
The sensor-interconnect structure is located at sensor regions II tops, the sensor-interconnect structure and polysilicon zone of heating 122 electrical connections, the sensor-interconnect structure at least includes 2 layers of metal interconnecting layer, and the metal interconnecting layer of sensor regions includes At least 1 layer metal interconnecting layer is also located at MOS device in second top-level metallic interconnection layer 423, and the sensor-interconnect structure Area I tops, the top of the second top-level metallic interconnection layer 423 flushes with dielectric layer top；
Positioned at the passivation layer on the dielectric layer surface and the surface of the first top-level metallic interconnection layer 413；
Positioned at the gas sensing layer 110 on the surface of the second top-level metallic interconnection layer 423；
Around the gas sensing layer 110 and the groove 113 above the II of sensor regions, the groove 113 runs through sensor Passivation layer 108 and dielectric layer above area II, and the groove 113 exposes the surface of section substrate 100 of sensor regions II；
By the circular hanging structure of the groove 113, have between the hanging structure and the substrate 100 of sensor regions II Area of insulation 114, and the hanging structure bottom flushes with dielectric layer bottom.
In the present embodiment, the dielectric layer includes：Positioned at the of the surface of substrate 100 of MOS device area I and sensor regions II One dielectric layer 103, second dielectric layer 104, the positioned at the surface of second dielectric layer 104 the 3rd positioned at 103 surface of first medium layer Dielectric layer 105, the 4th dielectric layer 106 positioned at the surface of the 3rd dielectric layer 105 and the top positioned at the surface of the 4th dielectric layer 106 Layer dielectric layer 107.
The MOS device interconnection structure includes 4 layers of metal interconnecting layer, and the MOS device interconnection structure includes：Positioned at MOS First metal interconnecting layer 401 on the surface of device region I first mediums floor 103, positioned at the surface of MOS device area I second dielectric layer 104 Second metal interconnecting layer 402, the 3rd metal interconnecting layer 403 positioned at the surface of the 3rd dielectric layers of MOS device area I 105, positioned at MOS The first top-level metallic interconnection layer 413 on the surface of the 4th dielectric layers of device region I 106.
The MOS device interconnection structure also includes：The first conductive plunger 301 in first medium layer 103, described the One conductive plunger 301 is electrically connected with the metal interconnecting layer 401 of polysilicon gate 112 and first；In second dielectric layer 104 Two conductive plungers 302, second conductive plunger 302 is electrically connected with the first metal interconnecting layer 401 and the second metal interconnecting layer 402 Connect；The 3rd conductive plunger 303 in the 3rd dielectric layer 105, the 3rd conductive plunger 303 and the second metal interconnecting layer 402 and the 3rd metal interconnecting layer 403 electrically connect, and between the 3rd metal interconnecting layer 403 and polysilicon zone of heating 122 electricity absolutely Edge；The 4th conductive plunger 304 in the 4th dielectric layer 106, the 4th conductive plunger 304 and the 3rd metal interconnecting layer 403 and first top-level metallic interconnection layer 413 electrically connect.
The sensor-interconnect structure includes 4 layers of metal interconnecting layer, and the sensor-interconnect structure includes：Positioned at sensor First metal interconnecting layer 401 on the surface of area II first mediums floor 103, positioned at the surface of sensor regions II second dielectric layer 104 Two metal interconnecting layers 402, the 3rd metal interconnecting layer 403 positioned at the surface of the 3rd dielectric layer of sensor regions II 105, positioned at sensor Second top-level metallic interconnection layer 423 of some mutually insulateds on the surface of the 4th dielectric layers of area II 106.
In the present embodiment, the second metal interconnecting layer 402 in sensor-interconnect structure is also located at the second of MOS device area I The surface of dielectric layer 104 so that the second metal interconnecting layer 402 prevents hanging structure from dropping as the support arm of hanging structure；It is actual On, support arm is the second metal interconnecting layer 402, second dielectric layer 104, the first metal interconnecting layer 401, first medium layer 103 Laminated construction, support arm can also include polysilicon zone of heating 122.There are some mutual electricity absolutely in the sensor-interconnect structure Second metal interconnecting layer 402 of edge, the second metal interconnecting layer 402 in the sensor-interconnect structure is also located at MOS device area I The surface of second dielectric layer 104, wherein, the second metal interconnecting layer of part 402 in sensor-interconnect structure is heated with polysilicon Layer 122 is electrically connected, another part the second metal interconnecting layer 402 and the second top-level metallic interconnection layer in sensor-interconnect structure 423 electrical connections.
The sensor-interconnect structure also includes：The first conductive plunger 301 in first medium layer 103, described the One conductive plunger 301 is electrically connected with the metal interconnecting layer 401 of polysilicon zone of heating 122 and first, and is heated with the polysilicon The electrically insulated from one another of first metal interconnecting layer 401 of the electrical connection of layer 122；The second conductive plunger in second dielectric layer 104 302, second conductive plunger 302 is electrically connected with the first metal interconnecting layer 401 and the second metal interconnecting layer of part 402；Position The 3rd conductive plunger 303 in the 3rd dielectric layer 105, the 3rd conductive plunger 303 and the second metal interconnecting layer of part 402 And the 3rd metal interconnecting layer 403 electrically connect；The 4th conductive plunger 304 in the 4th dielectric layer 106, the described 4th is conductive Connector 304 is electrically connected with the 3rd metal interconnecting layer 403 and the second top-level metallic interconnection layer 423.In other embodiments, MOS Device interconnected structure can also include 2 layers, 3 layers, 5 layers or 6 layers metal interconnecting layer, accordingly, the metal of sensor-interconnect structure The number of plies of interconnection layer is identical with the number of plies of MOS device interconnection structure.
Due to the electrically insulated from one another of the first metal interconnecting layer 401 electrically connected with polysilicon zone of heating 122, so that electric current After flowing into polysilicon zone of heating 122 via one first metal interconnecting layer 401, flowed out via another first metal interconnecting layer 401, from And cause that electric current flows through from polysilicon zone of heating 122, and then make to produce joule electric current in polysilicon zone of heating 122.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, are not departing from this In the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute The scope of restriction is defined.

Claims (7)

1. a kind of CMOS gas sensors, it is characterised in that including：
Substrate, the substrate includes MOS device area and sensor regions；
Positioned at the polysilicon gate on the MOS device area section substrate surface；
Positioned at the polysilicon zone of heating on the sensor regions section substrate surface；
Dielectric layer in the MOS device area and sensor regions substrate, and the dielectric layer is covered in polysilicon gate table Face and polysilicon heating layer surface；
MOS device interconnection structure and sensor-interconnect structure in the dielectric layer；
Wherein, the MOS device interconnection structure is located at MOS device area top, the MOS device interconnection structure and polysilicon gate electricity Connection, the MOS device interconnection structure at least includes being wrapped in 2 layers of metal interconnecting layer, and the metal interconnecting layer in the MOS device area The first top-level metallic interconnection layer is included, the first top-level metallic interconnection layer top flushes with dielectric layer top；
The sensor-interconnect structure is located at sensor regions top, and the sensor-interconnect structure is electrically connected with polysilicon zone of heating Connect, the sensor-interconnect structure at least includes 2 layers of metal interconnecting layer, the metal interconnecting layer of sensor regions includes the second top layer At least 1 floor metal interconnecting layer is also located at MOS device area top in metal interconnecting layer, and the sensor-interconnect structure, described Second top-level metallic interconnection layer top flushes with dielectric layer top；
Positioned at the dielectric layer surface and the passivation layer of the first top-level metallic interconnection layer surfaces；
Positioned at the gas sensing layer of the second top-level metallic interconnection layer surfaces；
Around the gas sensing layer and the groove above sensor regions, passivation layer of the groove above sensor regions with And dielectric layer, and the groove exposes the section substrate surface of sensor regions；
By the circular hanging structure of the groove, there is area of insulation between the hanging structure and the substrate of sensor regions, and The hanging structure bottom flushes with dielectric layer bottom.
2. CMOS gas sensors according to claim 1, it is characterised in that the dielectric layer includes：Positioned at MOS device The first medium floor of the substrate surface of area and sensor regions, the second dielectric layer positioned at first medium layer surface, it is situated between positioned at second 3rd dielectric layer of matter layer surface, the 4th dielectric layer positioned at the 3rd dielectric layer surface and positioned at the 4th dielectric layer surface Top layer dielectric layer.
3. CMOS gas sensors according to claim 2, it is characterised in that the MOS device interconnection structure includes 4 layers Metal interconnecting layer, the MOS device interconnection structure includes：The first metal positioned at MOS device area first medium layer surface is interconnected Floor, the second metal interconnecting layer positioned at MOS device area second medium layer surface, positioned at the dielectric layer surface of MOS device area the 3rd 3rd metal interconnecting layer, the first top-level metallic interconnection layer positioned at the dielectric layer surface of MOS device area the 4th.
4. CMOS gas sensors according to claim 3, it is characterised in that the MOS device interconnection structure also includes： The first conductive plunger in first medium layer, first conductive plunger and polysilicon gate and the first metal interconnecting layer electricity Connection；The second conductive plunger in second dielectric layer, second conductive plunger and the first metal interconnecting layer and second Metal interconnecting layer is electrically connected；The 3rd conductive plunger in the 3rd dielectric layer, the 3rd conductive plunger is mutual with the second metal Even layer and the electrical connection of the 3rd metal interconnecting layer；The 4th conductive plunger in the 4th dielectric layer, the 4th conductive plunger Electrically connected with the 3rd metal interconnecting layer and the first top-level metallic interconnection layer.
5. CMOS gas sensors according to claim 2, it is characterised in that the sensor-interconnect structure includes 4 layers Metal interconnecting layer, the sensor-interconnect structure includes：The first metal interconnecting layer positioned at sensor regions first medium layer surface, The second metal interconnecting layer positioned at sensor regions second medium layer surface, the 3rd gold medal positioned at the dielectric layer surface of sensor regions the 3rd Category interconnection layer, positioned at the dielectric layer surface of sensor regions the 4th some electrically insulated from one another the second top-level metallic interconnection layer.
6. CMOS gas sensors according to claim 5, it is characterised in that the sensor-interconnect structure also includes： The first conductive plunger in first medium layer, first conductive plunger is interconnected with polysilicon zone of heating and the first metal Layer electrical connection, and the first metal interconnecting layer electrically insulated from one another electrically connected with the polysilicon zone of heating；Positioned at second dielectric layer The second interior conductive plunger, second conductive plunger is electrically connected with the first metal interconnecting layer and the metal interconnecting layer of part second Connect；The 3rd conductive plunger in the 3rd dielectric layer, the 3rd conductive plunger and the metal interconnecting layer of part second and the Three metal interconnecting layers are electrically connected, and are electrically insulated between the 3rd metal interconnecting layer and polysilicon zone of heating；In the 4th dielectric layer The 4th conductive plunger, the 4th conductive plunger electrically connects with the 3rd metal interconnecting layer and the second top-level metallic interconnection layer.
7. CMOS gas sensors according to claim 5, it is characterised in that if having in the sensor-interconnect structure Second metal interconnecting layer of dry electrically insulated from one another, the second metal interconnecting layer in the sensor-interconnect structure is also located at MOS devices The second medium layer surface in part area, wherein, the metal interconnecting layer of part second and polysilicon zone of heating in sensor-interconnect structure Electrical connection, the metal interconnecting layer of another part second in sensor-interconnect structure is electrically connected with the second top-level metallic interconnection layer；Institute It is the support arm of hanging structure to state the second metal interconnecting layer in sensor-interconnect structure.
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