CN105428417B - The preparation method of autoregistration graphene/black phosphorus crystal pipe structure - Google Patents

The preparation method of autoregistration graphene/black phosphorus crystal pipe structure Download PDF

Info

Publication number
CN105428417B
CN105428417B CN201510821612.1A CN201510821612A CN105428417B CN 105428417 B CN105428417 B CN 105428417B CN 201510821612 A CN201510821612 A CN 201510821612A CN 105428417 B CN105428417 B CN 105428417B
Authority
CN
China
Prior art keywords
black phosphorus
graphene
substrate
gate
silica
Prior art date
Application number
CN201510821612.1A
Other languages
Chinese (zh)
Other versions
CN105428417A (en
Inventor
李平
王刚
张庆伟
陈远富
宋林财
Original Assignee
电子科技大学
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 电子科技大学 filed Critical 电子科技大学
Priority to CN201510821612.1A priority Critical patent/CN105428417B/en
Publication of CN105428417A publication Critical patent/CN105428417A/en
Application granted granted Critical
Publication of CN105428417B publication Critical patent/CN105428417B/en

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66969Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials

Abstract

The preparation method of autoregistration graphene/black phosphorus crystal pipe structure, is related to semiconductor technology.The present invention includes the following steps:A, silica separation layer is formed on substrate;B, silica slot is prepared on silica separation layer;C, gate material is filled in silica slot;D, make surface planarisation processing to substrate;E, thermal oxide is carried out to gate material, forms oxide thin layer silicon layer, using oxide thin layer silicon layer as insulation gate medium;F, metal layer is covered in substrate surface;G, surface planarisation processing is carried out to metal layer;H, source electrode and drain electrode is formed;I, gate electrode contact hole is formed;J, graphene film or black phosphorus film are formed on substrate, and graphical treatment is made to graphene film or black phosphorus film.The invention has the advantages that easily controllable, technical maturity, reproducible, the autoregistration of gate electrode and source-drain electrode can be readily realized.

Description

The preparation method of autoregistration graphene/black phosphorus crystal pipe structure

Technical field

The present invention relates to semiconductor technologies.

Background technology

Graphene/black phosphorus has caused the very big concern of researchers with its excellent performance since being found.Especially The characteristics of high mobility, becomes the critical material of radio-frequency devices.At present, University of California in Los Angeles is it has been reported that frequency Rate is the grapheme transistor of 427GHz.Grid and source and drain autoregistration are pursue graphene/black phosphorus crystal pipe radio-frequency performance one Important means, researchers propose a variety of self aligned methods.The present invention proposes a kind of to be realized with chemical-mechanical planarization Self aligned method.

Invention content

The technical problem to be solved by the invention is to provide a kind of preparations of autoregistration graphene/black phosphorus crystal pipe structure Method.

The present invention solve the technical problem the technical solution adopted is that, autoregistration graphene/black phosphorus crystal pipe structure Preparation method, which is characterized in that include the following steps:

A, silica separation layer is formed on substrate;

B, silica slot is prepared on silica separation layer;

C, gate material is filled in silica slot;

D, make surface planarisation processing to substrate;

E, thermal oxide is carried out to gate material, forms oxide thin layer silicon layer, be situated between using oxide thin layer silicon layer as insulated gate Matter;

F, metal layer is covered in substrate surface;

G, surface planarisation processing is carried out to metal layer, until insulation gate medium is exposed to surface;

H, make graphical treatment to remaining metal layer, form source electrode and drain electrode;

I, gate electrode contact hole is formed;

J, graphene film or black phosphorus film are formed on substrate, and graphical place is made to graphene film or black phosphorus film Reason makes patterned graphene film or black phosphorus film across gate electrode/gate medium and is electrically connected with source electrode and drain electrode realization It connects.

Gate material is the polysilicon or refractory metal silicon compound of doping.

The invention has the advantages that easily controllable, technical maturity, reproducible, can readily realize gate electrode with The autoregistration of source-drain electrode.

Below in conjunction with the drawings and specific embodiments, the present invention is further illustrated.

Description of the drawings

Fig. 1 is the schematic diagram of transistor arrangement that the present invention is prepared.

Fig. 2 to Figure 21 is the schematic diagram of each step, wherein,

Fig. 2 is the schematic diagram of graphene/black phosphorus crystal pipe silicon substrate and its surface isolation from oxygen SiClx;

Fig. 3 is the vertical view of graphene/black phosphorus crystal pipe silicon substrate and its surface isolation from oxygen SiClx;

Fig. 4 is the forming step schematic diagram of isolation from oxygen SiClx slot;

Fig. 5 is the vertical view of the formation of isolation from oxygen SiClx slot;

Fig. 6 is polygate electrodes filling step schematic diagram;

Fig. 7 is the vertical view of polygate electrodes filling;

Fig. 8 is polygate electrodes chemical-mechanical polishing step schematic diagram;

Fig. 9 is the vertical view of polygate electrodes chemically mechanical polishing;

Figure 10 is the forming step schematic diagram of graphene/black phosphorus crystal pipe gate medium silica;

Figure 11 is the vertical view of the formation of graphene/black phosphorus crystal pipe gate medium silica;

Figure 12 is the schematic diagram in device surface deposited metal material step;

Figure 13 is the vertical view of device surface deposited metal material;

Figure 14 is the chemical-mechanical polishing step schematic diagram of device surface deposited metal;

Figure 15 is the vertical view of the chemically mechanical polishing of device surface deposited metal;

Figure 16 is graphene/black phosphorus crystal pipe source-drain electrode patterning step schematic diagram;

Figure 17 is graphene/patterned vertical view of black phosphorus crystal pipe source-drain electrode;

Figure 18 is graphene/black phosphorus crystal pipe gate electrode contact hole etching step schematic diagram;

Figure 19 is the vertical view of graphene/black phosphorus crystal pipe gate electrode contact hole etching;

Figure 20 is the formation of graphene/black phosphorus and patterning step schematic diagram;

Figure 21 is the formation of graphene/black phosphorus and patterned vertical view.

Label declaration

1 substrate

2 isolation from oxygen SiClxs

3 gate electrodes

4 gate mediums

5 metals

501 source electrodes

502 drain electrodes

6 graphenes/black phosphorus

Specific embodiment

The present invention proposes a kind of implementation method of autoregistration graphene/black phosphorus crystal pipe structure, as shown in Figure 1.Graphite The gate electrode 3 of alkene/black phosphorus crystal pipe is polysilicon or refractory metal (titanium, molybdenum, cobalt etc.) silicide, and gate medium 4 is gate electrode table The silica membrane that face is formed.The gate electrode 3 and gate medium 4 of graphene/black phosphorus crystal pipe are located in a silica trench. In technical process, the position of device gate electrode 3 automatically with device source electrode 501 and the position alignment of drain electrode 502, so as to big The big overlap capacitance for reducing grid and source and drain, finally may be such that device frequency is greatly improved.

Fig. 2 to Figure 21 is cuing open in the forming process of novel Si-gate graphene/black phosphorus crystal pipe structure proposed by the present invention Face figure and vertical view.As shown in Figure 2 and Figure 3, thick 2 layers of an isolation from oxygen SiClx, 2 layers of the isolation from oxygen SiClx are formed on substrate 1 first It is main to play isolation.The substrate 1 used can be silicon substrate, including n-type silicon and p-type silicon or some other material Material, such as quartz glass, sapphire.The formation of isolation from oxygen SiClx 2 can be the side of the mode of thermal oxide or deposition Formula, such as chemical vapor deposition or physical vapour deposition (PVD).

After isolation from oxygen SiClx 2 is formed, silica is formed by using the method for wet etching or dry etching on it Slot, as shown in Figure 4, Figure 5.

Using the method for plasma enhanced chemical vapor deposition (PECVD) polycrystalline is filled into established silica slot Silicon gate electrode 3, as shown in Figure 6, Figure 7.The doping of polygate electrodes 3 can use mode in situ, can also be noted using ion The mode entered, doping type include N-shaped or p-type.

Surface planarisation is carried out to the polygate electrodes 3 in silica slot using methods such as chemically mechanical polishings (CMP), As shown in Figure 8, Figure 9.Then thermal oxide is carried out to the polygate electrodes 3 in silica slot, forms a thin layer silicon oxide layer, it should Gate medium 4 of the oxide thin layer silicon layer as graphene/black phosphorus crystal pipe, as shown in Figure 10, Figure 11.

Next one layer of metal 5 is formed in above-mentioned substrate surface using the deposition method such as evaporation or sputtering, such as Figure 12, Figure 13 It is shown.5 material of metal formed includes various metals type, such as titanium, nickel, gold, platinum, palladium.

Surface planarisation is carried out to above-mentioned metal 5 using methods such as chemically mechanical polishings (CMP), until insulation gate medium 4 Surface is exposed to, as shown in Figure 14, Figure 15.

Remaining metal 5 is patterned using methods such as chemical wet etchings, forms patterned source electrode 501 and electric leakage Pole 502, as shown in Figure 16, Figure 17.

3 contact hole of polygate electrodes is formed with the method for chemical wet etching, as shown in Figure 18, Figure 19.

Finally, 6 film of graphene/black phosphorus is formed in flatter substrate surface, and uses the methods such as plasma etching 6 film of graphene/black phosphorus is patterned, as shown in Figure 20, Figure 21.Due to 6 film of graphene/black phosphorus be formed in it is flatter Substrate surface, therefore the performance of 6 film of graphene/black phosphorus can be kept well.

The final result of above-mentioned realization process is to realize graphene/black phosphorus crystal pipe source electrode 501 and electric leakage well Pole 502 and the autoregistration of gate electrode 3.

Claims (3)

1. the preparation method of autoregistration graphene/black phosphorus crystal pipe structure, which is characterized in that include the following steps:
A, silica separation layer is formed on substrate;
B, silica slot is prepared on silica separation layer;
C, gate material is filled in silica slot;
D, make surface planarisation processing to substrate;
E, thermal oxide is carried out to gate material, forms oxide thin layer silicon layer, using oxide thin layer silicon layer as insulation gate medium;
F, metal layer is covered in substrate surface;
G, surface planarisation processing is carried out to metal layer, until insulation gate medium is exposed to surface;
H, make graphical treatment to remaining metal layer, form source electrode and drain electrode;
I, gate electrode contact hole is formed;
J, graphene film or black phosphorus film are formed on substrate, and graphical treatment is made to graphene film or black phosphorus film, Make patterned graphene film or black phosphorus film across gate electrode/gate medium and be electrically connected with source electrode and drain electrode realization.
2. the preparation method of autoregistration graphene as described in claim 1/black phosphorus crystal pipe structure, which is characterized in that grid electricity Pole material is the polysilicon or refractory metal silicon compound of doping.
3. the preparation method of autoregistration graphene as described in claim 1/black phosphorus crystal pipe structure, which is characterized in that described The material of substrate is silicon either quartz glass or sapphire.
CN201510821612.1A 2015-11-24 2015-11-24 The preparation method of autoregistration graphene/black phosphorus crystal pipe structure CN105428417B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510821612.1A CN105428417B (en) 2015-11-24 2015-11-24 The preparation method of autoregistration graphene/black phosphorus crystal pipe structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510821612.1A CN105428417B (en) 2015-11-24 2015-11-24 The preparation method of autoregistration graphene/black phosphorus crystal pipe structure

Publications (2)

Publication Number Publication Date
CN105428417A CN105428417A (en) 2016-03-23
CN105428417B true CN105428417B (en) 2018-07-03

Family

ID=55506483

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510821612.1A CN105428417B (en) 2015-11-24 2015-11-24 The preparation method of autoregistration graphene/black phosphorus crystal pipe structure

Country Status (1)

Country Link
CN (1) CN105428417B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107634099B (en) * 2017-08-11 2020-06-09 上海集成电路研发中心有限公司 Two-dimensional crystal material field effect transistor and preparation method thereof
CN107919400A (en) * 2017-10-09 2018-04-17 上海集成电路研发中心有限公司 A kind of InSe transistors and preparation method thereof
CN107785434A (en) * 2017-10-17 2018-03-09 江苏大学 A kind of preparation method of n-type black phosphorus field-effect transistor
CN108039373A (en) * 2017-11-24 2018-05-15 上海集成电路研发中心有限公司 Semiconductor devices and preparation method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102931057A (en) * 2012-11-16 2013-02-13 中国科学院上海微系统与信息技术研究所 Graphene field-effect device based on gate dielectric structure and manufacturing method for graphene field-effect device
CN103858344A (en) * 2011-06-23 2014-06-11 国际商业机器公司 Graphene or carbon nanotube devices with localized bottom gates and gate dielectric

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7858989B2 (en) * 2008-08-29 2010-12-28 Globalfoundries Inc. Device and process of forming device with device structure formed in trench and graphene layer formed thereover
US9076873B2 (en) * 2011-01-07 2015-07-07 International Business Machines Corporation Graphene devices with local dual gates

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103858344A (en) * 2011-06-23 2014-06-11 国际商业机器公司 Graphene or carbon nanotube devices with localized bottom gates and gate dielectric
CN102931057A (en) * 2012-11-16 2013-02-13 中国科学院上海微系统与信息技术研究所 Graphene field-effect device based on gate dielectric structure and manufacturing method for graphene field-effect device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Wafer scale fabrication of carbon nanotube FETs with embedded poly-gates;Han S J et al;《Electron Devices Meeting (IEDM), 2010 IEEE International》;20110128;全文 *

Also Published As

Publication number Publication date
CN105428417A (en) 2016-03-23

Similar Documents

Publication Publication Date Title
US9385237B2 (en) Source and drain doping profile control employing carbon-doped semiconductor material
CN104658912B (en) Semiconductor structure and forming method thereof
TWI545761B (en) Semiconductor devices and methods for manufacturing the same and pmos transistors
US9559119B2 (en) High voltage metal oxide semiconductor field effect transistor integrated into extremely thin semiconductor on insulator process
CN105470132B (en) The forming method of fin field effect pipe
KR101813176B1 (en) Graphene electronic device and method of fabricating the same
US8513068B2 (en) Nanowire field effect transistors
TWI511234B (en) Semiconductor structures and methods for forming isolation between fin structures of finfet devices
CN103843120B (en) There is the vertical transistor of asymmetric grid
US8680512B2 (en) Graphene transistor with a self-aligned gate
CN103325831B (en) For the source/drain profile of FinFET
US20140264590A1 (en) FinFET with Bottom SiGe Layer in Source/Drain
US7804130B1 (en) Self-aligned V-channel MOSFET
US9000499B2 (en) Gate-all-around carbon nanotube transistor with selectively doped spacers
US9478622B2 (en) Wrap-around contact for finFET
CN103403873B (en) offset electrode TFT structure
CN104992974B (en) Buddha's warrior attendant ground mass double hyer insulation gate medium field-effect transistor and preparation method thereof
CN103295904B (en) There is the FinFET design that LDD extends
CN100562988C (en) The manufacture method of soi device
US9660083B2 (en) LDMOS finFET device and method of manufacture using a trench confined epitaxial growth process
US9721970B2 (en) Gate all-around FinFET device and a method of manufacturing same
US7385258B2 (en) Transistors having v-shape source/drain metal contacts
DE102012221824A1 (en) Embedded stressors for multi-gate transistor units
US20150155353A1 (en) Borderless contact for ultra-thin body devices
US9337828B2 (en) Transistor including reentrant profile

Legal Events

Date Code Title Description
PB01 Publication
C06 Publication
SE01 Entry into force of request for substantive examination
C10 Entry into substantive examination
GR01 Patent grant
GR01 Patent grant