CN102403208B

CN102403208B - Preparation method for grid of RFLDMOS (radio frequency laterally diffused metal oxide semiconductor) device

Info

Publication number: CN102403208B
Application number: CN201010274275.6A
Authority: CN
Inventors: 王雷; 王海军
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2010-09-07
Filing date: 2010-09-07
Publication date: 2014-04-16
Anticipated expiration: 2030-09-07
Also published as: CN102403208A

Abstract

The invention discloses a preparation method for a grid of a RFLDMOS (radio frequency laterally diffused metal oxide semiconductor) device. A metal floating grid structure wrapping a grid and a drain is further prepared during preparation of a low-resistance metal grid, and is capable of effectively shielding high-frequency signals.

Description

The preparation method of grid in RFLDMOS device

Technical field

The present invention relates to the preparation method of grid in a kind of RFLDMOS device.

Background technology

Semiconductor device based on polysilicon gate is the semiconductor device of current main flow, is extensively manufactured and applies.But due to material itself, because silicon materials itself are a kind of semi-conducting material non-conductive material, its resistivity is higher.Although can adopt the method for doping to reduce its resistivity, there is its limit, typically adopt dopant implant technique can only reach bulk concentration 10 ²¹～10 ²²atom/cm3 (every cubic centimetre, individual atom), its resistivity approximately 40～100 ohm/cm.Therefore for high speed device, its resistivity has restricted the lifting of speed and frequency greatly.In order to reduce the resistivity of device grids, conventional method is to make polysilicon form metal silicide, and conventional metal silicide is SiW.But the resistivity of typical SiW is 5～20 ohm/cm, although resistivity value decreases, but cannot meet at a high speed or the demand of high frequency.Therefore conventionally for such devices, do not adopt Si to do, but with SiGe (germanium silicon), the special material of InP or metal gate device is done.But this type of process materials is special, and technology difficulty is large, production cost and selling price are all far longer than the common semiconductor device based on silicon conventionally.

For the common device based on silicon, using SiW is the technique of relatively commonly using as metal silicide, and its preparation technology's flow process is:

1) deposit spathic silicon, deposits tungsten (W) on polysilicon then, heating anneal forms SiW;

2) etch polysilicon and SiW form grid;

3) light dope injects the lightly-doped source drain region (Low DopingSource/Drain injects, and is called for short LDD and injects) that forms source region and drain region); Wherein not necessarily, in large-size technique, LDD injects does not need this step.

4) form grid curb wall;

5) be then the injection formation (Source/Drain injection) of autoregistration source-drain area;

6) deposition interlayer dielectric;

7) contact hole forms and follow-up subsequent interconnection technique.

In this traditional preparation method, because before device forms, metal is introduced into.And the introducing of metal ion can be polluted semiconductor equipment, make whole cavity be infected with metal ion, metal ion is a kind of very active doping ion simultaneously, once enter in normal device, can greatly change the performance of device.Therefore for the technique that contains metal, all adopt special installation to produce specially.And in existing semiconductor technology, conventional metal is W, Cu, Al, the most equipment of therefore general semiconductor factory is all to carry out line configuration for above several metals.Therefore for traditional semiconductor factory, generally can only carry out the metal silicide production of SiW.

In order further to reduce resistivity, use Ti, Co or Ni resistance rate can be reduced to below 1 ohm/cm.But for general semiconductor factory and traditional handicraft, because line configuration reason may adopt these metals to produce hardly, its output is also extremely restricted.Therefore most factories polysilicon resistance all can not be accomplished very little level, and therefore the high-speed high frequency device based on silicon is difficult to scale of mass production.

When RFLDMOS is operated in high frequency, high-frequency current on grid is collected in drain electrode, and in this process, because very high frequency, so its electromagnetic field can cause current loss to radiation in environment, and the amplitude of loss raises with frequency, and this effect can restrict frequency applications equally.

Summary of the invention

The technical problem to be solved in the present invention is to provide the preparation method of grid in a kind of RFLDMOS device, and employing the method is prepared low resistive metal grid and had the RF LDMOS device of the metal floating gate structure in parcel grid and drain region.

For solving the problems of the technologies described above, the preparation method of grid in RFLDMOS device of the present invention, after on silicon chip, preparation forms source region, drain region and polysilicon gate, comprises the steps:

1) on silicon chip, deposit insulating medium layer as hard mask layer;

2) on silicon chip, fill afterwards photoresist or organic filler material and form packed layer;

3) remove the packed layer of grid top, expose the hard mask layer on polysilicon gate;

4) dry etching is removed the hard mask layer on polysilicon gate, removes afterwards remaining packed layer;

5) deposit and silicon form the metal level of alloy;

6) adopt annealing in process, make the metal of metal level and polysilicon form silicon alloy;

7) remove unreacted metal level;

8) on silicon chip, deposit successively the second insulating medium layer and the second metal level;

9) photoetching and etching the second metal level, the metal floating boom in formation cover part polysilicon gate and drain region.

In preparation method of the present invention, the step that utilizes grid itself highly to form, deielectric-coating by deposit conformal is as hard mask layer, then fill photoresist or the organic filler material with mobility, be formed on packed layer that lower source-drain area is thicker and the higher thinner packed layer in gate regions, then utilize the phase same rate of filler to remove technique, thereby leave over and be partially filled layer at source-drain area, then utilize packed layer different from the etch rate of hard mask layer, when removing, hard mask layer protects the hard mask layer of source-drain area, in the alloying technology of silicon, utilize subsequently the self aligned silicon alloy that forms in gate regions of hard mask layer of the protection source-drain area of leaving over, simultaneously because hard mask layer very thin thickness, in forming, follow-up metal floating boom can be used as a part for insulating barrier, formation has the metal floating boom compared with thin dielectric layer.Preparation method of the present invention, low resistance gate (metal gate) and metal floating gate structure is simultaneously integrated, the loss of signal while reducing high-frequency work, the operating frequency of raising RFLDMOS device.

Accompanying drawing explanation

Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:

Fig. 1 is preparation method's flow chart of grid in RFLDMOS device of the present invention;

Fig. 2 to Figure 11 is and the corresponding structural representation of preparation flow of the present invention.

Embodiment

The preparation method of grid in RFLDMOS device of the present invention, on silicon chip 1, preparation forms source region 3, drain region 2 and polysilicon gate 5 (4 is grid oxygen) and afterwards, comprises the steps (seeing Fig. 1):

1) on silicon chip, deposit insulating medium layer 7 as hard mask layer (seeing Fig. 3);

2) on silicon chip, fill afterwards photoresist or organic filler material and form packed layer 9 (seeing Fig. 4);

3) remove the packed layer of grid top, expose the hard mask layer (seeing Fig. 5) on polysilicon gate;

4) dry etching is removed the hard mask layer (seeing Fig. 6) on polysilicon gate, removes afterwards remaining packed layer;

5) deposit and silicon form the metal level 10 (seeing Fig. 7) of alloy;

6) adopt annealing in process, make the metal of metal level and polysilicon form silicon alloy 6 (seeing Fig. 8);

7) remove unreacted metal level 10 (seeing Fig. 9);

8) on silicon chip, deposit successively the second insulating medium layer and the second metal level 8 (see Figure 10, in figure, the second insulating medium layer is identical with the insulating medium layer in step 1);

9) photoetching and etching the second metal level, the metal floating boom (seeing Figure 11) in formation cover part polysilicon gate and drain region.

Then the insulating medium layer (seeing Fig. 2) of removing through hole area on source region and drain region, carries out follow-up metal connecting line technique.

Insulating medium layer in above-mentioned steps one can be SiO ₂or SIN or other Si, N, O, the compound of C etc., its thickness is 200～5000 dusts, can pass through CVD, the methods such as PVD are carried out deposit.When the packing material in step 2 is photoresist, step 3 can and be developed with non-abundant exposure and be removed the photoresist of grid top.Exposure light source during now photoetching can be I-line, KrF or ArF etc.Photoresist thickness T now, the developing powder DR that exposure energy E is corresponding and developing time t; Etching selection ratio A in step 4, etching thickness of dielectric layers t, and must meeting between over etching amount OE: T-DR*t > A*t* (1+OE), ensures residual thickness of dielectric layers > 200 dusts in source region.Packing material in step 2 is that organic antireflecting material or organic filler material are, can return to carve with dry etching and remove in step 3.Now guarantee the residual packing thickness G reatT.GreaT.GT A*t* (1+OE) in step 3.Metal level in step 5 can be W, Ti, and Co or Ni etc. can form with Si the material of alloy, and the thickness of metal level is 100～2000 dusts, can adopt sputter or depositional mode to produce.Annealing time in step 6 and temperature be industry know altogether can form W, Ti, time and the temperature of the Si alloys such as Co or Ni.The technique of the unreacted metal level of removal in step 7 be industry know altogether can remove W, Ti, the wet-etching technology that Co or Ni etc. are corresponding.The second insulating medium layer in step 8 is SiO ₂or SiN or other Si, N, O, the compound of C etc., can be consistent with the dielectric layer material in step 2 or inconsistent all can, its thickness is 200～5000 dusts.Metal level can be Al, Cu, and the alloy of Ag or other Si and metal, its thickness is 500～5000 dusts.Finally can directly by chemical wet etching, remove the dielectric layer of through hole area, or direct etching is removed in follow-up via layer etching.

The prepared low resistive metal grid of preparation method of the present invention is in conjunction with the metal floating gate structure of parcel grid and drain electrode, and it can shield high-frequency signal effectively.But simultaneously in order to prevent the short circuit of grid and drain electrode, conventionally needing between the two has dielectric to intercept.

Claims

1. a preparation method for grid in RF LDMOS device, is characterized in that, after on silicon chip, preparation forms source region, drain region and polysilicon gate, comprises the steps:

1) on silicon chip, deposit insulating medium layer as hard mask layer;

4) dry etching is removed the hard mask layer on described polysilicon gate, removes afterwards remaining packed layer;

5) deposit and silicon form the metal level of alloy;

7) remove unreacted metal level;

9) the second metal level described in photoetching and etching, forms the metal floating boom of polysilicon gate and described drain region described in cover part.

2. according to preparation method claimed in claim 1, it is characterized in that: the second insulating medium layer in step 1 insulating medium layer and step 8 is same medium, is silicon dioxide or silicon nitride, and the thickness of the insulating medium layer in described step 1 is 200～5000 dusts.

3. according to preparation method claimed in claim 1, it is characterized in that: in step 5, the metal of deposit is tungsten, titanium, cobalt or nickel, the thickness of described metal level is 100～2000 dusts.

4. according to preparation method claimed in claim 1, it is characterized in that: in step 9, the second metal level is aluminium lamination, copper layer or silver layer, and the thickness of described the second metal level is 500～5000 dusts.

5. according to preparation method claimed in claim 1, it is characterized in that: described organic filler material is organic antireflecting material.