US20180261461A1 - Salicide formation using a cap layer - Google Patents
Salicide formation using a cap layer Download PDFInfo
- Publication number
- US20180261461A1 US20180261461A1 US15/981,665 US201815981665A US2018261461A1 US 20180261461 A1 US20180261461 A1 US 20180261461A1 US 201815981665 A US201815981665 A US 201815981665A US 2018261461 A1 US2018261461 A1 US 2018261461A1
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- US
- United States
- Prior art keywords
- semiconductor device
- salicide layer
- feature
- gate
- gate stack
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 230000015572 biosynthetic process Effects 0.000 title description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 66
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 17
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 24
- 239000010703 silicon Substances 0.000 claims description 24
- 125000006850 spacer group Chemical group 0.000 claims description 14
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 5
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 5
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 2
- 229910017052 cobalt Inorganic materials 0.000 claims description 2
- 239000010941 cobalt Substances 0.000 claims description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 2
- 229910052735 hafnium Inorganic materials 0.000 claims description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 239000010936 titanium Substances 0.000 claims description 2
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 claims description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 claims 1
- 238000000034 method Methods 0.000 description 55
- 229910052751 metal Inorganic materials 0.000 description 38
- 239000002184 metal Substances 0.000 description 38
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 29
- 238000000137 annealing Methods 0.000 description 21
- 229920002120 photoresistant polymer Polymers 0.000 description 16
- 238000000151 deposition Methods 0.000 description 13
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- 238000010586 diagram Methods 0.000 description 10
- 238000006243 chemical reaction Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
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- 229910021332 silicide Inorganic materials 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 229910005883 NiSi Inorganic materials 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910005487 Ni2Si Inorganic materials 0.000 description 1
- 229910012990 NiSi2 Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- IJKVHSBPTUYDLN-UHFFFAOYSA-N dihydroxy(oxo)silane Chemical compound O[Si](O)=O IJKVHSBPTUYDLN-UHFFFAOYSA-N 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000001017 electron-beam sputter deposition Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
- -1 polysilicon Chemical compound 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000009827 uniform distribution Methods 0.000 description 1
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Definitions
- Salicides are self-aligned silicides.
- Self-aligned refers to a manufacturing technique where a gate electrode region of a transistor is used as a mask for doping the source and drain.
- Some techniques for forming salicides over source and drain features include depositing a metal layer over a surface of a semiconductor assembly including the source and drain features. The assembly is then annealed to form a salicide in a reaction between silicon atoms in the source and drain features and metal atoms in the metal layer. The unreacted metal is then removed using an etching process.
- the reaction to form salicide consumes silicon atoms in the source and drain features. If the source and drain features have an insufficient amount of silicon at a surface interface with the metal layer, in some instances, the salicide is also etched through during the etching process to remove unreacted metal. Etching through the salicide creates openings that can form short circuits when metal contacts are deposited on the source and drain features. Additionally, in situations where silicon atoms are unevenly concentrated in the source and drain features, voids can form in the salicide and cause the semiconductor device to malfunction.
- FIG. 1 is a side view diagram of a semiconductor device including cap layers, according to one ore more embodiments.
- FIG. 2 is a flowchart of a method of forming a salicide layer in a semiconductor device including cap layers, according to one or more embodiment.
- FIGS. 3A-3G are side view diagrams of a semiconductor device during various stages of the method of FIG. 2 .
- FIG. 1 is a side view diagram of a semiconductor device 100 according to an embodiment.
- Semiconductor device 100 includes a substrate 102 having source and drain features 104 in substrate 102 .
- Semiconductor device 100 includes a gate stack 106 and optional spacers 108 over substrate 102 .
- Semiconductor device 100 further includes cap layers 110 over at least a portion of source and drain features 104 .
- substrate 102 is silicon. In some embodiments, substrate 102 is silicon germanium, gallium arsenide, germanium or other suitable semiconductor material. In some embodiments, substrate 102 is a semiconductor on insulator such as silicon on insulator
- Source and drain features 104 are areas of higher charge mobility within substrate 102 . In some embodiments, source and drain features 104 have higher hole mobility than substrate 102 . In some embodiments, source and drain features 104 have higher electron mobility than substrate 102 . In some embodiments, source and drain features 104 are doped with p-type dopants, such as boron or BF 2 ; or n-type dopants, such as phosphorous or arsenic. In some embodiments, source and drain features 104 comprise silicon germanium. In some embodiments, source and drain features 104 are substantially silicon free.
- Gate stack 106 includes a gate electrode 106 a over an optional a gate dielectric 106 b .
- gate electrode 106 a comprises polysilicon.
- gate electrode 106 a comprises molybdenum, aluminum, copper or other suitable conductive material.
- optional gate dielectric 106 b comprises silicon dioxide.
- optional gate dielectric 106 b comprises a high k dielectric, such as hafnium silicate, zirconium silicate, hafnium dioxide, zirconium dioxide, or other suitable dielectric material.
- source and drain features 104 and gate stack 106 collectively form a transistor. In some embodiments, where source and drain features 104 are selected to enhance hole mobility, source and drain features 104 and gate stack 106 collectively form a p-type metal oxide semiconductor (PMOS) transistor. In some embodiments, where source and drain features 104 are selected to enhance electron mobility, source and drain features 104 and gate stack 106 collectively form an n-type metal oxide semiconductor (NMOS) transistor.
- PMOS metal oxide semiconductor
- NMOS n-type metal oxide semiconductor
- semiconductor device 100 optionally includes spacers 108 along sidewalls of gate stack 106 .
- spacers 108 comprise silicon dioxide, silicon nitride, silicon oxynitride or other suitable material. In some embodiments, spacers 108 comprise non-conductive material.
- Cap layers 110 are over source and drain features 104 extending beyond gate stack 106 and optional spacers 108 . In at least some embodiments, cap layers 110 extend over substantially all of source and drain features 104 extending beyond gate stack 106 and optional spacers 108 . Cap layers 110 comprise silicon. In some embodiments, cap layers 110 have a thickness ranging from about 5 Angstroms to about 10 Angstroms. This range, in some embodiments, is narrower, e.g., from 5 Angstroms to 10 Angstroms.
- cap layers 110 provide sufficient silicon atoms to form the salicide layer over source and drain features 104 to a thickness sufficient to avoid etching through the salicide layer. The inclusion of cap layers 110 in semiconductor device 100 , thus acts to increase the yield of a production process by reducing the number of semiconductor devices that are defective due to short circuits.
- Cap layers 110 also provide substantially uniform silicon concentration over source and drain features 104 . In some instances where the salicide layer is formed with variations in silicon concentration, voids form in the salicide layer thereby increasing resistance to current flow. Increased resistance causes semiconductor device 100 to perform below acceptable standards. Cap layers 110 avoid the formation of voids in the salicide through the substantially uniform distribution of silicon, thereby increasing production yield.
- FIG. 2 is a process flow diagram of a method 200 of forming a semiconductor device 300 , according to one or more embodiments.
- Method 200 begins with forming source and drain features 104 in substrate 102 , gate stack 106 and optionally spacers 108 over substrate 102 in operation 202 .
- source and drain features 104 are formed by ion implantation, including tilted ion implantation.
- source and drain features 104 are formed by doping, annealing or other suitable processes.
- Gate stack 106 and optional spacers 108 are formed using methods known in the art including gate last processes.
- FIG. 3A is a side view diagram of semiconductor device 300 following formation of source and drain features 104 , gate stack 106 and optionally spacers 108 .
- Method 200 continues with optional operation 204 , in which a photoresist layer 112 ( FIG. 3B ) is deposited over substrate 102 .
- outer boundaries of source and drain features 104 are defined by isolation features, another gate stack, or other features over substrate 102 of semiconductor device 300 . If the outer boundaries of source and drain features 104 are defined by another feature, photoresist layer 112 is eliminated, according to some embodiments.
- spin-on deposition, physical vapor deposition, or other suitable deposition process deposits photoresist layer 112 over substrate 102 .
- Method 200 continues with optional operation 206 , in which photoresist layer 112 is patterned and etched.
- operation 206 is likewise omitted.
- ultraviolet light passing through a mask patterns photoresist layer 112 .
- thermal energy or other suitable patterning processes are used to pattern photoresist layer 112 .
- patterned photoresist layer 112 is etched using a wet etching process.
- the etching process is a dry etching process, a plasma etching process, a reactive ion etching process, or other suitable etching process.
- FIG. 3C is a side view diagram of semiconductor device 300 following patterning and etching of photoresist layer 112 .
- cap layers 110 are deposited over source and drain features 104 .
- cap layers 110 are deposited using an epitaxial growth process.
- cap layers 110 are deposited by sputtering, atomic layer deposition, or other suitable deposition processes. In some embodiments, deposition continues until cap layers 110 have a thickness ranging from about 5 Angstroms to about 10 Angstroms.
- FIG. 3D is a side view diagram of semiconductor device 300 following deposition of cap layers 110 .
- photoresist layer 112 is removed. In some embodiments, photoresist layer 112 is removed using plasma ashing. In some embodiments, photoresist layer 112 is removed using etching or other suitable removal processes.
- a metal layer 114 ( FIG. 3E ) is deposited over substrate 102 .
- metal layer 114 is deposited using physical vapor deposition.
- metal layer 114 is deposited using chemical vapor deposition, atomic layer deposition, electron beam evaporation, sputtering, or other suitable deposition process.
- metal layer 114 comprises nickel, cobalt, titanium, platinum, or other suitable metal material.
- the deposition process continues until metal layer 114 has a thickness ranging from about 200 Angstroms to about 400 Angstroms. This range, in some embodiments, is narrower, e.g., from 200 Angstroms to 400 Angstroms.
- FIG. 3E is a side view diagram of semiconductor device 300 following deposition of metal layer 114 .
- Method 200 continues with operation 212 , in which semiconductor device 300 is heated during an annealing process.
- the annealing process causes metal atoms in metal layer 114 to react with silicon atoms in cap layers 110 and in source and drain features 104 to create the salicide layer.
- semiconductor device 300 is heated to a temperature ranging from about 200 C to about 800 C. This range, in some embodiments, is narrower, e.g., from 200 C to 800 C.
- the annealing process continues for a duration ranging from about 1 minute to about 10 minutes.
- the annealing process tunes the resistivity of the salicide layer. Generally, the higher the annealing temperature and the longer the annealing duration, the lower the resistivity of the resulting salicide layer because of the formation of larger grains in the salicide layer. If the metal of metal layer 114 and the silicon of cap layers 110 react to form different compounds, tailoring the annealing process allows selective formation of a desired salicide compound. For example, when the metal of metal layer 114 is nickel, the desired salicide compound is NiSi, instead of materials with a higher resistivity such as Ni 2 Si or NiSi 2 . In order to obtain the highest concentration of NiSi in the salicide layer, the annealing process takes place at a temperature of about 200 C to about 500 C for a duration of about one minute.
- FIG. 3F is a side view diagram of semiconductor device 300 following the annealing process.
- the annealing process causes metal layer 114 to react with silicon to form salicide layer 116 .
- salicide layer 116 has a thickness ranging from about 120 Angstroms to about 300 Angstroms. This range, in some embodiments, is narrower, e.g., from 120 Angstroms to 300 Angstroms.
- gate electrode 106 a contains silicon, e.g., polysilicon, and the annealing process causes metal layer 114 to react with silicon atoms of gate electrode 106 a to form a salicide layer over gate stack 106 as well as over source and drain features 104 .
- FIG. 3G is a side view diagram of semiconductor device 300 following removal of the unreacted metal.
- cap layers 110 helps to form salicide layers 116 with sufficient thickness, to prevent the process removing metal layer 114 in operation 214 from also exposing source and drain features 104 through portions of salicide layers 116 .
- the inclusion of cap layers 110 also aids in forming salicide layers 116 having reduced amounts of germanium within the salicide layers.
- a germanium concentration within salicide layers 116 is less than about 3% by weight. Using conventional techniques which do not include cap layers 110 , a germanium concentration within conventional salicide layers ranges from about 13% by weight to about 17% by weight.
- cap layers 110 are connected to salicide layers 116 and electrically connected to an interconnect structure to incorporate semiconductor device 300 into a circuit. Including cap layers 110 in the formation of semiconductor device 300 increases production yield over formation processes in which cap layers 110 are omitted.
- the method includes forming a source feature and a drain feature in a substrate.
- the method further includes forming a gate stack over a first portion of the source feature and a first portion of the drain feature, the gate stack comprising a gate electrode.
- the method further includes depositing a first cap layer comprising silicon over a second portion of the source feature exposed by the gate stack.
- the method further includes depositing a second cap layer comprising silicon over a second portion of the drain feature exposed by the gate stack.
- the method further includes depositing a metal layer over the gate stack, the first cap layer and the second cap layer.
- the method further includes annealing the semiconductor device until all of the silicon in the first cap layer and the second cap layer reacts with metal from the metal layer, wherein the annealing causes metal from the metal layer to react with silicon in the first cap layer, the second cap layer, the source feature, and the drain feature while leaving at least a portion of the gate electrode free of silicide.
- Annealing the semiconductor device includes annealing the semiconductor device at a temperature ranging from 450° C. to 800° C. to form a salicide layer having a germanium concentration less than 3% by weight.
- the method includes forming a source feature and a drain feature in a substrate.
- the method further includes forming a gate stack over a first portion of the source feature and a first portion of the drain feature, the gate stack comprising a gate electrode.
- the method further includes depositing, patterning, and etching a photoresist layer over the substrate.
- the method further includes depositing a first cap layer comprising silicon over a second portion of the source feature exposed by the gate stack and the photoresist layer.
- the method further includes depositing a second cap layer comprising silicon over a second portion of the drain feature exposed by the gate stack and the photoresist layer.
- the method further includes removing the photoresist layer.
- the method further includes depositing a metal layer over the gate stack, the first cap layer and the second cap layer.
- the method further includes annealing the semiconductor device until all of the silicon in the first cap layer and the second cap layer is consumed by a silicidation reaction, wherein the annealing causes metal from the metal layer to react with silicon in the first cap layer, the second cap layer, the source feature, and the drain feature while leaving at least a portion of the gate electrode free of silicide.
- Annealing the semiconductor device includes annealing the semiconductor device at a temperature ranging from 450° C. to 800° C. to form a silicide layer having a germanium concentration less than 3% by weight.
- the semiconductor device includes a substrate having a source feature and a drain feature therein configured to enhance charge mobility.
- the semiconductor device further includes a gate stack over a portion of the source feature and a portion of the drain feature.
- the semiconductor device further includes a first salicide layer over substantially the entire source feature not covered by the gate stack, wherein the first salicide layer has a germanium concentration less than about 3% by weight.
- the semiconductor device further includes a second salicide layer over substantially the entire drain feature not covered by the gate stack, wherein the second salicide layer has a germanium concentration less than about 3% by weight.
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Abstract
Description
- The present application is a divisional of U.S. application Ser. No. 14/957,948, filed Dec. 3, 2015, which is a continuation of U.S. application Ser. No. 13/367,989, filed Feb. 7, 2012, now U.S. Pat. No. 9,343,318, issued May 17, 2016, which are incorporated herein by reference in their entireties.
- Many semiconductor devices use metal-silicon compounds called silicdes to enhance conductivity between source and drain features and conductive lines. Salicides are self-aligned silicides. Self-aligned refers to a manufacturing technique where a gate electrode region of a transistor is used as a mask for doping the source and drain. Some techniques for forming salicides over source and drain features include depositing a metal layer over a surface of a semiconductor assembly including the source and drain features. The assembly is then annealed to form a salicide in a reaction between silicon atoms in the source and drain features and metal atoms in the metal layer. The unreacted metal is then removed using an etching process.
- The reaction to form salicide consumes silicon atoms in the source and drain features. If the source and drain features have an insufficient amount of silicon at a surface interface with the metal layer, in some instances, the salicide is also etched through during the etching process to remove unreacted metal. Etching through the salicide creates openings that can form short circuits when metal contacts are deposited on the source and drain features. Additionally, in situations where silicon atoms are unevenly concentrated in the source and drain features, voids can form in the salicide and cause the semiconductor device to malfunction.
- One or more embodiments are illustrated by way of example, and not by limitation, in the figures of the accompanying drawings, wherein elements having the same reference numeral designations represent like elements throughout. It is emphasized that, in accordance with standard practice in the industry various features may not be drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features in the drawings may be arbitrarily increased or reduced for clarity of discussion.
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FIG. 1 is a side view diagram of a semiconductor device including cap layers, according to one ore more embodiments. -
FIG. 2 is a flowchart of a method of forming a salicide layer in a semiconductor device including cap layers, according to one or more embodiment. -
FIGS. 3A-3G are side view diagrams of a semiconductor device during various stages of the method ofFIG. 2 . - The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are of course, merely examples and are not intended to be limiting.
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FIG. 1 is a side view diagram of asemiconductor device 100 according to an embodiment.Semiconductor device 100 includes asubstrate 102 having source and drain features 104 insubstrate 102.Semiconductor device 100 includes agate stack 106 andoptional spacers 108 oversubstrate 102.Semiconductor device 100 further includescap layers 110 over at least a portion of source and drain features 104. - In some embodiments,
substrate 102 is silicon. In some embodiments,substrate 102 is silicon germanium, gallium arsenide, germanium or other suitable semiconductor material. In some embodiments,substrate 102 is a semiconductor on insulator such as silicon on insulator - Source and
drain features 104 are areas of higher charge mobility withinsubstrate 102. In some embodiments, source anddrain features 104 have higher hole mobility thansubstrate 102. In some embodiments, source anddrain features 104 have higher electron mobility thansubstrate 102. In some embodiments, source anddrain features 104 are doped with p-type dopants, such as boron or BF2; or n-type dopants, such as phosphorous or arsenic. In some embodiments, source and drain features 104 comprise silicon germanium. In some embodiments, source anddrain features 104 are substantially silicon free. -
Gate stack 106 includes agate electrode 106 a over an optional a gate dielectric 106 b. In some embodiments,gate electrode 106 a comprises polysilicon. In some embodiments,gate electrode 106 a comprises molybdenum, aluminum, copper or other suitable conductive material. In some embodiments, optional gate dielectric 106 b comprises silicon dioxide. In some embodiments, optional gate dielectric 106 b comprises a high k dielectric, such as hafnium silicate, zirconium silicate, hafnium dioxide, zirconium dioxide, or other suitable dielectric material. - In some embodiments, source and drain features 104 and
gate stack 106 collectively form a transistor. In some embodiments, where source anddrain features 104 are selected to enhance hole mobility, source and drain features 104 andgate stack 106 collectively form a p-type metal oxide semiconductor (PMOS) transistor. In some embodiments, where source anddrain features 104 are selected to enhance electron mobility, source and drain features 104 andgate stack 106 collectively form an n-type metal oxide semiconductor (NMOS) transistor. - In some embodiments,
semiconductor device 100 optionally includesspacers 108 along sidewalls ofgate stack 106. In some embodiments,spacers 108 comprise silicon dioxide, silicon nitride, silicon oxynitride or other suitable material. In some embodiments,spacers 108 comprise non-conductive material. -
Cap layers 110 are over source and drain features 104 extending beyondgate stack 106 andoptional spacers 108. In at least some embodiments,cap layers 110 extend over substantially all of source anddrain features 104 extending beyondgate stack 106 andoptional spacers 108.Cap layers 110 comprise silicon. In some embodiments,cap layers 110 have a thickness ranging from about 5 Angstroms to about 10 Angstroms. This range, in some embodiments, is narrower, e.g., from 5 Angstroms to 10 Angstroms. - In the reaction to form a salicide layer (
FIG. 3G ) over source and drain features 104, silicon is consumed. In some embodiments, where source anddrain features 104 do not comprise sufficient silicon concentrations, the salicide layer formed over source anddrain features 104 is insufficiently thick to prevent etching through the salicide layer and prevent exposing source and drain features 104 during removal of unreacted metal. Exposing source anddrain features 104 creates short circuits when metallized features, e.g., vias, are formed in contact with source and drain features 104.Cap layers 110 provide sufficient silicon atoms to form the salicide layer over source and drain features 104 to a thickness sufficient to avoid etching through the salicide layer. The inclusion ofcap layers 110 insemiconductor device 100, thus acts to increase the yield of a production process by reducing the number of semiconductor devices that are defective due to short circuits. -
Cap layers 110 also provide substantially uniform silicon concentration over source and drain features 104. In some instances where the salicide layer is formed with variations in silicon concentration, voids form in the salicide layer thereby increasing resistance to current flow. Increased resistance causessemiconductor device 100 to perform below acceptable standards. Cap layers 110 avoid the formation of voids in the salicide through the substantially uniform distribution of silicon, thereby increasing production yield. -
FIG. 2 is a process flow diagram of amethod 200 of forming asemiconductor device 300, according to one or more embodiments.Method 200 begins with forming source and drain features 104 insubstrate 102,gate stack 106 and optionally spacers 108 oversubstrate 102 inoperation 202. In some embodiments, source and drain features 104 are formed by ion implantation, including tilted ion implantation. In some embodiments, source and drain features 104 are formed by doping, annealing or other suitable processes.Gate stack 106 andoptional spacers 108 are formed using methods known in the art including gate last processes.FIG. 3A is a side view diagram ofsemiconductor device 300 following formation of source and drain features 104,gate stack 106 and optionally spacers 108. -
Method 200 continues withoptional operation 204, in which a photoresist layer 112 (FIG. 3B ) is deposited oversubstrate 102. In some embodiments, outer boundaries of source and drain features 104 are defined by isolation features, another gate stack, or other features oversubstrate 102 ofsemiconductor device 300. If the outer boundaries of source and drain features 104 are defined by another feature,photoresist layer 112 is eliminated, according to some embodiments. In some embodiments, spin-on deposition, physical vapor deposition, or other suitable deposition processdeposits photoresist layer 112 oversubstrate 102. -
Method 200 continues withoptional operation 206, in whichphotoresist layer 112 is patterned and etched. In some embodiments, if the outer boundaries of source and drain features 104 are defined by otherfeatures photoresist layer 112 is eliminated. Ifoperation 204 is not used,operation 206 is likewise omitted. In some embodiments, ultraviolet light passing through a maskpatterns photoresist layer 112. In some embodiments, thermal energy or other suitable patterning processes are used topattern photoresist layer 112. In some embodiments, patternedphotoresist layer 112 is etched using a wet etching process. In other embodiments, the etching process is a dry etching process, a plasma etching process, a reactive ion etching process, or other suitable etching process.FIG. 3C is a side view diagram ofsemiconductor device 300 following patterning and etching ofphotoresist layer 112. - In
operation 208 ofmethod 200, cap layers 110 are deposited over source and drain features 104. In some embodiments, cap layers 110 are deposited using an epitaxial growth process. In some embodiments, cap layers 110 are deposited by sputtering, atomic layer deposition, or other suitable deposition processes. In some embodiments, deposition continues until cap layers 110 have a thickness ranging from about 5 Angstroms to about 10 Angstroms.FIG. 3D is a side view diagram ofsemiconductor device 300 following deposition of cap layers 110. - Following deposition of cap layers 110,
optional photoresist layer 112 is removed. In some embodiments,photoresist layer 112 is removed using plasma ashing. In some embodiments,photoresist layer 112 is removed using etching or other suitable removal processes. - In
operation 210, a metal layer 114 (FIG. 3E ) is deposited oversubstrate 102. In some embodiments,metal layer 114 is deposited using physical vapor deposition. In some embodiments,metal layer 114 is deposited using chemical vapor deposition, atomic layer deposition, electron beam evaporation, sputtering, or other suitable deposition process. In some embodiments,metal layer 114 comprises nickel, cobalt, titanium, platinum, or other suitable metal material. In some embodiments, the deposition process continues untilmetal layer 114 has a thickness ranging from about 200 Angstroms to about 400 Angstroms. This range, in some embodiments, is narrower, e.g., from 200 Angstroms to 400 Angstroms.FIG. 3E is a side view diagram ofsemiconductor device 300 following deposition ofmetal layer 114. -
Method 200 continues withoperation 212, in whichsemiconductor device 300 is heated during an annealing process. The annealing process causes metal atoms inmetal layer 114 to react with silicon atoms incap layers 110 and in source and drain features 104 to create the salicide layer. In some embodiments, during the annealingprocess semiconductor device 300 is heated to a temperature ranging from about 200 C to about 800 C. This range, in some embodiments, is narrower, e.g., from 200 C to 800 C. In some embodiments, the annealing process continues for a duration ranging from about 1 minute to about 10 minutes. - In some embodiments, the annealing process tunes the resistivity of the salicide layer. Generally, the higher the annealing temperature and the longer the annealing duration, the lower the resistivity of the resulting salicide layer because of the formation of larger grains in the salicide layer. If the metal of
metal layer 114 and the silicon ofcap layers 110 react to form different compounds, tailoring the annealing process allows selective formation of a desired salicide compound. For example, when the metal ofmetal layer 114 is nickel, the desired salicide compound is NiSi, instead of materials with a higher resistivity such as Ni2Si or NiSi2. In order to obtain the highest concentration of NiSi in the salicide layer, the annealing process takes place at a temperature of about 200 C to about 500 C for a duration of about one minute. -
FIG. 3F is a side view diagram ofsemiconductor device 300 following the annealing process. The annealing process causesmetal layer 114 to react with silicon to formsalicide layer 116. In some embodiments,salicide layer 116 has a thickness ranging from about 120 Angstroms to about 300 Angstroms. This range, in some embodiments, is narrower, e.g., from 120 Angstroms to 300 Angstroms. In some embodiments,gate electrode 106 a contains silicon, e.g., polysilicon, and the annealing process causesmetal layer 114 to react with silicon atoms ofgate electrode 106 a to form a salicide layer overgate stack 106 as well as over source and drain features 104. - If the temperature of
semiconductor device 300 is lowered below a temperature needed formetal layer 114 to react with silicon, the salicide forming reaction ceases, but unreacted metal remains inmetal layer 114. Inoperation 214, unreacted metal inmetal layer 114 is removed. In some embodiments, the unreacted metal is removed using an etching process such as wet etching, dry etching, reactive ion etching, plasma etching, or another suitable etching process.FIG. 3G is a side view diagram ofsemiconductor device 300 following removal of the unreacted metal. - The inclusion of cap layers 110 helps to form
salicide layers 116 with sufficient thickness, to prevent the process removingmetal layer 114 inoperation 214 from also exposing source and drain features 104 through portions of salicide layers 116. In some embodiments where the source and drain features 104 include silicon germanium, the inclusion ofcap layers 110 also aids in formingsalicide layers 116 having reduced amounts of germanium within the salicide layers. In some embodiments, a germanium concentration within salicide layers 116 is less than about 3% by weight. Using conventional techniques which do not include cap layers 110, a germanium concentration within conventional salicide layers ranges from about 13% by weight to about 17% by weight. - Following formation of
salicide layers 116, electrical contacts are connected tosalicide layers 116 and electrically connected to an interconnect structure to incorporatesemiconductor device 300 into a circuit. Including cap layers 110 in the formation ofsemiconductor device 300 increases production yield over formation processes in which cap layers 110 are omitted. - One aspect of this description relates to a method of forming a semiconductor device. The method includes forming a source feature and a drain feature in a substrate. The method further includes forming a gate stack over a first portion of the source feature and a first portion of the drain feature, the gate stack comprising a gate electrode. The method further includes depositing a first cap layer comprising silicon over a second portion of the source feature exposed by the gate stack. The method further includes depositing a second cap layer comprising silicon over a second portion of the drain feature exposed by the gate stack. The method further includes depositing a metal layer over the gate stack, the first cap layer and the second cap layer. The method further includes annealing the semiconductor device until all of the silicon in the first cap layer and the second cap layer reacts with metal from the metal layer, wherein the annealing causes metal from the metal layer to react with silicon in the first cap layer, the second cap layer, the source feature, and the drain feature while leaving at least a portion of the gate electrode free of silicide. Annealing the semiconductor device includes annealing the semiconductor device at a temperature ranging from 450° C. to 800° C. to form a salicide layer having a germanium concentration less than 3% by weight.
- Another aspect of this description relates to a method of forming a semiconductor device. The method includes forming a source feature and a drain feature in a substrate. The method further includes forming a gate stack over a first portion of the source feature and a first portion of the drain feature, the gate stack comprising a gate electrode. The method further includes depositing, patterning, and etching a photoresist layer over the substrate. The method further includes depositing a first cap layer comprising silicon over a second portion of the source feature exposed by the gate stack and the photoresist layer. The method further includes depositing a second cap layer comprising silicon over a second portion of the drain feature exposed by the gate stack and the photoresist layer. The method further includes removing the photoresist layer. The method further includes depositing a metal layer over the gate stack, the first cap layer and the second cap layer. The method further includes annealing the semiconductor device until all of the silicon in the first cap layer and the second cap layer is consumed by a silicidation reaction, wherein the annealing causes metal from the metal layer to react with silicon in the first cap layer, the second cap layer, the source feature, and the drain feature while leaving at least a portion of the gate electrode free of silicide. Annealing the semiconductor device includes annealing the semiconductor device at a temperature ranging from 450° C. to 800° C. to form a silicide layer having a germanium concentration less than 3% by weight.
- Still another aspect of this description relates to a semiconductor device. The semiconductor device includes a substrate having a source feature and a drain feature therein configured to enhance charge mobility. The semiconductor device further includes a gate stack over a portion of the source feature and a portion of the drain feature. The semiconductor device further includes a first salicide layer over substantially the entire source feature not covered by the gate stack, wherein the first salicide layer has a germanium concentration less than about 3% by weight. The semiconductor device further includes a second salicide layer over substantially the entire drain feature not covered by the gate stack, wherein the second salicide layer has a germanium concentration less than about 3% by weight.
- It will be readily seen by one of ordinary skill in the art that the disclosed embodiments fulfill one or more of the advantages set forth above. After reading the foregoing specification, one of ordinary skill will be able to affect various changes, substitutions of equivalents and various other embodiments as broadly disclosed herein. It is therefore intended that the protection granted hereon be limited only by the definition contained in the appended claims and equivalents thereof.
Claims (20)
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US15/981,665 US20180261461A1 (en) | 2012-02-07 | 2018-05-16 | Salicide formation using a cap layer |
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US10593600B2 (en) | 2016-02-24 | 2020-03-17 | International Business Machines Corporation | Distinct gate stacks for III-V-based CMOS circuits comprising a channel cap |
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US20020036353A1 (en) * | 2000-09-22 | 2002-03-28 | Song Won-Sang | Semiconductor device having a metal silicide layer and method for manufacturing the same |
US20050093021A1 (en) * | 2003-10-31 | 2005-05-05 | Ouyang Qiqing C. | High mobility heterojunction complementary field effect transistors and methods thereof |
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JPH118387A (en) * | 1997-06-18 | 1999-01-12 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
US6974737B2 (en) * | 2002-05-16 | 2005-12-13 | Spinnaker Semiconductor, Inc. | Schottky barrier CMOS fabrication method |
US6902994B2 (en) * | 2003-08-15 | 2005-06-07 | United Microelectronics Corp. | Method for fabricating transistor having fully silicided gate |
JP4181537B2 (en) * | 2004-11-12 | 2008-11-19 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
US7384853B2 (en) * | 2005-08-25 | 2008-06-10 | United Microelectronics Corp. | Method of performing salicide processes on MOS transistors |
US7432559B2 (en) * | 2006-09-19 | 2008-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Silicide formation on SiGe |
US8344447B2 (en) * | 2007-04-05 | 2013-01-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Silicon layer for stopping dislocation propagation |
US7989901B2 (en) * | 2007-04-27 | 2011-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | MOS devices with improved source/drain regions with SiGe |
US7981749B2 (en) * | 2007-08-20 | 2011-07-19 | GlobalFoundries, Inc. | MOS structures that exhibit lower contact resistance and methods for fabricating the same |
KR101369907B1 (en) * | 2007-10-31 | 2014-03-04 | 주성엔지니어링(주) | Transistor and method of manufacturing the same |
US20090152590A1 (en) * | 2007-12-13 | 2009-06-18 | International Business Machines Corporation | Method and structure for semiconductor devices with silicon-germanium deposits |
DE102009015748B4 (en) * | 2009-03-31 | 2014-05-22 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Reducing the silicide resistance in SiGe-containing drain / source regions of transistors |
US20110065245A1 (en) * | 2009-09-13 | 2011-03-17 | Jei-Ming Chen | Method for fabricating mos transistor |
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US20020036353A1 (en) * | 2000-09-22 | 2002-03-28 | Song Won-Sang | Semiconductor device having a metal silicide layer and method for manufacturing the same |
US20050093021A1 (en) * | 2003-10-31 | 2005-05-05 | Ouyang Qiqing C. | High mobility heterojunction complementary field effect transistors and methods thereof |
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US9343318B2 (en) | 2016-05-17 |
US9978604B2 (en) | 2018-05-22 |
US20160093497A1 (en) | 2016-03-31 |
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