CN109950151B - PMOS transistor and forming method thereof - Google Patents
PMOS transistor and forming method thereof Download PDFInfo
- Publication number
- CN109950151B CN109950151B CN201711390693.XA CN201711390693A CN109950151B CN 109950151 B CN109950151 B CN 109950151B CN 201711390693 A CN201711390693 A CN 201711390693A CN 109950151 B CN109950151 B CN 109950151B
- Authority
- CN
- China
- Prior art keywords
- epitaxial layer
- layer
- forming
- ions
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
A PMOS transistor and a forming method thereof are provided, the forming method comprises the following steps: providing a substrate; forming a gate structure on the substrate; and forming a first epitaxial layer and a second epitaxial layer on the first epitaxial layer on the substrate at two sides of the gate structure, wherein modulation ions are doped in the second epitaxial layer. Modulating ions are doped in the second epitaxial layer to reduce a Schottky barrier between a plug formed subsequently and the second epitaxial layer, reduce contact resistance between the plug and the second epitaxial layer, and further improve the performance of the formed semiconductor structure.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a PMOS transistor and a forming method thereof.
Background
In the fabrication of integrated circuits, after semiconductor device structures are formed, it is necessary to connect the semiconductor devices together to form a circuit. With the continuous development of integrated circuit manufacturing technology, the requirements for the integration level and performance of integrated circuits become higher and higher. In order to improve the integration level and reduce the cost, the critical dimensions of the devices are becoming smaller, and the circuit density inside the integrated circuits is becoming greater, so that the wafer surface cannot provide enough area to manufacture the interconnection lines required by the conventional circuits.
In order to meet the requirement of the interconnection line after the critical dimension is reduced, the conduction of different metal layers or metal layers and the semiconductor device structure is realized through the interconnection structure at present. The interconnection structure includes an interconnection line and a plug located in a contact hole, the plug in the contact hole is used for connecting semiconductor devices, and the interconnection line connects the plugs on different semiconductor devices to form a circuit.
With the continuous reduction of integrated circuit process nodes, the contact resistance between a plug and a transistor source-drain doped region is increased along with the reduction of the size of a device and the smaller contact area of the plug, and in order to reduce the contact resistance between the plug and the source-drain doped region, metal silicide is introduced between the plug and the source-drain doped region.
However, even if metal silicide is introduced, the contact resistance of the PMOS transistor in the semiconductor device formed by the prior art is still large, thereby affecting the electrical performance of the formed semiconductor structure.
Disclosure of Invention
The invention provides a PMOS transistor and a forming method thereof, which aims to reduce the contact resistance between an insert plug and a source-drain doped region and improve the performance of a formed semiconductor structure.
In order to solve the above problem, the present invention provides a method for forming a PMOS transistor, comprising:
providing a substrate; forming a gate structure on the substrate; and forming a first epitaxial layer and a second epitaxial layer on the first epitaxial layer on the substrate at two sides of the gate structure, wherein modulation ions are doped in the second epitaxial layer.
Optionally, the modulating ions are Ni or Al.
Optionally, a ratio of the thickness of the second epitaxial layer to the thickness of the first epitaxial layer is in a range from 8:1 to 12: 1.
Optionally, the thickness of the second epitaxial layer is in a range of 1nm to 10 nm.
Optionally, the doping concentration of the modulation ions in the second epitaxial layer is 5E12atom/cm3To 5E14atom/cm3Within the range.
Optionally, the second epitaxial layer is further doped with a repair ion, and the repair ion is Pt.
Optionally, the doping concentration of the repair ions in the second epitaxial layer is 5E12atom/cm3To 5E14atom/cm3Within the range.
Optionally, the step of forming the first epitaxial layer and the second epitaxial layer includes: forming openings on the substrate on two sides of the grid electrode structure in an upward mode; filling a semiconductor material into the opening through a first epitaxial process to form the first epitaxial layer; forming the second epitaxial layer on the first epitaxial layer by a second epitaxial process.
Optionally, in-situ doping is performed during the second epitaxy process.
Optionally, the process gas used in the second epitaxy process includes a first doping gas; the modulating ions are Ni, and the first doping gas is Ni (MeC (NtBu)2) 2; the modulating ions are Al, and the first doping gas is (CH3)2 AlH.
Optionally, the process gas used in the second epitaxy process further includes a second doping gas, and the second doping gas is mecppptme 3.
Optionally, the second epitaxy process and the second epitaxy process are performed in the same process chamber.
Optionally, after forming the first epitaxial layer and the second epitaxial layer, the method further includes: forming a metal precursor layer, wherein the metal precursor layer covers a part of the second epitaxial layer; and carrying out annealing treatment, so that at least part of the thickness of the second epitaxial layer reacts with the metal precursor layer to form a connecting layer.
Correspondingly, the invention also provides a PMOS transistor, comprising:
a substrate; a gate structure located on the substrate; the first epitaxial layer is positioned on the substrate at two sides of the grid structure; a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having modulation ions doped therein.
Optionally, the conditioning ions are nickel ions or aluminum ions.
Optionally, a ratio of the thickness of the second epitaxial layer to the thickness of the first epitaxial layer is in a range from 8:1 to 12: 1.
Optionally, the thickness of the second epitaxial layer is in a range of 1nm to 10 nm.
Optionally, the doping concentration of the modulation ions in the second epitaxial layer is 5E12atom/cm3To 5E14atom/cm3Within the range.
Optionally, the second epitaxial layer is further doped with a repair ion, and the repair ion is Pt.
Optionally, the doping concentration of the repair ions in the second epitaxial layer is 5E12atom/cm3To 5E14atom/cm3Within the range.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the second epitaxial layer and the first epitaxial layer jointly form a source-drain doped region of the formed PMOS transistor, and the second epitaxial layer is located on the first epitaxial layer, so that the subsequently formed plug is in contact connection with the second epitaxial layer. Because the second epitaxial layer is internally provided with the modulation ions, the modulation ions can effectively reduce the Schottky barrier between the plug formed subsequently and the second epitaxial layer, thereby effectively reducing the contact resistance between the plug formed subsequently and the source-drain doped region of the PMOS transistor, and being beneficial to improving the performance of the formed semiconductor structure.
In an alternative scheme of the invention, the repair ions are Ni, the second epitaxial layer is also doped with repair ions, and the repair ions are Pt; therefore, the addition of the repair ions can effectively inhibit the formation of Spike defects (Spike defects) in the second epitaxial layer, thereby effectively improving the quality of a subsequently formed connecting layer, being beneficial to reducing the probability of the occurrence of the Spike discharge phenomenon and being beneficial to improving the performance of the formed semiconductor structure.
In the alternative of the invention, the doping concentration of the repair ions is 5E12atom/cm3To 5E14atom/cm3Within the range. The doping concentration of the repair ions is preferably neither too high nor too low. If the doping concentration of the repair ions is too low, the suppression effect of the repair ions on the peak defects may be affected, the peak defects in the formed second epitaxial layer may be caused, the probability of the occurrence of the peak discharge phenomenon in the formed semiconductor structure is increased, and thus the stability and performance of the formed semiconductor structure are easily affected; if the doping concentration of the repair ions is too high, the performance of the source/drain doped region of the PMOS transistor and the performance of the connection layer may be affected, which may easily cause the formation of a semiconductorDegradation of structural performance.
Drawings
Fig. 1 to 4 are schematic cross-sectional views of steps of a PMOS transistor forming method according to an embodiment of the invention.
Detailed Description
As known from the background art, even though metal silicide is introduced in the prior art, the PMOS transistor in the formed semiconductor device has the problem of overlarge contact resistance between a plug and a source-drain doped region. The reason for the problem of excessive contact resistance is analyzed in combination with the structure of a PMOS transistor:
as described in the background, in order to reduce the contact resistance between the plug and the source and drain doped regions of the transistor, which is becoming more effective, a connection layer is typically formed in the region of contact between the plug and the source and drain doped regions. Typically, the tie layer is typically a titanium-silicon compound (Ti-silicon).
For an NMOS transistor, the silicon-titanium compound can effectively reduce a Schottky barrier between the plug and the source-drain doped region material, so that the contact resistance between the plug and the source-drain doped region can be effectively reduced; however, as for PMOS transistors, the silicon titanium compound cannot effectively reduce the Schottky Barrier Height (SBH) between the plug and the source/drain doped region, thereby affecting the reduction of the contact resistance between the plug and the source/drain doped region and the performance of the formed semiconductor structure.
In order to solve the technical problem, the invention provides a PMOS transistor and a method for forming the same, which reduces a schottky barrier between a plug formed subsequently and the second epitaxial layer by doping modulation ions in the second epitaxial layer, reduces a contact resistance between the plug and the second epitaxial layer, and further improves the performance of a formed semiconductor structure.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 1 to 4, schematic cross-sectional structures corresponding to steps of a PMOS transistor forming method according to an embodiment of the invention are shown.
Referring to fig. 1, a substrate 110 is provided.
The substrate 110 is used to provide a process platform.
It should be noted that, in this embodiment, the substrate 110 includes a PMOS region 102 for forming a PMOS transistor. In addition, as shown in fig. 1, the substrate 110 further includes an NMOS region 101 for forming an NMOS transistor. Specifically, the PMOS region 102 and the NMOS region 101 are disposed adjacent to each other. However, in other embodiments of the present invention, the PMOS region and the NMOS region may not be disposed adjacently.
In this embodiment, the PMOS transistor is a fin field effect transistor, so the substrate 110 is further formed with a fin 120. Specifically, the fin portion 120 is formed on the substrate 110 of each of the PMOS region 102 and the NMOS region 101. In other embodiments of the present invention, the PMOS transistor may also be a planar transistor, and the substrate is a planar substrate.
In this embodiment, the substrate 110 is made of monocrystalline silicon. In other embodiments of the present invention, the substrate may also be a polysilicon substrate, an amorphous silicon substrate or a silicon germanium substrate, a carbon silicon substrate, a silicon on insulator substrate, a germanium on insulator substrate, a glass substrate or a III-V compound substrate, such as a gallium nitride substrate or a gallium arsenide substrate. The material of the substrate may be chosen to be suitable for the process requirements or to be easily integrated.
The fins 120 are used to provide channels for the transistors formed.
In this embodiment, the material of the fin 120 is the same as that of the substrate 110, and is also monocrystalline silicon. In other embodiments of the present invention, the material of the fin may be different from the material of the substrate, and may be selected from materials suitable for forming a fin, such as germanium, silicon carbon, or gallium arsenide.
Specifically, the substrate 110 and the fin 120 may be formed simultaneously. The steps of forming the substrate 110 and the fin 120 include: providing an initial substrate; forming a fin mask layer (not shown) on the surface of the initial substrate; and etching the initial substrate by taking the fin part mask layer as a mask to form the substrate 110 and the fin part 120 positioned on the substrate 110.
In this embodiment, the PMOS transistor further includes: an isolation layer (not shown) is disposed on the substrate 110 between adjacent fins 120.
The isolation layer covers a portion of the sidewalls of the fins 120, and a top of the isolation layer is lower than a top of the fins 120. The isolation layer is used as an isolation layer of the semiconductor structure and can play a role in electrical isolation between adjacent devices and adjacent fin parts. The isolation layer is located on the substrate 110 where the fins 120 are exposed, and the height of the isolation layer is lower than the height of the fins 120.
In this embodiment, the isolation layer is made of silicon oxide. In other embodiments of the present invention, the material of the isolation layer may also be other insulating materials such as silicon nitride or silicon oxynitride.
In this embodiment, the step of forming the isolation layer includes: forming an isolation material layer (not labeled) on the substrate 110 exposed by the fins 120, wherein the isolation material layer covers the tops of the fins 120; grinding to remove the isolation material layer on top of the fins 120; removing part of the thickness of the remaining isolation material layer in a back etching manner to expose the top and part of the sidewall of the fin portion 120, thereby forming the isolation layer; the fin mask layer is removed to expose the top of the fin 120.
With continued reference to fig. 1, a gate structure 130 is formed on the substrate 110.
The gate structure 130 is used to control the conduction and the cut-off of the channel of the formed semiconductor structure.
In this embodiment, the fin 120 is disposed on the substrate 110, so that the gate structure 130 crosses over the fin 120 and covers a portion of the top and a portion of the sidewall of the fin 120. In addition, the substrate 110 includes the NMOS region 101 and the PMOS region 102, so the gate structure 130 is formed on the NMOS region 101 and the PMOS region 102.
In this embodiment, the gate structure 130 is a polysilicon gate structure. The gate structure 130 includes a gate dielectric layer (not shown) on the substrate 110 and a gate electrode (not shown) on the gate dielectric layer. The gate dielectric layer is made of silicon oxide, and the gate electrode is made of polysilicon.
In other embodiments of the present invention, the gate structure may also be a metal gate structure, and includes a gate dielectric layer on the substrate, a work function layer on the gate dielectric layer, and an electrode layer on the work function layer. The gate dielectric layer can be made of a high-K dielectric material; the work function layer is made of a P-type work function material, the work function range is 5.1eV to 5.5eV, and the P-type work function layer can be specifically selected from one or more of TiN, TaN, TaSiN and TiSiN; the material of the electrode layer may be selected from one or more of W, Al, Cu, Ag, Au, Pt, Ni and Ti.
Specifically, in the present embodiment, the substrate 110 further has the fin portion 120 thereon, so the step of forming the gate structure 130 includes: forming a dielectric material layer on the surface of the fin portion 120; forming an electrode material layer on the dielectric material layer; and sequentially etching the electrode material layer and the dielectric material layer until part of the surface of the fin portion 120 is exposed, and forming the gate structure 130.
In this embodiment, after forming the gate structure 130, the forming method further includes: a sidewall spacer (not labeled in the figure) is formed on the sidewall of the gate structure 130 to protect the gate structure and to define the position of the subsequently formed source/drain doped region. In this embodiment, the sidewall is of a single-layer structure, and the material of the sidewall is silicon nitride. In other embodiments of the present invention, the material of the sidewall may also be silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride, and the sidewall may also be a stacked structure.
Referring to fig. 2 and 3, a first epitaxial layer 141 and a second epitaxial layer 142 on the first epitaxial layer 141 are formed on the substrate 110 at both sides of the gate structure 130, and the second epitaxial layer 142 is doped with modulation ions.
The first epitaxial layer 141 and the second epitaxial layer 142 are used for forming a source-drain doped region 140 of the formed PMOS transistor.
Because the second epitaxial layer 141 has the modulating ions therein, the modulating ions can effectively reduce the schottky barrier between the subsequently formed plug and the second epitaxial layer 141, thereby reducing the contact resistance between the subsequent plug and the drain doping region and being beneficial to improving the performance of the formed semiconductor structure.
It should be noted that, in this embodiment, the substrate 110 includes the PMOS region 102 and the NMOS region 101, so after forming the spacers and before forming the first epitaxial layer 141, the forming method further includes: a mask layer (not shown) is formed on the NMOS region 101.
The mask layer conformally covers the fin 120 and the gate structure 130 on the NMOS region 101 to protect the structure on the NMOS region 101 and prevent the formation process of the first epitaxial layer 141 and the second epitaxial layer 142 from adversely affecting the structure on the NMOS region 101.
Specifically, the mask layer is made of silicon nitride and is formed in an atomic layer deposition mode. In other embodiments of the present invention, the material of the mask layer may also be selected from one or more of silicon nitride carbide, silicon nitride boride, silicon nitride oxycarbide, and silicon oxynitride. The material of the mask layer is different from the material of the fin portion 120, and the material of the mask layer is different from the material of the isolation layer. The mask layer can also be formed by other film deposition processes such as chemical vapor deposition or physical vapor deposition.
In this embodiment, the modulating ions are Ni. In other embodiments of the present invention, the modulating ions may also be Al. The doping of Ni or Al can reduce the schottky barrier between the second epitaxial layer 142 and the plug to achieve the purpose of reducing the contact resistance.
Specifically, the doping concentration of the modulation ions in the second epitaxial layer 142 is 5E12atom/cm3To 5E14atom/cm, i.e., the doping concentration of Ni in the second epitaxial layer 142 is 5E12atom @cm3To 5E14 atom/cm.
The doping concentration of the modulating ions should not be too high nor too low. If the doping concentration of the modulation ions is too low, the function of the modulation ions for reducing the schottky barrier between the subsequently formed plug and the source-drain doped region 140 may be affected, which is not beneficial to reducing the reduction of the contact resistance between the plug and the source-drain doped region 140; if the doping concentration of the modulation ions is too high, the probability of formation of a spike defect in the second epitaxial layer 142 may be increased, the performance of the source/drain doped region 140 formed by the first epitaxial layer 141 and the second epitaxial layer 142 may be affected, and the performance of the formed PMOS transistor may be affected.
It should be noted that the ratio of the second epitaxial layer 142 may affect the performance of the source/drain doped region 140, and thus the performance of the semiconductor structure. In this embodiment, the ratio of the thickness of the second epitaxial layer 140 to the thickness of the first epitaxial layer 140 is in the range of 8:1 to 12: 1.
The ratio of the thickness of the second epitaxial layer 140 to the thickness of the first epitaxial layer 140 is preferably neither too high nor too large.
If the ratio of the thickness of the second epitaxial layer 140 to the thickness of the first epitaxial layer 140 is too high, the ratio of the second epitaxial layer 140 in the source-drain doped region 140 is too high, and modulated ions in the second epitaxial layer 140 may cause metal ion pollution to the source-drain doped region 140, thereby causing performance degradation of the source-drain doped region 140; if the ratio of the thickness of the second epitaxial layer 140 to the thickness of the first epitaxial layer 140 is too low, the thickness of the second epitaxial layer 140 is too small, which may affect the function of reducing the schottky barrier between the plug formed in the following step and the source/drain doped region 140, and is not favorable for reducing the reduction of the contact resistance between the plug and the source/drain doped region 140.
Specifically, in this embodiment, the thickness of the second epitaxial layer 142 is in a range from 1nm to 10 nm.
In this embodiment, the second epitaxial layer 142 is further doped with a repair ion. The repair ions are used for inhibiting formation of Spike defects (Spike defects) in the second epitaxial layer 142, so that the quality of the second epitaxial layer 142 can be effectively improved, the probability of occurrence of the Spike discharge phenomenon is reduced, and the performance of the formed semiconductor structure is improved. Specifically, the repair ion is Pt.
Specifically, the doping concentration of the repair ions in the second epitaxial layer 142 is 5E12 atoms/cm3To 5E14atom/cm3Within the range.
The doping concentration of the repair ions is preferably neither too high nor too low. If the doping concentration of the repair ions is too low, the suppression effect of the repair ions on the spike defects may be affected, the spike defects in the formed second epitaxial layer 142 may be caused, and the probability of the spike discharge phenomenon in the formed semiconductor structure is increased, so that the stability and performance of the formed semiconductor structure are easily affected; if the doping concentration of the repair ions is too high, metal ion contamination may be caused to the source/drain doped region 140, and the performance of the source/drain doped region 140 and the performance of a connection layer formed subsequently may be affected, thereby easily causing degradation of the performance of the formed semiconductor structure.
Specifically, the step of forming the first epitaxial layer 141 and the second epitaxial layer 142 includes: as shown in fig. 2, an opening 143 is formed in the substrate 110 on both sides of the gate structure 130; referring to fig. 3, a semiconductor material is filled into the opening 143 through a first epitaxial process to form the first epitaxial layer 141; the second epitaxial layer 142 is formed on the first epitaxial layer 141 through a second epitaxial process.
The opening 143 is used to provide a process space for the formation of the first epitaxial layer 141 and the second epitaxial layer 142.
In this embodiment, the fin portion 120 is further formed on the substrate 110, so the step of forming the opening 143 includes: and etching the fin parts 120 on the two sides of the gate structure 130 in the PMOS region 102 by using the mask layer as a mask to form the openings 143 in the fin parts 120 on the two sides of the gate structure 130.
The first epitaxial process and the second epitaxial process are used to fill the opening 143 with a semiconductor material, thereby forming the first epitaxial layer 141 and the second epitaxial layer 142, respectively.
Specifically, the material of the first epitaxial layer 141 is P-type doped Si or SiGe, wherein the doping ions may be B, Ga or In. The steps of the first epitaxial process therefore include: filling Si or SiGe into the opening 143 by means of epitaxial growth; and In-situ doping (In-situ dope) is performed during the first epitaxial process.
In another embodiment of the present invention, the first epitaxial layer 141 may be doped by other methods such as ion implantation, so the step of forming the first epitaxial layer includes: filling Si or SiGe into the opening in an epitaxial growth mode to form a first semiconductor layer; after the first semiconductor layer is formed, ion implantation is performed on the first semiconductor layer to form the first epitaxial layer.
The concentration of dopant ions in the first epitaxial layer 141 and the specific process parameters of the first epitaxial process are related to the specific performance requirements of the formed PMOS transistor, i.e., related to the design of the formed PMOS transistor. The present invention will not be described herein.
The material of the second epitaxial layer 142 is P-type doped Si or SiGe, and the second epitaxial layer 142 is further doped with the modulation ions, so the second epitaxial process includes: forming a second epitaxial layer 142 on the first epitaxial layer 142 by means of epitaxial growth; and in-situ doping is performed during the second epitaxial process.
In this embodiment, the modulating ions are Ni, so the process gas used in the second epitaxy process includes a first doping gas, and the first doping gas is Ni (mec (ntbu)2)2. It should be noted that, in other embodiments of the present invention, the modulating ion may also be Al, so the first doping gas may also be (CH)3)2AlH。
Further, the secondIn the epitaxial process, the adopted process gas further comprises: NH (NH)3And H2. Therefore, the process gas used in the second epitaxial process comprises the first doping gas, NH3And H2The mixed gas of (1).
The second epitaxial layer 142 is further doped with the repair ions, the repair ions are Pt, so the process gas used in the second epitaxial process further includes a second doping gas, and the second doping gas is mecppptme3。
It should be noted that, in this embodiment, the first epitaxy process and the second epitaxy process are performed in the same process chamber, so that the process steps can be effectively reduced, the process efficiency is improved, the stability of the formation process of the source/drain doped region 140 can be ensured, and the performance of the formed PMOS transistor can be improved.
In addition, in this embodiment, the first epitaxial process and the second epitaxial process are performed continuously. That is to say, after the first epitaxy process is performed, the first doping gas and the second doping gas are introduced into the process chamber, and the second epitaxy process is performed, so that the connection between the first epitaxy layer 141 and the second epitaxy layer 142 can be effectively ensured, the integrity of the source/drain doping region 140 is ensured, and the improvement of the device performance is facilitated. Therefore, the processes of the first epitaxial process and the second epitaxial process can be regarded as an epitaxial growth process, and only the first doping gas and the second doping gas are introduced at the later stage of the epitaxial growth process.
Referring to fig. 4, in this embodiment, after forming the first epitaxial layer 141 and the second epitaxial layer 142, the forming method further includes: forming a metal precursor layer covering a portion of the second epitaxial layer 142; an anneal process is performed to react at least a portion of the thickness of the second epitaxial layer 142 with the metal precursor layer to form a connecting layer 160.
In this embodiment, after forming the first epitaxial layer 141 and the second epitaxial layer 142, and before forming the metal precursor layer, the forming method further includes: a third epitaxial layer (not shown) is formed in the fin 120 on the NMOS region 101 at two sides of the gate structure 130.
And the third epitaxial layer is used for forming a source-drain doped region of the formed NMOS transistor.
The material of the third epitaxial layer is N-type doped Si or SiC, wherein the doping ions can be P, As or Sb. The step of forming said third epitaxial layer comprises: forming openings (not shown) in the fin 120 at two sides of the gate structure 130 in the NMOS region 101; filling Si or SiC into the opening in an epitaxial growth mode; and carrying out in-situ doping in the epitaxial growth process to form the third epitaxial layer.
It should be noted that, in this embodiment, a source/drain doped region 140 on the PMOS region 102 is formed first, and then a source/drain doped region on the NMOS region 101 is formed, which is taken as an example for description. In this process sequence, as shown in fig. 4, only a sidewall is formed on the sidewall of the gate structure 130 in the PMOS region 101, and a mask layer is formed on the sidewall of the gate structure 130 in the NMOS region 101 as well as the sidewall, so that the distance between the source-drain doped region 140 in the PMOS region 102 and the gate structure 130 is shorter and closer to the channel region below the gate structure 130, which is beneficial to improving the mobility of carriers in the formed channel and inhibiting the short channel effect.
Therefore, after the third epitaxial layer is formed, an interlayer dielectric layer 150 is formed on the source/drain doped region 140.
The interlevel dielectric layer 150 is used to achieve electrical isolation between adjacent semiconductor structures and between adjacent metal structures.
In this embodiment, the interlayer dielectric layer 150 is made of silicon oxide. In other embodiments of the present invention, the material of the interlayer dielectric layer may also be selected from other dielectric materials such as silicon nitride, silicon oxynitride, silicon oxycarbonitride, and the like.
Specifically, the substrate 110 further has the fin portions 120, an isolation layer is filled between adjacent fin portions 120, and a gate structure 130 is further formed on the fin portions 120. Therefore, the interlayer dielectric layer 150 is filled between the adjacent gate structures 130 and is located on the substrate 110, the fin 120, the isolation layer and the source/drain doped region 140, and the top of the interlayer dielectric layer 150 is higher than the top of the gate structure 130.
It should be noted that, in other embodiments of the present invention, when a gate-last process is adopted, the gate structure is a dummy gate structure, so the step of forming the interlayer dielectric layer includes: after forming a source-drain doped region on the NMOS region, forming a first dielectric layer on the substrate exposed out of the dummy gate structure, wherein the first dielectric layer exposes out of the dummy gate structure; removing the pseudo gate structure, and forming a gate opening in the first dielectric layer; forming a gate structure in the gate opening; and forming a second dielectric layer on the first dielectric layer and the grid structure, wherein the second dielectric layer and the first dielectric layer are used for forming the interlayer dielectric layer.
The first dielectric layer is used for realizing electrical isolation between adjacent semiconductor structures and also used for defining the size and the position of the gate structure; the second dielectric layer is used for realizing electric isolation between adjacent semiconductor structures.
The first dielectric layer and the second dielectric layer are used for forming the interlayer dielectric layer, so the first dielectric layer and the second dielectric layer are both made of silicon oxide. In other embodiments of the present invention, the first dielectric layer and the second dielectric layer may also be made of other insulating materials, which may be the same or different.
The technical solution of forming the gate structure in the gate opening can refer to the technical solution of the gate structure in the foregoing embodiment, and the description of the present invention is omitted here.
After the interlayer dielectric layer 150 is formed, a contact hole (not labeled in the figure) penetrating through the interlayer dielectric layer 150 is formed, and the bottom of the contact hole exposes the source-drain doped regions on the PMOS region 102 and the NMOS region.
The contact hole is used for exposing the source-drain doped region, so that a process basis is provided for the formation of a subsequent plug.
In this embodiment, the source-drain doped region 140 on the PMOS region includes the first epitaxial layer 141 and the second epitaxial layer 142, and the second epitaxial layer 142 is located on the first epitaxial layer 141; the second epitaxial layer 142 is exposed at the bottom of the contact hole in the interlayer dielectric layer 150 on the PMOS region.
After the contact holes are formed, a metal precursor layer (not shown) is formed on the source-drain doped regions of the NMOS region 101 and the PMOS region 102.
The metal precursor layer is used for reacting with a part of material of the source-drain doped region to form a connecting layer 160, so that contact resistance between a subsequently formed plug and the source-drain doped region is reduced. Specifically, the metal precursor layer is formed on the bottom and the side wall of the contact hole. In this embodiment, the material of the precursor metal layer is Ti. The specific technical scheme for forming the precursor metal layer is the same as that in the prior art, and the detailed description of the invention is omitted.
After the metal precursor layer is formed, annealing treatment is performed, and the annealing treatment enables the metal precursor layer and the source-drain doped region material with partial thickness to react, so that a connecting layer 160 is formed: for the NMOS transistor formed in the NMOS region 101, the material of the connection layer 160 is a silicon-titanium compound, so that the schottky barrier between the plug and the source-drain doped region material can be effectively reduced, and the contact resistance between the plug and the source-drain doped region can be effectively reduced; for the PMOS transistor formed in the PMOS region 102, the material of the connection layer 160 is a silicon-titanium compound doped with a certain dose of modulation ions, and the doping of the modulation ions can effectively reduce the schottky barrier between the plug and the material of the source-drain doped region 140, so that the contact resistance between the plug and the source-drain doped region can also be effectively reduced. Therefore, the doping of the modulation ions is beneficial to improving the performance of the formed semiconductor structure.
The specific technical scheme of the annealing treatment is the same as that of the prior art, and the detailed description of the invention is omitted here.
After the connection layer 160 is formed, a conductive material is filled in the contact hole in which the connection layer 160 is formed to form a plug 170.
The plug 170 is used to electrically connect the source/drain doped region to an external circuit. The plug 170 is made of one or more materials selected from tungsten, aluminum, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum, and copper.
Referring to fig. 4, a cross-sectional structure diagram of an embodiment of a PMOS transistor of the present invention is shown.
The PMOS transistor includes:
a substrate 110; a gate structure 130, the gate structure 130 being located on the substrate 110; a first epitaxial layer 141, wherein the first epitaxial layer 141 is located on the substrate 110 at two sides of the gate structure 130; a second epitaxial layer 142, the second epitaxial layer 142 being on the first epitaxial layer 141, and the second epitaxial layer 142 being doped with modulation ions.
The substrate 110 is used to provide a process platform.
It should be noted that, in this embodiment, the substrate 110 includes a PMOS region 102 for forming a PMOS transistor. In addition, as shown in fig. 1, the substrate 110 further includes an NMOS region 101 for forming an NMOS transistor. Specifically, the PMOS region 102 and the NMOS region 101 are disposed adjacent to each other. However, in other embodiments of the present invention, the PMOS region and the NMOS region may not be disposed adjacently.
In this embodiment, the PMOS transistor is a fin field effect transistor, so the substrate 110 is further formed with a fin 120. Specifically, the fin portion 120 is formed on the substrate 110 of each of the PMOS region 102 and the NMOS region 101. In other embodiments of the present invention, the PMOS transistor may also be a planar transistor, and the substrate is a planar substrate.
In this embodiment, the substrate 110 is made of monocrystalline silicon. In other embodiments of the present invention, the substrate may also be a polysilicon substrate, an amorphous silicon substrate or a silicon germanium substrate, a carbon silicon substrate, a silicon on insulator substrate, a germanium on insulator substrate, a glass substrate or a III-V compound substrate, such as a gallium nitride substrate or a gallium arsenide substrate. The material of the substrate may be chosen to be suitable for the process requirements or to be easily integrated.
The fins 120 are used to provide channels for the transistors formed.
In this embodiment, the material of the fin 120 is the same as that of the substrate 110, and is also monocrystalline silicon. In other embodiments of the present invention, the material of the fin may be different from the material of the substrate, and may be selected from materials suitable for forming a fin, such as germanium, silicon carbon, or gallium arsenide.
In this embodiment, the PMOS transistor further includes: an isolation layer (not shown) is disposed on the substrate 110 between adjacent fins 120.
The isolation layer covers a portion of the sidewalls of the fins 120, and a top of the isolation layer is lower than a top of the fins 120. The isolation layer is used as an isolation layer of the semiconductor structure and can play a role in electrical isolation between adjacent devices and adjacent fin parts. The isolation layer is located on the substrate 110 where the fins 120 are exposed, and the height of the isolation layer is lower than the height of the fins 120.
In this embodiment, the isolation layer is made of silicon oxide. In other embodiments of the present invention, the material of the isolation layer may also be other insulating materials such as silicon nitride or silicon oxynitride.
The gate structure 130 is used to control the conduction and the cut-off of the channel of the formed semiconductor structure.
In this embodiment, the fin 120 is disposed on the substrate 110, so that the gate structure 130 crosses over the fin 120 and covers a portion of the top and a portion of the sidewall of the fin 120. In addition, the substrate 110 includes the NMOS region 101 and the PMOS region 102, so the gate structure 130 is formed on the NMOS region 101 and the PMOS region 102.
In this embodiment, the gate structure 130 is a polysilicon gate structure. The gate structure 130 includes a gate dielectric layer (not shown) on the substrate 110 and a gate electrode (not shown) on the gate dielectric layer. The gate dielectric layer is made of silicon oxide, and the gate electrode is made of polysilicon.
It should be noted that, in this embodiment, a sidewall (not labeled in the figure) is further disposed on the sidewall of the gate structure 130 to protect the gate structure and define the position of the subsequently formed source/drain doped region. In this embodiment, the sidewall is of a single-layer structure, and the material of the sidewall is silicon nitride. In other embodiments of the present invention, the material of the sidewall may also be silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride, and the sidewall may also be a stacked structure.
The first epitaxial layer 141 and the second epitaxial layer 142 are used for forming a source-drain doped region 140 of the formed PMOS transistor.
Because the second epitaxial layer 141 has the modulating ions therein, the modulating ions can effectively reduce the schottky barrier between the subsequently formed plug and the second epitaxial layer 141, thereby reducing the contact resistance between the subsequent plug and the drain doping region and being beneficial to improving the performance of the formed semiconductor structure.
In this embodiment, the modulating ions are Ni. In other embodiments of the present invention, the modulating ions may also be Al. The doping of Ni or Al can reduce the schottky barrier between the second epitaxial layer 142 and the plug to achieve the purpose of reducing the contact resistance.
Specifically, the doping concentration of the modulation ions in the second epitaxial layer 142 is 5E12atom/cm3To 5E14atom/cm3In the range, that is, the doping concentration of Ni in the second epitaxial layer 142 is 5E12atom/cm3To 5E14atom/cm3Within the range.
The doping concentration of the modulating ions should not be too high nor too low. If the doping concentration of the modulation ions is too low, the function of the modulation ions for reducing the schottky barrier between the subsequently formed plug and the source-drain doped region 140 may be affected, which is not beneficial to reducing the reduction of the contact resistance between the plug and the source-drain doped region 140; if the doping concentration of the modulation ions is too high, the probability of formation of a spike defect in the second epitaxial layer 142 may be increased, the performance of the source/drain doped region 140 formed by the first epitaxial layer 141 and the second epitaxial layer 142 may be affected, and the performance of the formed PMOS transistor may be affected.
It should be noted that the ratio of the second epitaxial layer 142 may affect the performance of the source/drain doped region 140, and thus the performance of the semiconductor structure. In this embodiment, the ratio of the thickness of the second epitaxial layer 140 to the thickness of the first epitaxial layer 140 is in the range of 8:1 to 12: 1.
The ratio of the thickness of the second epitaxial layer 140 to the thickness of the first epitaxial layer 140 is preferably neither too high nor too large.
If the ratio of the thickness of the second epitaxial layer 140 to the thickness of the first epitaxial layer 140 is too high, the ratio of the second epitaxial layer 140 in the source-drain doped region 140 is too high, and modulated ions in the second epitaxial layer 140 may cause metal ion pollution to the source-drain doped region 140, thereby causing performance degradation of the source-drain doped region 140; if the ratio of the thickness of the second epitaxial layer 140 to the thickness of the first epitaxial layer 140 is too low, the thickness of the second epitaxial layer 140 is too small, which may affect the function of reducing the schottky barrier between the plug formed in the following step and the source/drain doped region 140, and is not favorable for reducing the reduction of the contact resistance between the plug and the source/drain doped region 140.
Specifically, in this embodiment, the thickness of the second epitaxial layer 142 is in a range from 1nm to 10 nm.
In this embodiment, the second epitaxial layer 142 is further doped with a repair ion. The repair ions are used for inhibiting formation of Spike defects (Spike defects) in the second epitaxial layer 142, so that the quality of the second epitaxial layer 142 can be effectively improved, the probability of occurrence of the Spike discharge phenomenon is reduced, and the performance of the formed semiconductor structure is improved. Specifically, the repair ion is Pt.
Specifically, the doping concentration of the repair ions in the second epitaxial layer 142 is 5E12 atoms/cm3To 5E14atom/cm3Within the range.
The doping concentration of the repair ions is preferably neither too high nor too low. If the doping concentration of the repair ions is too low, the suppression effect of the repair ions on the spike defects may be affected, the spike defects in the formed second epitaxial layer 142 may be caused, and the probability of the spike discharge phenomenon in the formed semiconductor structure is increased, so that the stability and performance of the formed semiconductor structure are easily affected; if the doping concentration of the repair ions is too high, metal ion contamination may be caused to the source/drain doped region 140, and the performance of the source/drain doped region 140 and the performance of a connection layer formed subsequently may be affected, thereby easily causing degradation of the performance of the formed semiconductor structure.
Specifically, the material of the first epitaxial layer 141 is P-type doped Si or SiGe, wherein the doping ions may be B, Ga or In.
The PMOS transistor further includes:
a third epitaxial layer (not shown) located in the fin 120 on the NMOS region 101 at two sides of the gate structure 130; an interlayer dielectric layer 150, wherein the interlayer dielectric layer 150 is located in the source-drain doped region 140; the plug 170 is positioned on the source-drain doped region 140 and penetrates through the interlayer dielectric layer 150; and the connecting layer 160, wherein the connecting layer 160 is at least positioned between the plug 170 and the source-drain doped region 170.
And the third epitaxial layer is used for forming a source-drain doped region of the formed NMOS transistor. The material of the third epitaxial layer is N-type doped Si or SiC, wherein the doping ions can be P, As or Sb.
The interlevel dielectric layer 150 is used to achieve electrical isolation between adjacent semiconductor structures and between adjacent metal structures.
In this embodiment, the interlayer dielectric layer 150 is made of silicon oxide. In other embodiments of the present invention, the material of the interlayer dielectric layer may also be selected from other dielectric materials such as silicon nitride, silicon oxynitride, silicon oxycarbonitride, and the like.
Specifically, the substrate 110 further has the fin portions 120, isolation layers are filled between adjacent fin portions 120, and gate structures 130 are further formed on the fin portions 120. Therefore, the interlayer dielectric layer 150 is filled between the adjacent gate structures 130 and is located on the substrate 110, the fin 120, the isolation layer and the source/drain doped region 140, and the top of the interlayer dielectric layer 150 is higher than the top of the gate structure 130.
The plug 170 is used to electrically connect the source/drain doped region to an external circuit. The plug 170 is made of one or more materials selected from tungsten, aluminum, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum, and copper.
The connection layer 160 is used to reduce the schottky barrier height between the plug 170 and the source-drain doped region material on the PMOS region 102 and the NMOS region 101, and reduce the contact resistance.
For the NMOS transistor formed in the NMOS region 101, the material of the connection layer 160 is a silicon titanium compound, so that the schottky barrier between the plug and the source-drain doped region material can be effectively reduced, and the contact resistance between the plug and the source-drain doped region can be effectively reduced; for the PMOS transistor formed in the PMOS region 102, the material of the connection layer 160 is a silicon-titanium compound doped with a certain amount of modulation ions, and the doping of the modulation ions can effectively reduce the schottky barrier between the plug and the material of the source/drain doped region 140, so as to effectively reduce the contact resistance between the plug and the source/drain doped region. Therefore, the doping of the modulation ions is beneficial to improving the performance of the formed semiconductor structure.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (19)
1. A method for forming a PMOS transistor, comprising:
providing a substrate;
forming a gate structure on the substrate;
forming a first epitaxial layer and a second epitaxial layer on the first epitaxial layer on the substrate on two sides of the gate structure, wherein modulation ions are doped in the second epitaxial layer;
forming a metal precursor layer, wherein the metal precursor layer covers a part of the second epitaxial layer;
and carrying out annealing treatment, so that at least part of the thickness of the second epitaxial layer reacts with the metal precursor layer to form a connecting layer.
2. The method of claim 1, wherein the modulating ion is Ni or Al.
3. The method of forming of claim 1, wherein a ratio of the thickness of the second epitaxial layer to the thickness of the first epitaxial layer is in a range of 8:1 to 12: 1.
4. The forming method of claim 1 or 3, wherein a thickness of the second epitaxial layer is in a range of 1nm to 10 nm.
5. The method of forming of claim 1 wherein said second epitaxial layer has a dopant concentration of said modulation ions of 5E12 atoms/cm3To 5E14atom/cm3Within the range.
6. The forming method of claim 1 or 2, wherein the second epitaxial layer is further doped with a repair ion, and the repair ion is Pt.
7. The method of forming of claim 6 wherein said second epitaxial layer is doped with said repair ions at a concentration of 5E12 atoms/cm3To 5E14atom/cm3Within the range.
8. The method of forming of claim 1, wherein forming the first epitaxial layer and the second epitaxial layer comprises:
forming openings on the substrate on two sides of the grid structure;
filling a semiconductor material into the opening through a first epitaxial process to form a first epitaxial layer;
forming the second epitaxial layer on the first epitaxial layer by a second epitaxial process.
9. The method of forming of claim 8, wherein in-situ doping is performed during the second epitaxial process.
10. The forming method of claim 8 or 9, wherein the process gas used in the second epitaxial process comprises a first doping gas;
the modulating ions are Ni, and the first doping gas is Ni (MeC (NtBu)2)2；
The modulating ions are Al, and the first doping gas is (CH)3)2AlH。
11. The method of claim 10, wherein the process gas used in the second epitaxy process further comprises a second doping gas, wherein the second doping gas is mecppptme3。
12. The method of forming of claim 8, wherein the first epitaxial process and the second epitaxial process are performed in a same process chamber.
13. A PMOS transistor, comprising:
a substrate;
a gate structure located on the substrate;
the first epitaxial layer is positioned on the substrate at two sides of the grid structure;
the second epitaxial layer is positioned on the first epitaxial layer, and modulation ions are doped in the second epitaxial layer; the first epitaxial layer and the second epitaxial layer are used for forming a source-drain doped region;
the plug is positioned on the source drain doped region;
and the connecting layer is at least positioned between the plug and the source drain doped region.
14. The PMOS transistor of claim 13 wherein said modulating ions are nickel ions or aluminum ions.
15. The PMOS transistor of claim 13 wherein a ratio of the thickness of said second epitaxial layer to the thickness of said first epitaxial layer is in a range of 8:1 to 12: 1.
16. The PMOS transistor of claim 13 or 15 wherein the thickness of the second epitaxial layer is in the range of 1nm to 10 nm.
17. The PMOS transistor of claim 13 wherein the dopant concentration of the modulating ions in the second epitaxial layer is 5E12 atoms/cm3To 5E14atom/cm3Within the range.
18. The PMOS transistor of claim 13 wherein said second epitaxial layer is further doped with a repair ion, said repair ion being Pt.
19. The PMOS transistor of claim 18 wherein said second epitaxial layer has a doping concentration of said repair ions of 5E12 atoms/cm3To 5E14atom/cm3Within the range.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711390693.XA CN109950151B (en) | 2017-12-20 | 2017-12-20 | PMOS transistor and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711390693.XA CN109950151B (en) | 2017-12-20 | 2017-12-20 | PMOS transistor and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109950151A CN109950151A (en) | 2019-06-28 |
| CN109950151B true CN109950151B (en) | 2022-02-15 |
Family
ID=67005342
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711390693.XA Active CN109950151B (en) | 2017-12-20 | 2017-12-20 | PMOS transistor and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109950151B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1685520A (en) * | 2002-09-30 | 2005-10-19 | 先进微装置公司 | MOSFETs incorporating nickel germanosilicided gate and methods of their formation |
| CN101271838A (en) * | 2007-03-22 | 2008-09-24 | 中芯国际集成电路制造(上海)有限公司 | Light doping section forming method and mask used to forming light doping section |
| CN102544009A (en) * | 2010-12-08 | 2012-07-04 | 中国科学院微电子研究所 | High-mobility complementary metal oxide semiconductor (CMOS) integrated unit |
| CN103367363A (en) * | 2012-03-27 | 2013-10-23 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SE519382C2 (en) * | 2000-11-03 | 2003-02-25 | Ericsson Telefon Ab L M | Integration of self-oriented MOS high voltage components and semiconductor structure including such |
| TWI280674B (en) * | 2002-08-06 | 2007-05-01 | Vanguard Int Semiconduct Corp | High voltage device manufacturing process capable of matching low voltage device manufacturing process |
| GB2416210B (en) * | 2004-07-13 | 2008-02-20 | Christofer Toumazou | Ion sensitive field effect transistors |
| US7029967B2 (en) * | 2004-07-21 | 2006-04-18 | Texas Instruments Incorporated | Silicide method for CMOS integrated circuits |
| CN100539024C (en) * | 2006-06-23 | 2009-09-09 | 台湾积体电路制造股份有限公司 | The formation method of semiconductor device |
| KR101561059B1 (en) * | 2008-11-20 | 2015-10-16 | 삼성전자주식회사 | Semiconductor device and method of forming the same |
| TWI544623B (en) * | 2012-11-07 | 2016-08-01 | 聯華電子股份有限公司 | Epitaxial layer and method of forming the same |
-
2017
- 2017-12-20 CN CN201711390693.XA patent/CN109950151B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1685520A (en) * | 2002-09-30 | 2005-10-19 | 先进微装置公司 | MOSFETs incorporating nickel germanosilicided gate and methods of their formation |
| CN101271838A (en) * | 2007-03-22 | 2008-09-24 | 中芯国际集成电路制造(上海)有限公司 | Light doping section forming method and mask used to forming light doping section |
| CN102544009A (en) * | 2010-12-08 | 2012-07-04 | 中国科学院微电子研究所 | High-mobility complementary metal oxide semiconductor (CMOS) integrated unit |
| CN103367363A (en) * | 2012-03-27 | 2013-10-23 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109950151A (en) | 2019-06-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10340355B2 (en) | Method of forming a dual metal interconnect structure | |
| CN108257916B (en) | Semiconductor structure and forming method thereof | |
| US9991123B2 (en) | Doped protection layer for contact formation | |
| US10411114B2 (en) | Air gap spacer with wrap-around etch stop layer under gate spacer | |
| CN111092122A (en) | Method for forming semiconductor structure | |
| CN108695257B (en) | Semiconductor structure and forming method thereof | |
| KR20160003539A (en) | Contact structures and methods of forming the same | |
| CN109427678B (en) | Semiconductor structure and forming method thereof | |
| US9735231B2 (en) | Block layer in the metal gate of MOS devices | |
| US20150115335A1 (en) | Mechanism for forming metal gate structure | |
| US20100197089A1 (en) | Methods of fabricating semiconductor devices with metal-semiconductor compound source/drain contact regions | |
| CN108257917B (en) | Semiconductor structure and forming method thereof | |
| KR102249703B1 (en) | Finfet structure and method with reduced fin buckling | |
| CN108074815B (en) | Semiconductor structure and forming method thereof | |
| CN109216278B (en) | Semiconductor structure and forming method thereof | |
| US11393924B2 (en) | Structure and formation method of semiconductor device with high contact area | |
| CN109309056B (en) | Semiconductor structure and forming method thereof | |
| CN108573910B (en) | Semiconductor structure and forming method thereof | |
| US11616133B2 (en) | Fin field-effect transistor device and method | |
| US20220278199A1 (en) | Contact structure for semiconductor device and method | |
| CN109950151B (en) | PMOS transistor and forming method thereof | |
| CN107104051B (en) | Semiconductor element and manufacturing method thereof | |
| CN109671673B (en) | Semiconductor structure and forming method thereof | |
| TW202129772A (en) | Method of fabricating semiconductor structure | |
| CN108630683B (en) | Semiconductor structure and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |