CN108630683B

CN108630683B - Semiconductor structure and forming method thereof

Info

Publication number: CN108630683B
Application number: CN201710175999.7A
Authority: CN
Inventors: 李勇
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2017-03-22
Filing date: 2017-03-22
Publication date: 2021-03-09
Anticipated expiration: 2037-03-22
Also published as: CN108630683A

Abstract

A semiconductor structure and a method of forming the same, the method comprising: providing a substrate comprising an NMOS region; forming a gate structure on a substrate; forming N-region grooves in the substrate on two sides of the grid structure; forming an N-region doped epitaxial layer in the N-region groove, wherein the N-region doped epitaxial layer is of a laminated structure formed by a first N-type doped epitaxial layer and a second N-type doped epitaxial layer, the first N-type doped epitaxial layer is a first epitaxial layer doped with N-type ions, the second N-type doped epitaxial layer is a second epitaxial layer doped with the N-type ions, and the forbidden bandwidth of the second epitaxial layer is smaller than that of the first epitaxial layer; forming an interlayer dielectric layer on the N region doped epitaxial layer; forming a first contact opening exposing the N region doped epitaxial layer in the interlayer dielectric layer; a first contact hole plug is formed within the first contact opening. According to the invention, the Schottky barrier height is reduced through the second epitaxial layer doped with N-type ions, and the N-type ion concentration of the N-region doped epitaxial layer is increased, so that the contact resistance is reduced.

Description

Semiconductor structure and forming method thereof

Technical Field

The present invention relates to the field of semiconductors, and more particularly, to a semiconductor structure and a method for forming the same.

Background

With the continuous development of integrated circuit manufacturing technology, the requirements for the integration level and performance of integrated circuits become higher and higher. In order to improve the integration level and reduce the cost, the critical dimensions of the devices are becoming smaller, and the circuit density inside the integrated circuits is becoming higher, which makes the wafer surface unable to provide enough area to make the required interconnection lines.

In order to meet the requirement of the interconnection line after the critical dimension is reduced, the conduction of different metal layers or metal layers and the substrate is realized by an interconnection structure at present. The interconnect structure includes an interconnect line and a contact hole plug formed within the contact opening. The contact hole plugs are connected with the semiconductor device, and the interconnection lines realize connection between the contact hole plugs, thereby forming a circuit.

The contact hole plug in the transistor structure comprises a contact hole plug positioned on the surface of the gate structure and used for realizing the connection between the gate structure and an external circuit; and the contact hole plug is positioned on the surface of the source-drain doped region and used for realizing the connection between the source region or the drain region of the transistor and an external circuit.

Due to the fact that the key size of the device is continuously reduced, the area of a contact region between the contact hole plug and the source-drain doped region is also continuously reduced, and the reduction of the area of the contact region correspondingly causes the increase of contact resistance, so that the driving current of the device is reduced, and the performance of the semiconductor device is degraded. Therefore, in order to reduce the contact resistance and increase the driving current, the following methods are mainly adopted: and forming a metal silicide layer on the surface of the substrate corresponding to the position where the contact hole plug is to be formed so as to reduce the contact resistance of the contact region.

However, after the metal silicide layer technology is adopted, the electrical performance of the formed semiconductor structure is still to be improved.

Disclosure of Invention

The invention provides a semiconductor structure and a forming method thereof, which can improve the electrical property of the semiconductor structure.

To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises an NMOS region for forming an N-type device; forming a gate structure on the substrate; forming N-region grooves in the substrate at two sides of the NMOS region gate structure; forming an N-region doped epitaxial layer in the N-region groove, wherein the N-region doped epitaxial layer is a laminated structure formed by a first N-type doped epitaxial layer and a second N-type doped epitaxial layer, the first N-type doped epitaxial layer is a first epitaxial layer doped with N-type ions, the second N-type doped epitaxial layer is a second epitaxial layer doped with N-type ions, and the forbidden bandwidth of the second epitaxial layer is smaller than that of the first epitaxial layer; forming an interlayer dielectric layer on the N region doped epitaxial layer; forming a first contact opening exposing the N region doped epitaxial layer in the interlayer dielectric layer of the NMOS region; and forming a first contact hole plug electrically connected with the N-region doped epitaxial layer in the first contact opening.

Accordingly, the present invention also provides a semiconductor structure comprising: a substrate comprising an NMOS region with an N-type device; the grid structure is positioned on the substrate; the N-region doped epitaxial layer is positioned in the substrate on two sides of the NMOS region gate structure and is a laminated structure formed by a first N-type doped epitaxial layer and a second N-type doped epitaxial layer, wherein the first N-type doped epitaxial layer is a first epitaxial layer doped with N-type ions, the second N-type doped epitaxial layer is a second epitaxial layer doped with N-type ions, and the forbidden bandwidth of the second epitaxial layer is smaller than that of the first epitaxial layer; the interlayer dielectric layer is positioned on the N region doped epitaxial layer; and the first contact hole plug penetrates through the interlayer dielectric layer of the NMOS region and is electrically connected with the N region doped epitaxial layer.

Compared with the prior art, the technical scheme of the invention has the following advantages:

the invention provides a method for forming a semiconductor structure, which comprises the following steps: forming N-region grooves in the substrate at two sides of the NMOS region gate structure; and forming an N-region doped epitaxial layer in the N-region groove, wherein the N-region doped epitaxial layer is a laminated structure formed by a first N-type doped epitaxial layer and a second N-type doped epitaxial layer, the first N-type doped epitaxial layer is a first epitaxial layer doped with N-type ions, the second N-type doped epitaxial layer is a second epitaxial layer doped with N-type ions, and the forbidden bandwidth of the second epitaxial layer is smaller than that of the first epitaxial layer. Compared with the scheme that the formed N-region doped epitaxial layer only comprises the first epitaxial layer doped with N-type ions, the second epitaxial layer has smaller forbidden bandwidth, so that the Schottky Barrier Height (SBH) of the N-region doped epitaxial layer and the channel region is favorably reduced through the second epitaxial layer; in addition, the doping ions of the second N-type doping epitaxial layer are N-type ions, so that the concentration of the N-type ions in the N-region doping epitaxial layer is improved; since the contact resistance is proportional to the schottky barrier height and inversely proportional to the N-type ion concentration, the scheme of the invention can reduce the contact resistance to improve the driving current of the formed N-type device, thereby improving the electrical performance of the semiconductor structure.

In an alternative, the step of forming the N region doped epitaxial layer includes: forming a first epitaxial layer in the N-region groove; doping N-type ions into the first epitaxial layer to form a first N-type doped epitaxial layer; forming a second epitaxial layer on the first N-type doped epitaxial layer; doping N-type ions into the second epitaxial layer to form a second N-type doped epitaxial layer; the second N-type doped epitaxial layer and the first N-type doped epitaxial layer form an N-region doped epitaxial layer. The second epitaxial layer is made of SiGe, the P region doped epitaxial layer is made of SiGe doped with P-type ions, and in the step of forming a first contact opening exposing the N region doped epitaxial layer in the interlayer dielectric layer of the NMOS region, the first contact opening is formed in the interlayer dielectric layer of the PMOS region and exposes the P region doped epitaxial layer, the first contact opening of the NMOS region exposes the second epitaxial layer, the first contact opening of the NMOS region and the first contact opening of the PMOS region are exposed from the same material and are both SiGe, so that the forming process of the first contact opening and the forming process of the subsequent first contact hole plug are optimized.

The invention provides a semiconductor structure which comprises N-region doped epitaxial layers positioned in substrates on two sides of a gate structure of an NMOS region, wherein the N-region doped epitaxial layers are of a laminated structure formed by a first N-type doped epitaxial layer and a second N-type doped epitaxial layer, the first N-type doped epitaxial layer is a first epitaxial layer doped with N-type ions, the second N-type doped epitaxial layer is a second epitaxial layer doped with N-type ions, and the forbidden bandwidth of the second epitaxial layer is smaller than that of the first epitaxial layer. Compared with the scheme that the N region doped epitaxial layer only comprises the first epitaxial layer doped with N-type ions, the Schottky barrier height of the N region doped epitaxial layer and the channel region can be reduced through the second epitaxial layer due to the fact that the forbidden bandwidth of the second epitaxial layer is small; in addition, the doping ions of the second N-type doping epitaxial layer are N-type ions, so that the concentration of the N-type ions in the N-region doping epitaxial layer is improved; because the contact resistance is in direct proportion to the height of the Schottky barrier and in inverse proportion to the concentration of the N-type ions, the contact resistance of the semiconductor structure is smaller, the driving current of an N-type device is correspondingly improved, and the electrical performance of the semiconductor structure is improved.

Drawings

FIGS. 1-29 are schematic structural diagrams corresponding to steps of a method of forming a semiconductor structure according to an embodiment of the present invention;

fig. 30 to 32 are schematic structural views of a semiconductor structure according to an embodiment of the invention.

Detailed Description

Parasitic external resistance (Rext) is an important factor affecting the electrical performance of a semiconductor structure; therefore, in order to reduce the contact resistance to increase the driving current, a metal silicide layer is formed on the surface of the substrate corresponding to the position where the contact hole plug is to be formed to reduce the contact resistance of the contact region.

However, even after the metal silicide layer technology is adopted, the electrical performance of the formed semiconductor structure is still to be improved.

In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps: forming N-region grooves in the substrate at two sides of the NMOS region gate structure; and forming an N-region doped epitaxial layer in the N-region groove, wherein the N-region doped epitaxial layer is a laminated structure formed by a first N-type doped epitaxial layer and a second N-type doped epitaxial layer, the first N-type doped epitaxial layer is a first epitaxial layer doped with N-type ions, the second N-type doped epitaxial layer is a second epitaxial layer doped with N-type ions, and the forbidden bandwidth of the second epitaxial layer is smaller than that of the first epitaxial layer. Compared with the scheme that the formed N region doped epitaxial layer only comprises the first epitaxial layer doped with N-type ions, the forbidden bandwidth of the second epitaxial layer is smaller, so that the Schottky barrier height of the N region doped epitaxial layer and the channel region can be reduced through the second epitaxial layer; in addition, the doping ions of the second N-type doping epitaxial layer are N-type ions, so that the concentration of the N-type ions in the N-region doping epitaxial layer is improved; since the contact resistance is proportional to the schottky barrier height and inversely proportional to the N-type ion concentration, the scheme of the invention can reduce the contact resistance to improve the driving current of the formed N-type device, thereby improving the electrical performance of the semiconductor structure.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 1 to 29 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Referring to fig. 1 and 2 in combination, fig. 1 is a perspective view (only two fins are shown), and fig. 2 is a cross-sectional view of fig. 1 taken along a cut line AA1, providing a substrate (not labeled) including an NMOS region II (shown in fig. 2) for forming an N-type device.

The substrate provides a process platform for the subsequent formation of a semiconductor structure.

In this embodiment, the base is used for forming a finfet, and thus, in the step of providing the base, the base includes a substrate 100 and a discrete fin (not shown) located on the substrate 100. In other embodiments, the base is used to form a planar transistor, and accordingly, the base is a planar substrate.

The substrate 100 provides a platform for subsequent formation of semiconductor structures, and the fins provide channels for the resulting finfets.

In this embodiment, taking the formed finfet as a CMOS device as an example, the substrate 100 includes not only an NMOS region II for forming an N-type device, but also a PMOS region I (as shown in fig. 2) for forming a P-type device, and the substrate 100 of the PMOS region I and the NMOS region II both have discrete fins. Specifically, the fin on the PMOS region I substrate 100 is a first fin 110, and the fin on the NMOS region II substrate 100 is a second fin 120.

In other embodiments, where the finfet formed may include only NMOS devices, the substrate may include only NMOS regions accordingly.

In this embodiment, the PMOS region I and the NMOS region II are adjacent regions. In other embodiments, the PMOS region and NMOS region may also be isolated.

In order to improve the carrier mobility of the formed semiconductor device, the substrate is a germanium-containing substrate. In this embodiment, the germanium-containing base is a germanium base, and correspondingly, the substrate 100 is made of germanium. In other embodiments, the material of the germanium-containing substrate can also be silicon germanium, and the germanium-containing substrate can also be a germanium-on-insulator substrate. The material of the substrate may be chosen to suit the process requirements or to facilitate integration.

In other embodiments, the material of the substrate may also be single crystal silicon, a polycrystalline silicon substrate, an amorphous silicon substrate or a silicon germanium substrate, a carbon silicon substrate, a silicon on insulator substrate, a germanium on insulator substrate, a glass substrate or a III-V compound substrate, such as a gallium nitride substrate or a gallium arsenide substrate; the material of the substrate may be chosen to be suitable for process requirements or easy to integrate.

The material of the fin is the same as the material of the substrate 100. Therefore, in the present embodiment, the material of the fin portion is germanium, that is, the material of the first fin portion 110 and the second fin portion 120 is germanium.

Specifically, the steps of forming the substrate 100 and the fin portion include: providing an initial substrate; forming a fin hard mask layer 200 on the surface of the initial substrate; and etching the initial substrate by taking the fin part hard mask layer 200 as a mask to form the substrate 100 and a fin part protruding out of the surface of the substrate 100.

In this embodiment, after the substrate 100 and the fin portion are formed, the fin portion hard mask layer 200 on the top of the fin portion is remained. The fin portion hard mask layer 200 is made of silicon nitride, and when a planarization process is performed subsequently, the top surface of the fin portion hard mask layer 200 is used for defining a stop position of the planarization process and plays a role in protecting the top of the fin portion.

Referring to fig. 3 in combination, it should be noted that after the substrate 100 and the fin portion (not labeled) are formed, the forming method further includes: and forming an isolation structure 101 on the substrate 100 with the exposed fin portion, wherein the isolation structure 101 covers part of the side wall of the fin portion, and the top of the isolation structure 101 is lower than the top of the fin portion.

The isolation structure 101 serves as an isolation structure of a semiconductor device and is used for isolating adjacent devices or adjacent fins. In this embodiment, the isolation structure 101 is made of silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride.

Specifically, the step of forming the isolation structure 101 includes: forming an isolation film on the substrate 100 with the exposed fin portion, wherein the top of the isolation film is higher than the top of the fin portion hard mask layer 200 (shown in fig. 2); grinding to remove the isolation film higher than the top of the fin hard mask layer 200; etching back the remaining isolation film with partial thickness to form an isolation structure 101; the fin hard mask layer 200 is removed.

Referring to fig. 4 and 5 in combination, fig. 4 is a perspective view (only two fins are shown), and fig. 5 is a cross-sectional view taken along a line DD1 of fig. 4, wherein a gate structure 102 is formed on the substrate.

In this embodiment, a process of forming a gate electrode layer (high-k metal gate last) after forming a high-k gate dielectric layer is adopted, so that the gate structure 102 is a dummy gate structure (dummy gate), and the gate structure 102 occupies a spatial position for subsequently forming a metal gate structure.

In other embodiments, a process of forming a high-k gate dielectric layer and forming a gate electrode layer (high-k first gate first) may also be adopted; correspondingly, the gate structure may also be a metal gate structure (metal gate).

The base includes a substrate 100 and a discrete fin (not labeled) on the substrate 100, so in the step of forming the gate structure 102 on the base, the gate structure 102 crosses over the fin and covers a portion of the top surface and the sidewall surface of the fin.

Specifically, the gate structure 102 of the PMOS region I crosses over the first fin 110, and covers a portion of the top surface and the sidewall surface of the first fin 110; the gate structure 102 of the NMOS region II crosses over the second fin 120 and covers a portion of the top surface and sidewall surfaces of the second fin 120.

The gate structure 102 is a single-layer structure or a stacked structure. The gate structure 102 includes a dummy gate layer; or the gate structure 102 includes a dummy oxide layer and a dummy gate layer on the dummy oxide layer. The pseudo gate layer is made of polycrystalline silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride or amorphous carbon, and the pseudo oxide layer is made of silicon oxide or silicon oxynitride.

Specifically, the step of forming the gate structure 102 includes: forming a dummy gate film on the isolation structure 101, wherein the dummy gate film crosses the fin portion and covers the top surface and the side wall surface of the fin portion; forming a gate hard mask layer 210 on the surface of the pseudo gate film, wherein the gate hard mask layer 210 defines a pattern of a gate structure 102 to be formed; and patterning the pseudo gate film by taking the gate hard mask layer 210 as a mask to form a gate structure 102.

It should be noted that after the gate structure 102 is formed, the gate hard mask layer 210 on the top of the gate structure 102 is remained. In this embodiment, the gate hard mask layer 210 is made of silicon nitride, and the gate hard mask layer 210 is used for protecting the top of the gate structure 102 in a subsequent process.

The following steps comprise: forming N-region grooves in the substrate on two sides of the NMOS region II gate structure 102; and forming an N region doped epitaxial layer in the N region groove.

It should be noted that the substrate 100 further includes a PMOS region I for forming a P-type device, and therefore the forming method further includes: forming P-region grooves in the substrate on two sides of the PMOS region I gate structure 102; and forming a P region doped epitaxial layer in the P region groove.

In this embodiment, the P region doped epitaxial layer is formed first, and then the N region doped epitaxial layer is formed.

Referring to fig. 6 and 7 in combination, fig. 6 is a schematic cross-sectional view based on fig. 5, and fig. 7 is a schematic cross-sectional view based on fig. 5 taken along a line perpendicular to the fin extension direction at the fin location (as indicated by EE1 in fig. 4), forming a P-region mask layer 310 on the sidewalls and top of the first fin 110.

The process of forming the P-region mask layer 310 may be a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process. In this embodiment, the P-region mask layer 310 is formed by an atomic layer deposition process. The P-region mask layer 310 is further located on the top and the sidewall of the second fin portion 120, and the P-region mask layer 310 is further located on the top and the sidewall of the gate structure 102 in the PMOS region I and the NMOS region II, and is further located on the isolation structure 101.

The P-region mask layer 310 functions include: the P-region mask layer 310 on the fin sidewalls plays a role in protecting the fin sidewalls, so as to avoid performing a subsequent epitaxial growth process on the sidewalls of the first fin 110 and the second fin 120; in addition, the P-region mask layer 310 in the NMOS region II is subsequently used as a part of the N-region mask layer in the NMOS region II.

The P-region mask layer 310 may be made of silicon nitride, silicon oxide, boron nitride, or silicon oxynitride. The material of the P-region mask layer 310 is different from the material of the fin portion, and the material of the P-region mask layer 310 is different from the material of the isolation structure 101. In this embodiment, the P-region mask layer 310 is made of silicon nitride.

Referring to fig. 8 and 9 in combination, fig. 8 is a schematic cross-sectional view based on fig. 7, and fig. 9 is a schematic cross-sectional view taken along a line cut along the extending direction of the first fin portion (e.g., a line cut along BB1 in fig. 1), wherein P-region initial recesses 111 are formed in the substrate at two sides of the PMOS region I-gate structure 102.

The P-region initial groove 111 provides a process basis for the subsequent formation of a P-region groove.

Specifically, the P-region mask layer 310 on the top of the first fin portion 110 on both sides of the PMOS region I-gate structure 102 is etched by using an anisotropic etching process, wherein the P-region mask layer 310 on the top of the PMOS region I-gate structure 102 and on the isolation structure 101 is also etched in the process of etching the P-region mask layer 310 on the top of the first fin portion 110 on both sides of the PMOS region I-gate structure 102; after the tops of the first fins 110 on the two sides of the PMOS region I-gate structure 102 are exposed, the first fins 110 with a partial thickness are continuously etched, and a P-region initial groove 111 is formed in the first fins 110.

In this embodiment, the subsequent steps further include etching the sidewalls and the bottom of the P-region initial groove 111 to form a P-region groove, so that in the step of etching the first fin 110 with the thickness at two sides of the PMOS region I-gate structure 102, in order to make the depth and the opening size of the P-region groove meet the process requirements, the removal amount of the first fin 110 is 10nm to 60nm, and correspondingly, the depth of the P-region initial groove 111 is 10nm to 60 nm.

It should be noted that, before etching the P-region mask layer 310 on the tops of the first fins 110 on both sides of the PMOS region I-gate structure 102, the forming method further includes: a first pattern layer 220 is formed on the NMOS area II (as shown in fig. 8), and the first pattern layer 220 covers the P-region mask layer 310 of the NMOS area II.

The first pattern layer 220 plays a role in protecting the P-region mask layer 310 on the NMOS region II, and the first pattern layer 220 may also cover an area not desired to be etched in the PMOS region I.

In this embodiment, the first pattern layer 220 is made of a photoresist material. After the P-region initial groove 111 is formed, the first pattern layer 220 is remained, and the first pattern layer 220 is used as an etching mask of a subsequent etching process.

It should be further noted that, in order to increase the volume of the P-region doped epitaxial layer formed in the P-region groove subsequently, the P-region mask layer 310 on the sidewall of the first fin 110 is etched while the first fin 110 is etched, so that after the P-region initial groove 111 is formed, the P-region mask layer 310 on the sidewall of the first fin 110 is flush with the top of the first fin 110.

Referring to fig. 10 and 11 in combination, fig. 10 is a schematic cross-sectional structure based on fig. 8, fig. 11 is a schematic cross-sectional structure based on fig. 9, and a mixed etching gas is used to etch the sidewalls and the bottom of the P-region initial groove 111 (shown in fig. 9) to form a P-region groove 112; the mixed etching gas includes a silicon source gas and an HCl gas.

The P-region recess 112 provides a spatial location for the subsequent formation of a P-region doped epitaxial layer.

It should be noted that, in the etching process for forming the P-region initial groove 111, the first fin 110 material on the sidewall and the bottom of the P-region initial groove 111 is subjected to ion bombardment, which easily causes the first fin 110 material with a partial thickness to be damaged and have defects (e.g., Ge atoms deviating from lattice positions), so that in order to improve the formation quality of the subsequent P-type doped epitaxial layer, the sidewall and the bottom of the P-region initial groove 111 are etched by using a mixed etching gas of a silicon source gas and an HCl gas, so that the damaged first fin 110 material is removed, and the first fin 110 is less damaged by the etching process, so that the first fin 110 material exposed by the P-region groove 112 has better quality, and the formation quality of the subsequent P-type doped epitaxial layer can be improved.

Specifically, the step of forming the P region groove 112 includes: providing a mixed gas of the silicon source gas and the HCl gas; the silicon source gas reacts with the first fin portion 110 exposed by the P region initial groove 111 to form a Ge-Si bond; the HCl gas removes the Ge-Si bonds to remove a portion of the thickness of the first fin 110 material.

In this embodiment, the silicon source gas is SiH₄The process temperature for forming the P-region groove 112 is 400 to 700 ℃. In other embodiments, the silicon source gas may also be Si₂Cl₂Or SiHCl₃。

In this example, SiH₄For reaction with the first fin 110 to form a Ge-Si bond, HCl for removing the Ge-Si bond to remove a portion of the thickness of the first fin 110 material, hence SiH₄And the gas flow rate of HCl both affect the amount of removal of the first fin 110. To avoid excessive loss of the first fin 110 while completely removing the defective first fin 110 material, the SiH may be added to the first fin 110₄The gas flow of HCl and HCl are controlled in a reasonable range and matched reasonably.

Note that SiH₄The gas flow rate should not be too low or too high. If SiH is present₄Too little gas flow may result in too few Ge-Si bonds being formed to react with the exposed first fins 110, which may lead to the exposed first fins 110The removal amount is too small to completely remove the defective first fin 110 material; on the contrary, if SiH₄The excessive flow of gas may result in excessive amounts of SiH and the material of the first fin 110₄Reactions occur which can adversely affect the electrical properties of the semiconductor device formed. For this purpose, SiH in this example₄The gas flow rate of (2) is 10sccm to 1000 sccm.

It should be noted that the flow rate of HCl gas should not be too low, nor too high. If the gas flow rate of HCl is too low, the effect of removing the Ge — Si bond is relatively poor, thereby making it difficult to completely remove the first fin 110 material having defects; on the contrary, if the gas flow of HCl is too high, damage to the remaining first fins 110 is easily caused, and the process risk is increased. Therefore, in the present embodiment, the flow rate of HCl gas is 5sccm to 100 sccm.

The amount of removal of the first fins 110 exposed by the P-region initial recess 111 depends on the actual process. If the removal amount is too small, the quality of the material of the first fin 110 exposed by the formed P-region recess 112 is relatively poor; if the removal amount is too large, the material of the first fin 110 corresponding to the channel region of the formed semiconductor device is adversely affected, and even the P-region mask layer 310 on the sidewall of the PMOS region I-gate structure 102 is likely to collapse. In this embodiment, after the sidewalls and the bottom of the P-region initial groove 111 are etched, the removal amount of the first fin 110 exposed by the P-region initial groove 111 is 1nm to 2 nm.

In this embodiment, after the P-region groove 112 is formed, a wet photoresist removal or ashing process is used to remove the first pattern layer 220.

Referring to fig. 12 and 13 in combination, fig. 12 is a schematic cross-sectional view based on fig. 10, and fig. 13 is a schematic cross-sectional view based on fig. 11, wherein a P-doped epitaxial layer 131 is formed in the P-region recess 112 (shown in fig. 11).

The P region doped epitaxial layer 131 is used as a source region or a drain region of a subsequently formed P-type device.

In this embodiment, a selective epitaxy process is adopted to form a P-type semiconductor layer (not shown) in the P-region groove 112, and during the process of forming the P-type semiconductor layer, P-type ions are self-doped in situ to form the P-region doped epitaxial layer 131. The P-type semiconductor layer provides a pressure stress effect for the channel region of the PMOS region I, so that the carrier mobility of the formed P-type device is improved.

It should be noted that the higher the doping concentration of the P-type ions in the P-region doped epitaxial layer 131 is, the more obvious the pressure stress providing effect is correspondingly played; however, the higher the doping concentration of the P-type ions, the larger the contact resistance.

Therefore, in this embodiment, in order to ensure that the compressive stress is provided and the contact resistance is reduced, the step of forming the P-doped epitaxial layer 131 in the P-region groove 112 includes: forming a first semiconductor layer (not shown) on the bottom and sidewalls of the P-region groove 112, and in the step of forming the first semiconductor layer, in-situ self-doping P-type ions to form a first P-type doped epitaxial layer (not shown); a second semiconductor layer (not shown) is formed on the first P-type doped epitaxial layer, and P-type ions are self-doped in situ in the step of forming the second semiconductor layer to form a second P-type doped epitaxial layer (not shown), wherein the concentration of the doped ions of the second P-type doped epitaxial layer is less than that of the doped ions of the first P-type doped epitaxial layer. Wherein the second P-type doped epitaxial layer and the first P-type doped epitaxial layer form the P-region doped epitaxial layer 131.

Specifically, the first semiconductor layer and the second semiconductor layer are both made of SiGe, and the P-type ions are B ions, so that the first P-type doped epitaxial layer is made of SiGe doped with B ions, and the second P-type doped epitaxial layer is made of SiGe doped with B ions.

The doping concentrations of the first P-type doped epitaxial layer and the second P-type doped epitaxial layer are determined according to actual process requirements. In this embodiment, the first P-type doped epitaxial layer has a Ge content of 30 to 60 atomic%, and a B ion doping concentration of 1.4E21atom/cm³To 2.6E21atom/cm³(ii) a The first P-type doped epitaxial layer contains 10 to 20 atomic percent of Ge and B ionsHas a doping concentration of 1.4E20atom/cm³To 2.6E20atom/cm³. And the ratio of the thickness of the first semiconductor layer to the thickness of the second semiconductor layer is 1:15 to 1: 5. Wherein, the content of Ge in atomic percent refers to the percentage of the total atomic number of Ge in the total atomic number of Si and Ge.

It should be noted that, in order to avoid process damage to the surface of the P-region doped epitaxial layer 131 caused by the subsequent process, after the P-region doped epitaxial layer 131 is formed, the method further includes: performing oxidation treatment on the surface of the P-region doped epitaxial layer 131, and forming an oxidation protection layer (not shown) on the surface of the P-region doped epitaxial layer 131; the oxidation treatment may be dry oxygen oxidation, wet oxygen oxidation or steam oxidation.

Referring to fig. 14 to 18 in combination, fig. 14 is a schematic cross-sectional view based on fig. 12, wherein N-region recesses 122 are formed in the substrate at two sides of the NMOS region II gate structure 102 (as shown in fig. 18).

The N-region recess 122 provides a spatial location for the subsequent formation of an N-region doped epitaxial layer.

The step of forming the N-region recess 122 is described in detail below with reference to the accompanying drawings.

Referring to fig. 14, an N-region mask layer 330 is formed on the top and sidewalls of the second fin 120.

Specifically, after the P-region doped epitaxial layer 131 is formed, N-region mask spacers 320 are formed on the P-region mask layer 310 of the NMOS region II, and the P-region mask layer 310 and the N-region mask spacers 320 located in the NMOS region II are used as the N-region mask layer 330. Correspondingly, the N-region mask layer 330 is also located on the top and the sidewall of the NMOS region II gate structure 102, and is also located on the isolation structure 101 of the NMOS region II.

In this embodiment, the N-region mask sidewall spacers 320 are further located on the P-type doped epitaxial layer 131 and the isolation structure 101 of the PMOS region I, and are further located on the sidewall and the top of the gate structure 102 of the PMOS region I.

The materials and the formation process of the N-region mask sidewall spacers 320 may refer to the description of the P-region mask layer 310, which is not repeated herein.

The N-region mask spacer 320 has the following functions: on one hand, the N-region mask sidewall 320 and the P-region mask layer 310 form an N-region mask layer 330 of a stacked structure, and when the second fin portion 120 with the thickness of the two sides of the NMOS region II gate structure 102 is subsequently etched, the N-region mask layer 330 is used as a mask, so that the distance between the subsequently formed N-region groove 122 and an NMOS channel region can be increased, and a short channel effect can be improved.

Referring to fig. 15 and 16 in combination, fig. 15 is a schematic cross-sectional view based on fig. 14, and fig. 16 is a schematic cross-sectional view taken along a line cut along the extending direction of the second fin portion (e.g., a line cut CC1 in fig. 1), wherein N-region initial recesses 121 are formed in the substrate at both sides of the NMOS region II gate structure 102.

The N-region initial groove 121 provides a process basis for the subsequent formation of an N-region groove.

Specifically, the N-region mask layer 330 on the tops of the second fins 120 on both sides of the NMOS region II gate structure 102 is etched by using an anisotropic etching process, wherein the N-region mask layer 330 on the top of the NMOS region II gate structure 102 and on the isolation structure 101 is also etched in the process of etching the N-region mask layer 330 on the tops of the second fins 120 on both sides of the NMOS region II gate structure 102; after the tops of the second fins 120 on the two sides of the NMOS region II gate structure 102 are exposed, the second fins 120 with a partial thickness are continuously etched, and an N-region initial groove 121 is formed in the second fins 120.

In this embodiment, in the step of etching the second fin portion 120 with the thickness of the two sides of the NMOS region II gate structure 102, the removal amount of the second fin portion 120 is 10nm to 60nm, and correspondingly, the depth of the N-region initial groove 121 is 10nm to 60 nm.

For the detailed process and parameter description of forming the N-region initial groove 121, reference is made to the corresponding description of forming the P-region initial groove 111 (as shown in fig. 9), which is not repeated herein.

It should be noted that, before the etching of the N-region mask layer 330 on the tops of the second fins 120 on both sides of the NMOS region II gate structure 102, the forming method further includes: forming a second pattern layer 230 on the PMOS region I (as shown in fig. 15), wherein the second pattern layer 230 covers the P-type doped epitaxial layer 131, and the second pattern layer 230 also covers the gate structure 102 of the PMOS region I.

Specifically, the second pattern layer 230 is formed on the N-region mask sidewall 320 of the PMOS region I, the second pattern layer 230 may play a role in protecting the PMOS region I, and the second pattern layer 230 may also cover an area that is not desired to be etched in the NMOS region II.

In this embodiment, the second pattern layer 230 is made of a photoresist material. After the N-region initial groove 121 is formed, the second pattern layer 230 is remained, and the second pattern layer 230 is used as an etching mask of a subsequent etching process.

It should be further noted that, in order to increase the volume of the N region doped epitaxial layer formed in the N region groove 122 subsequently, the N region mask layer 330 on the sidewall of the second fin 120 is etched while the second fin 120 is etched, so that after the N region initial groove 121 is formed, the N region mask layer 330 on the sidewall of the second fin 120 is flush with the top of the second fin 120.

Referring to fig. 17 and 18 in combination, fig. 17 is a schematic cross-sectional structure based on fig. 15, fig. 18 is a schematic cross-sectional structure based on fig. 16, and a mixed etching gas is used to etch the sidewalls and the bottom of the N-region initial groove 121 (shown in fig. 16) to form an N-region groove 122; the mixed etching gas includes a silicon source gas and an HCl gas.

It should be noted that, in the etching process for forming the N-region initial groove 121, the second fin 120 material on the sidewall and the bottom of the N-region initial groove 121 is subjected to ion bombardment, which easily causes the second fin 120 material with a partial thickness to be damaged and have defects (e.g., Ge atoms deviating from lattice positions), so that in order to improve the formation quality of the subsequent N-type doped epitaxial layer, the sidewall and the bottom of the N-region initial groove 121 are etched by using a mixed etching gas of a silicon source gas and an HCl gas, so that the damaged second fin 120 material is removed and the second fin 120 is less damaged, and thus the quality of the second fin 120 material exposed by the formed N-region groove 122 is better, and the formation quality of the subsequent N-type doped epitaxial layer can be improved.

In this embodiment, in the step of forming the N-region recess 122, the silicon source gas is SiH₄，SiH₄The gas flow rate of the gas is 10sccm to 1000sccm, the gas flow rate of the HCl is 5sccm to 100sccm, and the process temperature is 400 ℃ to 700 ℃. In other embodiments, the silicon source gas may also be Si₂Cl₂Or SiHCl₃。

In this embodiment, after the sidewalls and the bottom of the N-region initial groove 121 are etched, the removal amount of the second fin 110 exposed by the N-region initial groove 121 is 1nm to 2 nm.

For a detailed description of the process and parameters for forming the N-region groove 122, reference is made to the corresponding description of the process for forming the P-region groove 112 (as shown in fig. 11), which is not repeated herein.

In this embodiment, after the N-region recess 122 is formed, a wet photoresist removal or ashing process is used to remove the second pattern layer 230.

With reference to fig. 19 and 20, fig. 19 is a schematic cross-sectional structure view based on fig. 17, and fig. 20 is a schematic cross-sectional structure view based on fig. 18, an N-region doped epitaxial layer 231 is formed in the N-region recess 122 (as shown in fig. 18), the N-region doped epitaxial layer 231 is a stacked structure formed by a first N-type doped epitaxial layer 235 and a second N-type doped epitaxial layer 236, wherein the first N-type doped epitaxial layer 235 is a first epitaxial layer doped with N-type ions, the second N-type doped epitaxial layer 236 is a second epitaxial layer doped with N-type ions, and a forbidden bandwidth of the second epitaxial layer is smaller than a forbidden bandwidth of the first epitaxial layer.

The N region doped epitaxial layer 231 is used as a source region or a drain region of a subsequently formed N-type device.

The second epitaxial layer has a smaller forbidden bandwidth, so that the schottky barrier height of the N region doped epitaxial layer 231 and the channel region is reduced beneficially through the second epitaxial layer; and the doping ions of the second N-type doping epitaxial layer 236 are N-type ions, so that the concentration of the N-type ions in the N-region doping epitaxial layer 231 is increased. After a contact hole plug electrically connected to the N-doped epitaxial layer 231 is formed, the contact resistance of the contact hole plug contact region and the N-doped epitaxial layer 231 is proportional to the schottky barrier height and inversely proportional to the N-type ion concentration, and thus the contact resistance can be reduced by forming the second N-doped epitaxial layer 236.

In this embodiment, the first N-type doped epitaxial layer 235 is formed first, and then the second N-type doped epitaxial layer 236 is formed. That is, the step of forming the N region doped epitaxial layer 231 includes: forming a first epitaxial layer in the N-region groove 122; doping N-type ions into the first epitaxial layer to form a first N-type doped epitaxial layer 235; forming a second epitaxial layer on the first N-type doped epitaxial layer 235; doping the second epitaxial layer with N-type ions to form a second N-type doped epitaxial layer 236; the second N-type doped epitaxial layer 236 and the first N-type doped epitaxial layer 235 form an N-region doped epitaxial layer 231.

In other embodiments, the second N-type doped epitaxial layer may be formed first, and then the first N-type doped epitaxial layer may be formed.

In this embodiment, the N region doped epitaxial layer 231 is formed by a selective epitaxy process. Specifically, the step of forming the first N-type doped epitaxial layer 235 includes: in the step of forming the first epitaxial layer in the N region groove 122, N-type ions are doped in situ into the first epitaxial layer; the step of forming the second N-type doped epitaxial layer 236 includes: in the step of forming a second epitaxial layer on the first N-type doped epitaxial layer 235, N-type ions are doped in-situ to the second epitaxial layer.

In other embodiments, the N region doped epitaxial layer may also be formed by a non-epitaxial process. Correspondingly, the step of forming the first N-type doped epitaxial layer comprises: after a first epitaxial layer is formed in the N-region groove, doping N-type ions into the first epitaxial layer; the step of forming the second N-type doped epitaxial layer comprises: and doping N-type ions into the second epitaxial layer after forming the second epitaxial layer on the first N-type doped layer.

In this embodiment, the material of the first epitaxial layer is Si, and the N-type ions are P ions, so that the material of the first N-type doped epitaxial layer 235 is Si doped with P ions; the doping concentration of the P ions is determined according to the actual process requirements. In this example, the doping concentration of P ions was 1E21atom/cm³To 2E21atom/cm³. In other embodiments, the material of the first epitaxial layer may also be SiC.

In this embodiment, the material of the second epitaxial layer is SiGe, and the N-type ions are P-ions, so that the material of the second N-type doped epitaxial layer 236 is SiGe doped with P-ions.

It should be noted that the doping concentration of P ions in the second N-type doped epitaxial layer 236 is not too small. If the doping concentration of P ions is too small, the effect of reducing the contact resistance is not obvious, and the doping concentration of P ions in the second N-type doped epitaxial layer 236 is 2.5E20atom/cm in this embodiment because of the limitation of the solid solubility of P ions in SiGe³To 1.8E21atom/cm³。

It should be noted that the atomic percent content of Ge in the second N-type doped epitaxial layer 236 is not too low nor too high. If the atomic percentage content of Ge is too low, the effect of reducing the Schottky barrier height is not obvious; if the Ge content is too high in atomic percent, it tends to adversely affect the electrical properties of the resulting N-type device. For this reason, in the present embodiment, the content of Ge is 5 to 45 atomic%. Wherein, the content of Ge in atomic percent refers to the percentage of the total atomic number of Ge in the total atomic number of Si and Ge.

Correspondingly, in order to ensure that the effect of reducing the schottky barrier height is reduced and to avoid adverse effects on the electrical properties of the formed N-type device, in this embodiment, the thickness of the second epitaxial layer is 2nm to 8 nm.

Referring to fig. 21 to 23 in combination, fig. 21 is a schematic cross-sectional view based on fig. 19, fig. 22 is a schematic cross-sectional view taken along a line cut in the extending direction of the first fin (e.g., a line cut at BB1 in fig. 1), and fig. 23 is a schematic cross-sectional view taken along a line cut in the extending direction of the second fin (e.g., a line cut at CC1 in fig. 1), wherein an interlayer dielectric layer 104 is formed on the N-doped epitaxial layer 231.

The interlayer dielectric layer 104 is used for realizing electrical isolation between adjacent semiconductor structures and also used for providing a process platform for the subsequent formation of contact hole plugs.

In this embodiment, in the step of forming the interlayer dielectric layer 104 on the N-region doped epitaxial layer 231, the interlayer dielectric layer 104 is also located on the P-region doped epitaxial layer 131.

The interlayer dielectric layer 104 is made of an insulating material. In this embodiment, the interlayer dielectric layer 104 is made of silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be silicon nitride or silicon oxynitride.

It should be noted that the gate structure 102 (as shown in fig. 20) is a pseudo gate structure, so after the N region doped epitaxial layer 231 and the P region doped epitaxial layer 131 are formed, and before the interlayer dielectric layer 104 is formed, the forming method further includes: forming a bottom dielectric layer 103 on the substrate exposed by the gate structure 102, wherein the bottom dielectric layer 103 exposes the top of the gate structure 102 in the NMOS region II and the PMOS region I; removing the gate structure 102, and forming a gate opening (not shown) in the bottom dielectric layer 103; a metal gate structure 250 is formed within the gate opening (as shown in fig. 22).

A gate hard mask layer 210 is formed on the top of the gate structure 102 (as shown in fig. 20), so before removing the gate structure 102, the forming method further includes: the gate hard mask layer 210 is removed.

The bottom dielectric layer 103 is used to electrically isolate adjacent semiconductor structures, to provide a process platform for the subsequent formation of contact plugs, and to form gate openings to define the size and position of the metal gate structure 250 formed.

The bottom dielectric layer 103 is made of an insulating material. In this embodiment, in order to improve process compatibility, the material of the bottom dielectric layer 103 is the same as that of the interlayer dielectric layer 104, and the material of the bottom dielectric layer 103 is silicon oxide. In other embodiments, the material of the bottom dielectric layer may also be silicon nitride or silicon oxynitride.

The metal gate structure 250 is used to control the conduction and the cut-off of the channel of the formed semiconductor structure.

Specifically, the step of forming a metal gate structure 250 (as shown in fig. 22) within the gate opening includes: forming a high-k gate dielectric layer (not labeled) on the bottom and the side wall of the gate opening, wherein the high-k gate dielectric layer is also positioned at the top of the bottom dielectric layer 103; forming a metal layer (not labeled) on the high-k gate dielectric layer; and removing the metal layer higher than the top of the bottom dielectric layer 103, and also removing the high-k gate dielectric layer higher than the top of the bottom dielectric layer 103, wherein the remaining high-k gate dielectric layer and the metal layer in the gate opening form the metal gate structure 250. Correspondingly, the top of the bottom dielectric layer 103 is flush with the top of the metal gate structure 250.

The high-k gate dielectric layer is made of a gate dielectric material with a relative dielectric constant larger than that of silicon oxide. In this embodiment, the material of the high-k gate dielectric layer is HfO₂. In other embodiments, the material of the high-k gate dielectric layer may also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or ZrO₂Or Al₂O₃。

In this embodiment, the metal layer is made of W. In other embodiments, the material of the metal layer may also be Al, Cu, Ag, Au, Pt, Ni, or Ti.

Correspondingly, in the step of forming the interlayer dielectric layer 104, the interlayer dielectric layer 104 covers the bottom dielectric layer 103 and the metal gate structure 250.

With reference to fig. 24 to 26, fig. 24 is a schematic cross-sectional view based on fig. 21, fig. 25 is a schematic cross-sectional view based on fig. 22, and fig. 26 is a schematic cross-sectional view based on fig. 23, wherein a first contact opening 114 exposing the N-doped epitaxial layer 231 is formed in the interlayer dielectric layer 104 of the NMOS region II.

The first contact opening 114 of the NMOS region II provides a spatial location for a first contact plug to be subsequently formed and electrically connected to the N-doped epitaxial layer 231.

In this embodiment, the first contact opening 114 is further formed in the interlayer dielectric layer 104 of the PMOS region I and exposes the P-region doped epitaxial layer 131; the first contact opening 114 of the PMOS region I provides a spatial location for the subsequent formation of a first contact plug electrically connected to the P-doped epitaxial layer 131.

Specifically, the interlayer dielectric layer 104 covers the bottom dielectric layer 103 and the metal gate structure 250, so in the step of forming the first contact opening 114, the first contact opening 114 of the NMOS region II further penetrates through the bottom dielectric layer 103 to expose the N-region doped epitaxial layer 231, and the first contact opening 114 of the PMOS region I further penetrates through the bottom dielectric layer 103 to expose the P-region doped epitaxial layer 131.

In this embodiment, the interlayer dielectric layer 104 and the bottom dielectric layer 103 above the N-region doped epitaxial layer 231 and above the P-region doped epitaxial layer 131 are removed by dry etching.

It should be noted that, in the present embodiment, the first contact opening 114 is formed by a non-self-aligned process. Therefore, before the interlayer dielectric layer 104 and the bottom dielectric layer 103 are etched, a pattern layer is also formed on part of the interlayer dielectric layer 104; in the step of forming the first contact opening 114, etching is performed with the pattern layer as a mask. In other embodiments, the first contact opening may also be formed by a self-aligned process.

It should be further noted that, in the step of forming the first contact opening 114, a second contact opening 124 is further formed in the interlayer dielectric layer 104 above the metal gate structures 250 in the NMOS region II and the PMOS region I (as shown in fig. 25), and the metal gate structures 250 are exposed from the second contact opening 124.

The second contact opening 124 provides a spatial location for a second contact hole plug to be subsequently formed in electrical connection with the metal gate structure 250.

Referring to fig. 27 to 29 in combination, fig. 27 is a schematic cross-sectional view based on fig. 24, fig. 28 is a schematic cross-sectional view based on fig. 25, and fig. 29 is a schematic cross-sectional view based on fig. 26, wherein a first contact plug 151 electrically connected to the N-doped epitaxial layer 231 is formed in the first contact opening 114 (shown in fig. 24).

In this embodiment, in the step of forming the first contact plug 151 in the first contact opening 114, the first contact plug 151 is also formed in the first contact opening 114 of the PMOS region I and electrically connected to the P-region doped epitaxial layer 131.

The first contact hole plug 151 of the PMOS region I is electrically connected to the P region doped epitaxial layer 131, the first contact hole plug 151 of the NMOS region II is electrically connected to the N region doped epitaxial layer 231, and the first contact hole plug 151 is used for achieving electrical connection in a semiconductor device and electrical connection between devices.

In this embodiment, a second contact opening 124 (as shown in fig. 25) exposing the metal gate structure 250 is formed in the interlayer dielectric layer 104 above the metal gate structures 250 in the NMOS region II and the PMOS region I, so that in the step of forming the first contact plug 151 in the first contact opening 114, a second contact plug 152 (as shown in fig. 28) electrically connected to the metal gate structure 250 is also formed in the second contact opening 124.

The second contact hole plug 152 is electrically connected to the metal gate structure 250, and is used for electrical connection in a semiconductor device and electrical connection between devices.

Specifically, the step of forming the first and second contact hole plugs 151 and 152 includes: filling conductive materials into the first contact opening 114 and the second contact opening 124 of the PMOS region I and the first contact opening 114 and the second contact opening 124 of the NMOS region II, wherein the conductive materials are also located on the top of the interlayer dielectric layer 104; the conductive material is planarized to remove the conductive material above the top of the interlevel dielectric layer 104, forming a first contact plug 151 in the first contact opening 114 and a second contact plug 152 in the second contact opening 124.

In this embodiment, the material of the first contact hole plug 151 and the second contact hole plug 152 is uniform W, and the first contact hole plug 151 and the second contact hole plug 152 may be formed by a chemical vapor deposition process, a sputtering process, or an electroplating process. In other embodiments, the material of the first contact hole plug may also be a metal material such as Al, Cu, Ag, or Au, and the material of the second contact hole plug may also be a metal material such as Al, Cu, Ag, or Au.

It should be noted that, in order to reduce the contact resistance of the contact region, before filling the first contact opening 114 and the second contact opening 124 of the PMOS region I and the first contact opening 114 and the second contact opening 124 of the NMOS region II with a conductive material, the forming method further includes: a metal silicide layer (not shown) is formed at the bottom of the first contact opening 114. In this embodiment, the material of the metal silicide layer is TiSi. In other embodiments, the material of the metal silicide layer may also be NiSi.

It should be further noted that, in other embodiments, when a process of forming a high-k gate dielectric layer first and a gate electrode layer (high-k first metal gate first) first is adopted, in the step of forming a gate structure on the substrate, the gate structure is a metal gate structure; correspondingly, in the step of forming the interlayer dielectric layer, the interlayer dielectric layer is formed on the substrate exposed out of the grid structure, and the top of the interlayer dielectric layer is higher than that of the grid structure; in the step of forming the second contact opening, forming a second contact opening exposing the gate structure in the interlayer dielectric layer above the gate structures of the NMOS region and the PMOS region; in the step of forming a first contact hole plug within the first contact opening, a second contact hole plug is also formed within the second contact opening.

In the technical scheme of the method for forming the semiconductor structure, an N-region doped epitaxial layer is formed in the N-region groove, and is of a laminated structure formed by a first N-type doped epitaxial layer and a second N-type doped epitaxial layer, wherein the first N-type doped epitaxial layer is a first epitaxial layer doped with N-type ions, the second N-type doped epitaxial layer is a second epitaxial layer doped with N-type ions, and the forbidden bandwidth of the second epitaxial layer is smaller than that of the first epitaxial layer. Compared with the scheme that the formed N region doped epitaxial layer only comprises the first epitaxial layer doped with N-type ions, the forbidden bandwidth of the second epitaxial layer is smaller, so that the Schottky barrier height of the N region doped epitaxial layer and the channel region can be reduced through the second epitaxial layer; in addition, the doping ions of the second N-type doping epitaxial layer are N-type ions, so that the concentration of the N-type ions in the N-region doping epitaxial layer is improved; since the contact resistance is proportional to the schottky barrier height and inversely proportional to the N-type ion concentration, the scheme of the invention can reduce the contact resistance to improve the driving current of the formed N-type device, thereby improving the electrical performance of the semiconductor structure.

In addition, the step of forming the N region doped epitaxial layer comprises the following steps: forming a first epitaxial layer in the N-region groove; doping N-type ions into the first epitaxial layer to form a first N-type doped epitaxial layer; forming a second epitaxial layer on the first N-type doped epitaxial layer; doping N-type ions into the second epitaxial layer to form a second N-type doped epitaxial layer; the second N-type doped epitaxial layer and the first N-type doped epitaxial layer form an N-region doped epitaxial layer, correspondingly, the top material of the N-region doped epitaxial layer is SiGe doped with N-type ions, in the subsequent step of forming the first contact opening, the first contact opening is further formed in an interlayer medium layer of the PMOS region and exposes the P-region doped epitaxial layer, the P-region doped epitaxial layer is made of SiGe doped with P-type ions, namely, the exposed material of the first contact opening is SiGe, and therefore the forming process of the first contact opening and the forming process of the subsequent first contact hole plug are facilitated to be optimized.

Referring to fig. 30 to 32, which are schematic structural diagrams illustrating a semiconductor structure according to an embodiment of the present invention, fig. 30 is a schematic cross-sectional structure of a fin portion at a side of a gate structure along a line perpendicular to a fin extending direction (as indicated by EE1 in fig. 4), fig. 31 is a schematic cross-sectional structure of a line along a first fin extending direction (as indicated by BB1 in fig. 1), and fig. 32 is a schematic cross-sectional structure of a line along a second fin extending direction (as indicated by CC1 in fig. 1). Accordingly, the present invention also provides a semiconductor structure comprising:

a substrate (not labeled) comprising an NMOS region II with an N-type device; a gate structure 450 (shown in fig. 32) on the substrate; an N-region doped epitaxial layer 631 (as shown in fig. 32) located in the substrate on both sides of the NMOS region II gate structure 450, where the N-region doped epitaxial layer 631 is a stacked structure formed by a first N-type doped epitaxial layer 635 and a second N-type doped epitaxial layer 636, where the first N-type doped epitaxial layer 635 is a first epitaxial layer doped with N-type ions, the second N-type doped epitaxial layer 636 is a second epitaxial layer doped with N-type ions, and a forbidden bandwidth of the second epitaxial layer is smaller than a forbidden bandwidth of the first epitaxial layer; an interlayer dielectric layer 402 positioned on the N region doped epitaxial layer 631; and a first contact hole plug 451 which penetrates through the interlayer dielectric layer 402 of the NMOS region II and is electrically connected to the N region doped epitaxial layer 631.

In this embodiment, the base has a finfet, and thus the base includes a substrate 400 and a discrete fin (not shown) on the substrate 400. In other embodiments, the base has a planar transistor thereon, and accordingly, the base is a planar substrate.

In this embodiment, taking the finfet as a CMOS device as an example, the substrate 400 includes not only an NMOS region II with an N-type device, but also a PMOS region I with a P-type device, and the substrate 400 of the PMOS region I and the NMOS region II both have discrete fins. In other embodiments, when the finfet is an NMOS device, the substrate includes only an NMOS region.

Accordingly, the semiconductor structure further comprises: and a P region doped epitaxial layer 531 (shown in fig. 31) positioned in the substrate at two sides of the PMOS region igate structure 450.

In this embodiment, the fin on the PMOS region I substrate 400 is a first fin 410, and the fin on the NMOS region II substrate 400 is a second fin 420. Accordingly, the gate structure 450 of the PMOS region I crosses over the first fin 410 and covers a portion of the top surface and sidewall surface of the first fin 410; the gate structure 450 of the NMOS region II crosses over the second fin 420 and covers a portion of the top surface and sidewall surface of the second fin 420; the N region doped epitaxial layer 631 is located in the second fin 420 at two sides of the NMOS region II gate structure 450; the P-region doped epitaxial layer 531 is located in the first fin portion 410 at two sides of the PMOS region I-gate structure 450.

In order to improve the carrier mobility of the semiconductor device, the substrate is a germanium-containing substrate. In this embodiment, the germanium-containing base is a germanium base, and correspondingly, the substrate 400 is made of germanium. In other embodiments, the material of the germanium-containing substrate can also be silicon germanium, and the germanium-containing substrate can also be a germanium-on-insulator substrate. The material of the substrate may be chosen to suit the process requirements or to facilitate integration.

The material of the fin is the same as the material of the substrate 400. Therefore, in the present embodiment, the material of the fin portion is germanium, that is, the material of the first fin portion 410 and the second fin portion 420 is germanium.

In addition, the semiconductor structure further includes: and an isolation structure 401 (as shown in fig. 30) on the substrate 400 with the exposed fin portion, wherein the isolation structure 401 covers a portion of the sidewall of the fin portion, and the top of the isolation structure 401 is lower than the top of the fin portion.

The isolation structure 401 serves as an isolation structure of a semiconductor device and is used for isolating adjacent devices or adjacent fins. In this embodiment, the isolation structure 401 is made of silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride.

In this embodiment, the gate structure 450 is a metal gate structure (metal gate), and the gate structure 450 is used for controlling the conduction and the interruption of the formed semiconductor structure channel.

Specifically, the gate structure 450 includes a high-k gate dielectric layer and a metal layer on the surface of the high-k gate dielectric layer.

The P region doped epitaxial layer 531 is used as a source region or a drain region of the P-type device.

In this embodiment, the P-doped epitaxial layer 531 includes a first P-doped epitaxial layer (not labeled) and a second P-doped epitaxial layer (not labeled) on the first P-doped epitaxial layer; the first P-type doped epitaxial layer is a first semiconductor layer doped with P-type ions, and the second P-type doped epitaxial layer is a second semiconductor layer doped with P-type ions.

The first semiconductor layer and the second semiconductor layer can be used for providing a pressure stress effect for a channel region of the P-type device, so that the carrier mobility of the P-type device is improved.

It should be noted that the higher the doping concentration of the P-type ions in the P-region doped epitaxial layer 531 is, the more obvious the pressure stress providing effect is correspondingly played; however, the higher doping concentration of P-type ions also leads to an excessively high contact resistance of the contact hole plug. Therefore, in order to ensure that the pressure stress action is provided and simultaneously the contact resistance is reduced, the doping ion concentration of the second P-type doping epitaxial layer is smaller than that of the first P-type doping epitaxial layer. The doping concentrations of the first P-type doped epitaxial layer and the second P-type doped epitaxial layer are determined according to actual process requirements.

In this embodiment, the first P-type doped epitaxial layer has a Ge content of 30 to 60 atomic%, and a B ion doping concentration of 1.4E21atom/cm³To 2.6E21atom/cm³(ii) a The first P-type doped epitaxial layer contains 10 to 20 atomic percent of Ge and has the doping concentration of B ions of 1.4E20atom/cm³To 2.6E20atom/cm³. And the ratio of the thickness of the first semiconductor layer to the thickness of the second semiconductor layer is 1:15 to 1: 5. Wherein, the content of Ge in atomic percent refers to the percentage of the total atomic number of Ge in the total atomic number of Si and Ge.

The N region doped epitaxial layer 631 is used as a source or drain region of an N-type device.

The second epitaxial layer has a smaller forbidden bandwidth, so that the schottky barrier height of the N region doped epitaxial layer 631 and the channel region is reduced through the second epitaxial layer; and the doping ions of the second N-type doped epitaxial layer 636 are N-type ions, so that the concentration of the N-type ions in the N-region doped epitaxial layer 631 is increased. The contact resistance of the N-doped epitaxial layer 631 and the contact hole plug contact region is proportional to the schottky barrier height and inversely proportional to the N-type ion concentration, and thus the contact resistance can be reduced by the second N-doped epitaxial layer 636.

In this embodiment, the N-doped epitaxial layer 631 includes a first N-doped epitaxial layer 635, and a second N-doped epitaxial layer 636 located on the first N-doped epitaxial layer 635; the first N-type doped epitaxial layer 635 is a first epitaxial layer doped with N-type ions, and the second N-type doped epitaxial layer 636 is a second epitaxial layer doped with N-type ions.

In other embodiments, the N region doped epitaxial layer includes a second N type doped epitaxial layer and a first N type doped epitaxial layer on the second N type doped epitaxial layer.

In this embodiment, the first epitaxial layer is made of Si, and the N-type ions are P ions, so that the first N-type doped epitaxial layer 635 is made of Si doped with P ions; the doping concentration of the P ions is determined according to the actual process requirements. In this example, the doping concentration of P ions was 1E21atom/cm³To 2E21atom/cm³. In other embodiments, the material of the first epitaxial layer may also be SiC.

In this embodiment, the second epitaxial layer is made of SiGe, and the N-type ions are P-ions, so that the second N-doped epitaxial layer 636 is made of SiGe doped with P-ions.

It should be noted that the doping concentration of P ions in the second N-type doped epitaxial layer 636 is not too small. If the doping concentration of P ions is too small, the effect of reducing the contact resistance is not obvious, and the doping concentration of P ions in the second N-type doped epitaxial layer 636 is 2.5E20atom/cm in this embodiment because of the solid solubility limit of P ions in SiGe³To 1.8E21atom/cm³。

It should be noted that the content of Ge in atomic percent should not be too low or too high. If the atomic percentage content of Ge is too low, the effect of reducing the Schottky barrier height is not obvious; if the Ge content is too high in atomic percent, it tends to adversely affect the electrical properties of the resulting N-type device. For this reason, in the present embodiment, the content of Ge is 5 to 45 atomic%. Wherein, the content of Ge in atomic percent refers to the percentage of the total atomic number of Ge in the total atomic number of Si and Ge.

The interlayer dielectric layer 402 is used to electrically isolate adjacent semiconductor structures and also to provide a process platform for the formation of the first contact hole plug 451.

In this embodiment, the interlayer dielectric layer 402 is located on the substrate where the gate structure 450 is exposed, and the top of the interlayer dielectric layer 402 is higher than the top of the gate structure 450.

The interlayer dielectric layer 402 is made of an insulating material. In this embodiment, the interlayer dielectric layer 402 is made of silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be silicon nitride or silicon oxynitride.

It should be noted that the interlayer dielectric layer 402 is also located on the P region doped epitaxial layer 531.

Correspondingly, the first contact hole plug 451 not only penetrates through the interlayer dielectric layer 402 of the NMOS region II, but also penetrates through the interlayer dielectric layer 402 of the PMOS region I and is electrically connected with the P region doped epitaxial layer 531.

The first contact hole plug 451 of the PMOS region I is electrically connected with the P region doped epitaxial layer 531, the first contact hole plug 451 of the NMOS region II is electrically connected with the N region doped epitaxial layer 631, and the first contact hole plug 451 is used for achieving electrical connection in a semiconductor device and electrical connection between devices.

In this embodiment, the semiconductor structure further includes: and a second contact hole plug 452 penetrating the interlayer dielectric layer 402 above the gate structure 450 of the NMOS region II and the PMOS region I and electrically connected with the gate structure 450 (as shown in FIG. 32). The second contact hole plug 452 is electrically connected to the gate structure 450, and is used for electrical connection in a semiconductor device and electrical connection between devices.

In this embodiment, the material of each of the first contact hole plug 451 and the second contact hole plug 452 is W. In other embodiments, the material of the first contact hole plug may also be a metal material such as Al, Cu, Ag, or Au, and the material of the second contact hole plug may also be a metal material such as Al, Cu, Ag, or Au.

It should be noted that, in order to reduce the contact resistance of the contact region, the semiconductor structure further includes a metal silicide layer (not shown) located between the first contact hole plug 451 and the N-region doped epitaxial layer 631 and also located between the first contact hole plug 451 and the P-region doped epitaxial layer 531. In this embodiment, the material of the metal silicide layer is TiSi. In other embodiments, the material of the metal silicide layer may also be NiSi.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

In this embodiment, the semiconductor structure includes an N-region doped epitaxial layer located in the substrate on both sides of the NMOS area gate structure, the N-region doped epitaxial layer is a stacked structure formed by a first N-type doped epitaxial layer and a second N-type doped epitaxial layer, wherein the first N-type doped epitaxial layer is a first epitaxial layer doped with N-type ions, the second N-type doped epitaxial layer is a second epitaxial layer doped with N-type ions, and a forbidden bandwidth of the second epitaxial layer is smaller than a forbidden bandwidth of the first epitaxial layer. Compared with the scheme that the N region doped epitaxial layer only comprises the first epitaxial layer doped with N-type ions, the Schottky barrier height of the N region doped epitaxial layer and the channel region can be reduced through the second epitaxial layer due to the fact that the forbidden bandwidth of the second epitaxial layer is small; in addition, the doping ions of the second N-type doping epitaxial layer are N-type ions, so that the concentration of the N-type ions in the N-region doping epitaxial layer is improved; because the contact resistance is in direct proportion to the height of the Schottky barrier and in inverse proportion to the concentration of the N-type ions, the contact resistance of the semiconductor structure is smaller, the driving current of an N-type device is correspondingly improved, and the electrical performance of the semiconductor structure is improved.

Claims

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises an NMOS region for forming an N-type device;

forming a gate structure on the substrate;

forming N-region grooves in the substrate at two sides of the grid structure of the NMOS region;

forming an N-region doped epitaxial layer in the N-region groove, wherein the N-region doped epitaxial layer is a laminated structure formed by a first N-type doped epitaxial layer and a second N-type doped epitaxial layer, the first N-type doped epitaxial layer is a first epitaxial layer doped with N-type ions, the second N-type doped epitaxial layer is a second epitaxial layer doped with N-type ions, and the forbidden bandwidth of the second epitaxial layer is smaller than that of the first epitaxial layer;

forming an interlayer dielectric layer on the N region doped epitaxial layer;

forming a first contact opening exposing the N region doped epitaxial layer in the interlayer dielectric layer of the NMOS region;

forming a first contact hole plug electrically connected with the N region doped epitaxial layer in the first contact opening;

the step of forming the N-region groove comprises the following steps: forming N-region initial grooves in the substrate on two sides of the grid structure of the NMOS region; and etching the side wall and the bottom of the N-region initial groove by using mixed etching gas, removing damaged materials with partial thickness in the process of forming the N-region initial groove, and forming the N-region groove, wherein the mixed etching gas comprises silicon source gas and HCl gas, the silicon source gas is used for forming a Ge-Si bond with the damaged materials, and the HCl gas is used for removing the Ge-Si bond.

2. The method of forming a semiconductor structure of claim 1, wherein a material of the first epitaxial layer comprises Si; the material of the second epitaxial layer is SiGe.

3. The method of claim 1, wherein the first N-type doped epitaxial layer is formed of Si doped with P ions at a doping concentration of 1E21 atoms/cm³To 2E21atom/cm³。

4. The method of claim 1, wherein the second N-type doped epitaxial layer is SiGe doped with P ions having a doping concentration of 2.5E20 atoms/cm³To 1.8E21atom/cm³And the content of Ge in atomic percent is 5-45%.

5. The method of forming a semiconductor structure of claim 1, wherein the second epitaxial layer has a thickness of 2nm to 8 nm.

6. The method of forming a semiconductor structure of claim 1, wherein forming the N-region doped epitaxial layer comprises: forming a first epitaxial layer in the N-region groove;

doping N-type ions into the first epitaxial layer to form a first N-type doped epitaxial layer;

forming a second epitaxial layer on the first N-type doped epitaxial layer;

doping N-type ions into the second epitaxial layer to form a second N-type doped epitaxial layer; the second N-type doped epitaxial layer and the first N-type doped epitaxial layer form an N-region doped epitaxial layer.

7. The method of forming a semiconductor structure of claim 1, wherein the silicon source gas is SiH₄、Si₂Cl₂Or SiHCl₃。

8. The method of claim 1, wherein in the step of forming the N-region recess, the silicon source gas is SiH₄，SiH₄The gas flow rate of the gas is 10sccm to 1000sccm, the gas flow rate of the HCl is 5sccm to 100sccm, and the process temperature is 400 ℃ to 700 ℃.

9. The method of forming a semiconductor structure of claim 1, wherein in the step of providing a substrate, the substrate further comprises a PMOS region for forming a P-type device;

after forming the gate structure on the substrate, before forming an interlayer dielectric layer on the N region doped epitaxial layer, the forming method further includes: forming P-region grooves in the substrate at two sides of the grid structure of the PMOS region; forming a P region doped epitaxial layer in the P region groove;

in the step of forming the interlayer dielectric layer on the N region doped epitaxial layer, the interlayer dielectric layer is also positioned on the P region doped epitaxial layer;

in the step of forming a first contact opening exposing the N-region doped epitaxial layer in the interlayer dielectric layer of the NMOS region, the first contact opening is also formed in the interlayer dielectric layer of the PMOS region and exposes the P-region doped epitaxial layer;

in the step of forming a first contact hole plug electrically connected with the N-region doped epitaxial layer in the first contact opening, the first contact hole plug is also formed in the first contact opening of the PMOS region and electrically connected with the P-region doped epitaxial layer.

10. The method for forming a semiconductor structure according to claim 9, wherein the gate structure is a dummy gate structure;

after the N-region doped epitaxial layer and the P-region doped epitaxial layer are formed, and before the interlayer dielectric layer is formed, the forming method further includes: forming a bottom dielectric layer on the substrate with the exposed grid structure, wherein the bottom dielectric layer exposes the tops of the grid structures of the NMOS area and the PMOS area; removing the grid structure, and forming a grid opening in the bottom dielectric layer; forming a metal gate structure in the gate opening;

in the step of forming the interlayer dielectric layer, the interlayer dielectric layer covers the bottom dielectric layer and the metal gate structure;

in the step of forming the first contact opening, the first contact opening further penetrates through the bottom dielectric layer;

after the forming of the interlayer dielectric layer and before forming the first contact hole plug in the first contact opening, the forming method further comprises: forming a second contact opening exposing the metal gate structure in the interlayer dielectric layer above the metal gate structures of the NMOS area and the PMOS area;

and in the step of forming the first contact hole plug in the first contact opening, a second contact hole plug electrically connected with the metal gate structure is also formed in the second contact opening.

11. The method of claim 1, wherein in the step of providing a base, the base comprises a substrate and discrete fins on the substrate;

in the step of forming the gate structure on the substrate, the gate structure crosses over the fin portion and covers part of the top surface and the sidewall surface of the fin portion;

and in the step of forming N-region grooves in the substrate on two sides of the gate structure of the NMOS region, forming the N-region grooves in the fin parts on two sides of the gate structure of the NMOS region.

12. A semiconductor structure, comprising:

a substrate comprising an NMOS region with an N-type device;

the grid structure is positioned on the substrate;

the N-region doped epitaxial layer is positioned in the substrate on two sides of the grid structure of the NMOS region and is a laminated structure formed by a first N-type doped epitaxial layer and a second N-type doped epitaxial layer, wherein the first N-type doped epitaxial layer is a first epitaxial layer doped with N-type ions, the second N-type doped epitaxial layer is a second epitaxial layer doped with N-type ions, and the forbidden bandwidth of the second epitaxial layer is smaller than that of the first epitaxial layer;

the interlayer dielectric layer is positioned on the N region doped epitaxial layer;

the first contact hole plug penetrates through the interlayer dielectric layer of the NMOS region and is electrically connected with the N region doped epitaxial layer;

the N-region doped epitaxial layer is formed in N-region grooves in substrates on two sides of the NMOS region grid structure, the N-region grooves are formed by forming N-region initial grooves in the substrates on two sides of the NMOS region grid structure, etching the side wall and the bottom of the N-region initial groove by using mixed etching gas, and removing damaged materials with partial thickness in the process of forming the N-region initial groove, the mixed etching gas comprises silicon source gas and HCl gas, the silicon source gas is used for forming Ge-Si bonds with the damaged materials, and the HCl gas is used for removing the Ge-Si bonds.

13. The semiconductor structure of claim 12, wherein a material of the first epitaxial layer comprises Si; the material of the second epitaxial layer is SiGe.

14. The semiconductor structure of claim 12, wherein the material of the first N-type doped epitaxial layer is Si doped with P ions with a doping concentration of 1E21atom/cm³To 2E21atom/cm³。

15. The semiconductor structure of claim 12, wherein the material of the second N-type doped epitaxial layer is SiGe doped with P ions having a doping concentration of 2.5E20 atoms/cm³To 1.8E21atom/cm³And the content of Ge in atomic percent is 5-45%.

16. The semiconductor structure of claim 12, wherein the thickness of the second epitaxial layer is from 2nm to 8 nm.

17. The semiconductor structure of claim 12, wherein the N-region doped epitaxial layer comprises a first N-doped epitaxial layer and a second N-doped epitaxial layer on the first N-doped epitaxial layer.

18. The semiconductor structure of claim 12, wherein the substrate further comprises a PMOS region having a P-type device;

the semiconductor structure further includes: the P region doped epitaxial layer is positioned in the substrate at two sides of the grid structure of the PMOS region;

the interlayer dielectric layer is also positioned on the P region doped epitaxial layer;

the first contact hole plug also penetrates through the interlayer dielectric layer of the PMOS region and is electrically connected with the P region doped epitaxial layer.

19. The semiconductor structure of claim 12, wherein the base comprises a substrate and a discrete fin on the substrate;

the grid electrode structure crosses the fin part and covers part of the top surface and the side wall surface of the fin part;

the N region doped epitaxial layer is located in the fin portions on two sides of the grid electrode structure of the NMOS region.