CN105092111A - Capacitive pressure sensor and manufacturing method thereof - Google Patents
Capacitive pressure sensor and manufacturing method thereof Download PDFInfo
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- CN105092111A CN105092111A CN201410196810.9A CN201410196810A CN105092111A CN 105092111 A CN105092111 A CN 105092111A CN 201410196810 A CN201410196810 A CN 201410196810A CN 105092111 A CN105092111 A CN 105092111A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
- G01L1/00—Measuring force or stress, in general
- G01L1/14—Measuring force or stress, in general by measuring variations in capacitance or inductance of electrical elements, e.g. by measuring variations of frequency of electrical oscillators
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
- G01L9/00—Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means
- G01L9/12—Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means by making use of variations in capacitance, i.e. electric circuits therefor
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- Pressure Sensors (AREA)
- Measuring Fluid Pressure (AREA)
Abstract
The invention provides a capacitive pressure sensor and a manufacturing method thereof. The capacitive pressure sensor comprises an insulating substrate; a lower electrode formed on the insulating substrate; and a semiconductor substrate with a groove formed on a first surface. The first surface of the semiconductor substrate is opposed to the lower electrode and bonded to the insulating substrate. The lower electrode is accommodated inside the groove. A gap is present between the lower electrode and the semiconductor substrate. The capacitive pressure sensor further comprises an upper electrode being a doped region formed in the semiconductor substrate corresponding to the groove; and an upper electrode lead wire and a lower electrode lead wire respectively connected to the upper electrode and the lower electrode. By making the upper electrode and the lower electrode respectively formed on the semiconductor substrate and the insulating substrate, the capacitive pressure sensor requires no use of expensive TSV technologies for isolation. By means of the technical scheme provided in the invention, technically complex deep-pit etching can be prevented. Capacitive characteristics can be further prevented from being affected by etching.
Description
Technical field
The present invention generally relates to sensor field, and relates more specifically to the method for capacitance pressure transducer, and this capacitance pressure transducer, of making.
Background technology
At present, there is a kind of capacitance pressure transducer, it is by forming electric capacity cavity by two panels SOI wafer bonding, and upper/lower electrode is formed by silicon.But, make capacitance pressure transducer, by the method and there is more drawback.First, the dell etching technics adopted in this technology is very complicated, and the characteristic of electric capacity easily produces drift by the impact of etch chamber.Secondly, because the cost of SOI wafer is higher, the cost of manufacture of this capacitance pressure transducer, can therefore be increased.And need to adopt silicon through hole (ThroughSiliconVia, TSV) technology to isolate, and this technical costs is very high.
Therefore, a kind of method capacitance pressure transducer, being provided and making this capacitance pressure transducer, is needed, to solve the above-mentioned problem.
Summary of the invention
For solving the problems of the technologies described above, the invention provides a kind of capacitance pressure transducer, comprising: dielectric substrate; Bottom electrode, it is formed in described dielectric substrate; Semiconductor substrate, the first surface of described Semiconductor substrate is formed with groove, the described first surface of described Semiconductor substrate is relative with described bottom electrode and be bonded to described dielectric substrate, and described bottom electrode to be contained in described groove and and there is gap between described Semiconductor substrate; Top electrode, it is be formed in the doped region in Semiconductor substrate corresponding to described groove; And top electrode goes between and bottom electrode lead-in wire, it is connected to described top electrode and described bottom electrode respectively.
Preferably, in described doped region doped with boron and/or phosphorus.
Preferably, described dielectric substrate is glass substrate, and/or described bottom electrode is metal electrode, and/or described Semiconductor substrate is silicon substrate.
Preferably, the bottom surface of described groove is 10-100 micron to the thickness of the second surface relative with described first surface of described Semiconductor substrate.
Preferably, described bottom electrode cover described dielectric substrate surface on or be embedded in described dielectric substrate.
This capacitance pressure transducer, provided by the invention, by being respectively formed in Semiconductor substrate and dielectric substrate by top electrode and bottom electrode, can be avoided the TSV technology of use cost costliness to isolate.And adopt the dell etching that technology of the present invention can avoid technique comparatively complicated, and then the characteristic affecting electric capacity because of etching can be avoided.In addition owing to decreasing the use of SOI substrate, the cost of manufacture of this capacitance pressure transducer, 100 can therefore be lowered.
Present invention also offers a kind of method making above-mentioned capacitance pressure transducer, described method comprises: provide dielectric substrate; Described dielectric substrate is formed bottom electrode and bottom electrode lead-in wire; Semiconductor base is provided; First substrate surface of described semiconductor base forms groove; Perform doping process to form doped region in the described semiconductor base below described groove, described doped region does not arrive second substrate surface relative with described first substrate surface of described semiconductor base; By described semiconductor base and described dielectric substrate bonding, wherein said bottom electrode is contained in described groove also and between described semiconductor base exists gap; Carry out thinning from described second substrate surface to described semiconductor base, to described doped region; And form the top electrode lead-in wire being connected to described top electrode.
Preferably, the method forming described bottom electrode and described bottom electrode lead-in wire comprises: in described dielectric substrate, form electrode material layer; Patterning is carried out to described electrode material layer, to form described bottom electrode and described bottom electrode lead-in wire.
Preferably, the method forming described bottom electrode and described bottom electrode lead-in wire comprises: carry out patterning to the surface of described dielectric substrate, to form the groove pattern corresponding to described bottom electrode and described bottom electrode lead-in wire; The surface of described groove pattern and described dielectric substrate forms electrode material layer; Remove the electrode material layer beyond described groove pattern, to form described bottom electrode and described bottom electrode lead-in wire.
Preferably, described dielectric substrate is glass substrate, and/or described bottom electrode is metal electrode, and/or described Semiconductor substrate is silicon substrate.
Preferably, in described doped region doped with boron and/or phosphorus.
Preferably, the etching agent of described thinning use is potassium hydroxide solution.
Below in conjunction with accompanying drawing, describe advantages and features of the invention in detail.
Accompanying drawing explanation
In order to make advantage of the present invention be easier to understand, concise and to the point the present invention described above will be described in more detail by reference to specific embodiment illustrated in the accompanying drawings.Be appreciated that these accompanying drawings depict only exemplary embodiments of the present invention, therefore should do not think the restriction to its protection domain, described and explanation the present invention with additional characteristic and details by accompanying drawing.
Fig. 1 is the schematic diagram of capacitance pressure transducer, according to an embodiment of the invention;
Fig. 2 a is the schematic diagram that bottom electrode according to an embodiment of the invention covers on the surface of dielectric substrate;
Fig. 2 b is the schematic diagram that bottom electrode is according to another embodiment of the invention embedded in dielectric substrate;
The schematic diagram of the device obtained in the process of Fig. 3 a and 3b for making top electrode according to an embodiment of the invention; And
Fig. 4 a and 4b is for forming the schematic diagram of the device obtained in the process of resulting devices according to one embodiment of present invention by semiconductor base and dielectric substrate bonding.
Embodiment
Next, by reference to the accompanying drawings the present invention will more intactly be described, shown in the drawings of embodiments of the invention.But the present invention can implement in different forms, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiments will expose thoroughly with complete, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, in order to clear, the size in Ceng He district and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or layer time, its can directly on other elements or layer, with it adjacent, connect or be coupled to other elements or layer, or the element that can exist between two parties or layer.On the contrary, when element be called as " directly exist ... on ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other elements or layer time, then there is not element between two parties or layer.In the accompanying drawings, for the sake of clarity, the size in Ceng He district and relative size may be exaggerated.And use the element that identical Reference numeral represents identical.
The invention discloses a kind of capacitance pressure transducer, as shown in Figure 1, this capacitance pressure transducer, 100 comprises dielectric substrate 110, bottom electrode 120, Semiconductor substrate 130, top electrode 140 and top electrode lead-in wire and bottom electrode lead-in wire (not shown).Particularly, bottom electrode 120 is formed in dielectric substrate 110, for the concrete generation type of this bottom electrode 120, hereafter will discuss in detail.The first surface 131 of Semiconductor substrate 130 is formed with groove 133, and this groove 133 can carry out patterning formation by the first surface 131 of photoetching technique to Semiconductor substrate 130, and also can be formed by alternate manner, the present invention is not for being limited.This first surface 131 is relative with the bottom electrode 120 in dielectric substrate 110, and Semiconductor substrate 130 is bonded in dielectric substrate 110.It should be noted that, " relatively " mentioned in the present invention refers to both mutual opposition on direction, namely in opposite directions.Bottom electrode 120 to be contained in groove 133 and and to there is certain gap between Semiconductor substrate 130.Because bottom electrode 120 and Semiconductor substrate 130 all exist gap, therefore by dielectric substrate 110 electrical isolation on horizontal and vertical.The space formed between dielectric substrate 110 and Semiconductor substrate 130 forms capacitance cavity 150.Part (top of the groove 133 namely shown in Fig. 1) corresponding with groove 133 in Semiconductor substrate 130 is formed with doped region 140 ', and this doped region 140 ' is the top electrode 140 of capacitance pressure transducer.In addition, this capacitance pressure transducer, 100 also comprises top electrode lead-in wire (not shown) and bottom electrode lead-in wire (not shown), it is connected to top electrode 140 and bottom electrode 120 respectively, and respectively electric charge is wherein drawn with the change of Detection capacitance, its concrete connected mode is in this no limit.This capacitance pressure transducer, by being respectively formed in Semiconductor substrate and dielectric substrate by top electrode and bottom electrode, can be avoided the TSV technology of use cost costliness to isolate.And adopt the dell etching that technology of the present invention can avoid technique comparatively complicated, and then the characteristic affecting electric capacity because of etching can be avoided.In addition owing to decreasing the use of SOI substrate, the cost of manufacture of this capacitance pressure transducer, 100 can therefore be lowered.
Preferably, be formed in doped with boron and/or phosphorus in the doped region in Semiconductor substrate 130, to obtain having the top electrode 140 of doped region as this capacitance pressure transducer, of electric conductivity.The method of doping comprises thermal diffusion technology, ion implantation technique etc., and the present invention is also not intended to be limited.
Due to the cost of the SOI wafer of the upper/lower electrode as capacitance pressure transducer, that uses in prior art costly, preferably, the bottom electrode 120 in the present invention selects metal as electrode, as good conductivity, cheap aluminium, copper etc.In order to reduce costs further, dielectric substrate 110 selects glass substrate with low cost, and Semiconductor substrate 130 selects cheap silicon as substrate.Certain above-mentioned parts also can select other material, and such as Semiconductor substrate 130 selects SOI wafer, but preferred version of the present invention can cheap and realizing reaching best balance between effect of the present invention.
Continue with reference to figure 1, preferably, the bottom surface of groove 133 is 10-100 micron to the thickness of the second surface 132 of Semiconductor substrate 130, and this second surface 132 is relative with first surface 131 mentioned above.Mentioned herein to the bottom surface of groove 133 refer to when Semiconductor substrate 130 horizontal positioned being made the opening upwards of groove 133 wherein, the lower surface of the part that groove 133 is inwardly recessed.The doped region of top electrode 140 is positioned at this region, and the thickness of top electrode 140 is relevant with the thickness in this region.Second surface 132 is as the compression face of capacitance pressure transducer, 100, and when pressure is applied on top electrode 140, top electrode 140 distortion makes the capacitance of capacitance pressure transducer, 100 change, thus measures pressure.Therefore, the bottom surface of groove 133 is relevant with the range of the expectation of capacitance pressure transducer, 100 to the distance of second surface 132, therefore, those skilled in the art can reasonably select the bottom surface of groove 133 to the distance of second surface 132 according to the range expected in above-mentioned scope.
Preferably, as illustrated in figures 2 a-2b, bottom electrode 120 cover dielectric substrate 110 surface on or be embedded in dielectric substrate 110.In practice, the method covered by bottom electrode 120 on the surface of dielectric substrate 110 is generally by forming electrode material layer in this dielectric substrate 110, then utilizes photoetching technique to carry out patterning to this electrode material layer, to form bottom electrode 120.And to be embedded in dielectric substrate 110 by bottom electrode 120 be generally carry out patterning by photoetching technique to the surface of dielectric substrate 110, to form the groove pattern corresponding to bottom electrode 120; Then on the surface of this groove pattern and dielectric substrate 110, electrode material layer is formed; Remove the electrode material layer beyond this groove pattern afterwards again, to form bottom electrode 120.The preferred embodiment of the present invention manufacture craft is simple, with low cost, and can realize object of the present invention preferably.
This capacitance pressure transducer, by being respectively formed in Semiconductor substrate and dielectric substrate by top electrode and bottom electrode, can be avoided the TSV technology of use cost costliness to isolate.And adopt the dell etching that technology of the present invention can avoid technique comparatively complicated, and then the characteristic affecting electric capacity because of etching can be avoided.In addition owing to decreasing the use of SOI substrate, the cost of manufacture of this capacitance pressure transducer, 100 can therefore be lowered.
On the other hand, the invention also discloses a kind of method making above-mentioned capacitance pressure transducer, the method comprises the following steps:
First, dielectric substrate is provided.
Secondly, as illustrated in figures 2 a-2b, dielectric substrate 110 is formed bottom electrode 120 and bottom electrode lead-in wire (not shown).On the surface that this bottom electrode 120 can cover dielectric substrate 110 or be embedded in dielectric substrate 110, wherein, the concrete generation type of this bottom electrode and bottom electrode lead-in wire hereafter will be described in detail.
Then, semiconductor base is provided.
Then, as shown in Figure 3 a, at the first substrate surface 131 ' upper formation groove 133 of semiconductor base 200.The shape of this groove 133 as shown in Figure 3 a.Wherein, semiconductor base 200 is formed groove 133 and can use photoetching technique as known in the art, also can be formed by adopting alternate manner, the present invention is also not intended to be limited.
Then, with reference to figure 3b, from the side at groove 133 place, doping process is performed to this semiconductor base 200, to form doped region 140 ' in the semiconductor base 200 below groove 133.In order to reduce processing step, the mask 134 that doping process uses can for making the mask 134 that groove 133 uses.This doped region 140 ' does not arrive the second substrate surface 210 of semiconductor base, that is, there is certain distance the lower end of this doped region 140 ' to the second substrate surface 210 of semiconductor base 200.This second substrate surface 210 is relative with the first substrate surface 131 '.By performing doping process to this semiconductor base, can obtain having the doped region of electric conductivity as the top electrode 140 above mentioned.The method of doping can be thermal diffusion technology, ion implantation technique etc., and the present invention is also not intended to be limited.
Then, as shown in fig. 4 a, semiconductor base 200 and dielectric substrate 110 bonding of doped region 140 ' will be formed, in the groove 133 making bottom electrode 120 be contained in semiconductor base 200 and and there is certain gap between semiconductor base 200, the space wherein formed between bottom electrode 120 and semiconductor base 200 forms capacitance cavity 150.
Then, composition graphs 4a-4b, carries out thinning, until described doped region 140 ' from the second substrate surface 210 of semiconductor base 200 to this semiconductor base 200.This thinning method can by using etching technique conventional in this area, as etched this semiconductor substrate 200 from the second substrate surface 210 of semiconductor base 200 by use potassium hydroxide solution, the characteristic of etching solution makes when it etches into doped region 140 ' time, thinning automatic stopping, thus obtain the top electrode 140 of the good doped region 140 ' of electric conductivity as capacitance pressure transducer, of the present invention.
Finally, form top electrode lead-in wire (not shown), this top electrode lead-in wire is connected to top electrode to be drawn by electric charge wherein.
It should be noted that, make bottom electrode 120 (see Fig. 2 a-2b, comprising step) and make top electrode 140 (Fig. 3 a-3b) not order, both can carry out simultaneously, also can successively carry out.
Referring back to Fig. 2 a, according to a preferred embodiment of the present invention, the method forming bottom electrode 120 and bottom electrode lead-in wire (not shown) comprises and such as adopts known depositing operation to form electrode material layer in dielectric substrate 110, and patterning is carried out to this electrode material layer, go between with the bottom electrode forming bottom electrode 120 and be connected with this bottom electrode 120.The method of this electrode material layer being carried out to patterning is well-known in the art photoetching process, is not described in detail at this.In addition, be appreciated that bottom electrode lead-in wire needs dielectric layer, such as monox etc. on this bottom electrode lead-in wire after completing, insulate to make itself and peripheral devices.This technique can complete the making of bottom electrode and bottom electrode lead-in wire simultaneously, and technique is simple, and easily realizes.
Referring back to Fig. 2 b, according to another preferred embodiment of the present invention, the method forming bottom electrode 120 and bottom electrode lead-in wire comprises the following steps:
Patterning is carried out to the surface of dielectric substrate 110, to form the groove pattern corresponding to bottom electrode 120 and bottom electrode lead-in wire.The method of carrying out patterning to this dielectric substrate 110 is well-known in the art photoetching process, is not described in detail at this;
Known depositing operation is such as adopted to form electrode material layer in groove pattern with on the surface of dielectric substrate 110;
Remove the electrode material layer beyond groove pattern, go between with the bottom electrode forming bottom electrode 120 and be connected with bottom electrode 120.It should be noted that contact conductor needs dielectric layer, such as monox etc. on this bottom electrode lead-in wire after completing instantly, insulate to make itself and peripheral devices.This technique disposablely can complete the making of bottom electrode and bottom electrode lead-in wire equally, and technique is simple.
Preferably, be formed in the doped region 140 ' in Semiconductor substrate 200 doped with boron and/or phosphorus.The method of doping comprises thermal diffusion technology, ion implantation technique etc., and the present invention is also not intended to be limited.The doped region of doped with boron and/or phosphorus can as thinning etching stop layer in follow-up reduction process.Certainly, for the region beyond doping, also need to control etching stopping by etching time.Owing to adopting boron and/or phosphorus can make thinning automatic stopping as adulterant, therefore, it is possible to the surface configuration in controlled doping district 140 ' (see Fig. 4 b) more exactly.Further preferably, thinning used etching agent is potassium hydroxide solution.This etching agent is more responsive for the stopping arriving boron and/or phosphorus doping district 140 '.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (11)
1. a capacitance pressure transducer, comprising:
Dielectric substrate;
Bottom electrode, it is formed in described dielectric substrate;
Semiconductor substrate, the first surface of described Semiconductor substrate is formed with groove, the described first surface of described Semiconductor substrate is relative with described bottom electrode and be bonded to described dielectric substrate, and described bottom electrode to be contained in described groove and and there is gap between described Semiconductor substrate;
Top electrode, it is be formed in the doped region in Semiconductor substrate corresponding to described groove; And
Top electrode lead-in wire and bottom electrode lead-in wire, it is connected to described top electrode and described bottom electrode respectively.
2. capacitance pressure transducer, as claimed in claim 1, is characterized in that, doped with boron and/or phosphorus in described doped region.
3. capacitance pressure transducer, as claimed in claim 1, it is characterized in that, described dielectric substrate is glass substrate, and/or described bottom electrode is metal electrode, and/or described Semiconductor substrate is silicon substrate.
4. capacitance pressure transducer, as claimed in claim 1, is characterized in that, the bottom surface of described groove is 10-100 micron to the thickness of the second surface relative with described first surface of described Semiconductor substrate.
5. capacitance pressure transducer, as claimed in claim 1, is characterized in that, on the surface that described bottom electrode covers described dielectric substrate or be embedded in described dielectric substrate.
6. make a method for capacitance pressure transducer, as claimed in claim 1, described method comprises:
Dielectric substrate is provided;
Described dielectric substrate is formed bottom electrode and bottom electrode lead-in wire;
Semiconductor base is provided;
First substrate surface of described semiconductor base forms groove;
Perform doping process to form doped region in the described semiconductor base below described groove, described doped region does not arrive second substrate surface relative with described first substrate surface of described semiconductor base;
By described semiconductor base and described dielectric substrate bonding, wherein said bottom electrode is contained in described groove also and between described semiconductor base exists gap;
Carry out thinning from described second substrate surface to described semiconductor base, to described doped region; And
Form the top electrode lead-in wire being connected to described top electrode.
7. method as claimed in claim 6, is characterized in that, the method forming described bottom electrode and described bottom electrode lead-in wire comprises:
Described dielectric substrate forms electrode material layer;
Patterning is carried out to described electrode material layer, to form described bottom electrode and described bottom electrode lead-in wire.
8. method as claimed in claim 6, is characterized in that, the method forming described bottom electrode and described bottom electrode lead-in wire comprises:
Patterning is carried out to the surface of described dielectric substrate, to form the groove pattern corresponding to described bottom electrode and described bottom electrode lead-in wire;
The surface of described groove pattern and described dielectric substrate forms electrode material layer;
Remove the electrode material layer beyond described groove pattern, to form described bottom electrode and described bottom electrode lead-in wire.
9. method as claimed in claim 6, it is characterized in that, described dielectric substrate is glass substrate, and/or described bottom electrode is metal electrode, and/or described Semiconductor substrate is silicon substrate.
10. method as claimed in claim 6, is characterized in that, doped with boron and/or phosphorus in described doped region.
11. methods as claimed in claim 10, is characterized in that, the etching agent of described thinning use is potassium hydroxide solution.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410196810.9A CN105092111A (en) | 2014-05-09 | 2014-05-09 | Capacitive pressure sensor and manufacturing method thereof |
| PCT/CN2015/078525 WO2015169249A1 (en) | 2014-05-09 | 2015-05-08 | Capacitive pressure sensor and manufacturing method therefor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410196810.9A CN105092111A (en) | 2014-05-09 | 2014-05-09 | Capacitive pressure sensor and manufacturing method thereof |
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| CN105092111A true CN105092111A (en) | 2015-11-25 |
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| CN201410196810.9A Pending CN105092111A (en) | 2014-05-09 | 2014-05-09 | Capacitive pressure sensor and manufacturing method thereof |
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| WO (1) | WO2015169249A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105784212A (en) * | 2016-03-25 | 2016-07-20 | 深圳安培龙科技股份有限公司 | Ceramic capacitive pressure sensor and preparation method thereof |
| CN107463867A (en) * | 2016-06-03 | 2017-12-12 | 上海丽恒光微电子科技有限公司 | Sensor and preparation method thereof |
| WO2024145728A1 (en) * | 2023-01-03 | 2024-07-11 | 京东方科技集团股份有限公司 | Pressure sensor, manufacturing method therefor and pressure measuring device |
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| CN106959176B (en) * | 2017-05-10 | 2019-06-07 | 江西科技师范大学 | A kind of pliable pressure sensor and preparation method thereof |
| CN107830966B (en) * | 2017-12-05 | 2023-08-29 | 苏州科技大学 | MEMS gas pressure sensor and manufacturing process thereof |
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| Publication number | Publication date |
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| WO2015169249A1 (en) | 2015-11-12 |
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