WO2015169249A1

WO2015169249A1 - Capacitive pressure sensor and manufacturing method therefor

Info

Publication number: WO2015169249A1
Application number: PCT/CN2015/078525
Authority: WO
Inventors: 苏佳乐
Original assignee: 无锡华润上华半导体有限公司
Priority date: 2014-05-09
Filing date: 2015-05-08
Publication date: 2015-11-12
Also published as: CN105092111A

Abstract

A capacitive pressure sensor (100), comprising: an insulating substrate (110); a lower electrode (120) which is formed on the insulating substrate (110); a semiconductor substrate (130), wherein a groove (133) is formed on a first surface (131) of the semiconductor substrate, the first surface (131) of the semiconductor substrate (130) is opposite to the lower electrode (120) and is bonded to the insulating substrate (110), and the lower electrode (120) is accommodated in the groove (133) and is separated from the semiconductor substrate (130) by a gap; an upper electrode (140) which is formed in a doping region (140') in the semiconductor substrate (130) corresponding to the groove (133); an upper electrode leading wire which is connected to the upper electrode (140); and a lower electrode leading wire which is connected to the lower electrode (120). Also provided is a manufacturing method for the capacitive pressure sensor (100).

Description

Capacitive pressure sensor and manufacturing method thereof

[Technical Field]

The present invention relates to the field of sensors, and more particularly to a capacitive pressure sensor and a method of fabricating the same.

【Background technique】

At present, there is a capacitive pressure sensor that forms a capacitor cavity by bonding two SOI wafers, and the upper and lower electrodes are each formed of silicon. However, there are many drawbacks to fabricating a capacitive pressure sensor by this method. First, the deep pit etching process used in this technology is very complicated, and the characteristics of the capacitor are easily affected by the etching cavity to cause drift. Second, due to the high cost of the SOI wafer, the manufacturing cost of such a capacitive pressure sensor is increased. And also need to use through silicon vias (Through Silicon Via, TSV) technology is isolated, and the technology is costly.

[Summary of the Invention]

In view of this, it is necessary to provide a capacitive pressure sensor with a simple process and a low cost and a manufacturing method thereof.

A capacitive pressure sensor comprising: an insulating substrate; a lower electrode formed on the insulating substrate; a semiconductor substrate having a first surface and having a recess formed on the first surface, the semiconductor The first surface of the substrate is opposite to the lower electrode and bonded to the insulating substrate, and the lower electrode is received in the recess and has a gap with the semiconductor substrate; an upper electrode a doped region formed in a corresponding semiconductor substrate of the recess; an upper electrode lead connected to the upper electrode; and a lower electrode lead connected to the lower electrode.

A method of fabricating the above capacitive pressure sensor, the method comprising: providing an insulating substrate; forming a lower electrode and a lower electrode lead on the insulating substrate; providing a semiconductor substrate, the semiconductor substrate having a first substrate surface and a second substrate surface opposite the first substrate surface; forming a groove on the first substrate surface of the semiconductor substrate; performing a doping process to form a doped region in the semiconductor substrate under the recess The doped region does not reach the second substrate surface of the semiconductor substrate; the semiconductor substrate is bonded to the insulating substrate, wherein the lower electrode is received in the recess and with the semiconductor substrate There is a gap therebetween; the semiconductor substrate is thinned from the second substrate surface to the doped region; and an upper electrode lead connected to the upper electrode is formed.

The capacitive pressure sensor can avoid the use of expensive TSV technology for isolation by forming the upper and lower electrodes on the semiconductor substrate and the insulating substrate, respectively. Moreover, the technique can avoid deep pit etching with complicated process, thereby avoiding the influence of capacitance on the characteristics of the capacitor. In addition, since the use of the SOI substrate is reduced, the manufacturing cost of the capacitive pressure sensor 100 can be reduced.

[Description of the Drawings]

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present invention, and those skilled in the art can obtain drawings of other embodiments according to the drawings without any creative work.

Figure 1a is a schematic illustration of a capacitive pressure sensor in accordance with one embodiment;

1b is a flow chart showing the steps of a method of fabricating a capacitive pressure sensor according to an embodiment;

2a is a schematic view of a lower electrode overlying a surface of an insulating substrate, in accordance with one embodiment;

2b is a schematic view of a lower electrode embedded in an insulating substrate according to another embodiment;

3a and 3b are schematic illustrations of devices obtained during the fabrication of an upper electrode, in accordance with one embodiment;

4a and 4b are schematic illustrations of devices obtained during bonding of a semiconductor substrate to an insulating substrate to form a final device, in accordance with one embodiment.

【detailed description】

The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

As shown in FIG. 1a, a capacitive pressure sensor 100 of an embodiment includes an insulating substrate 110, a lower electrode 120, a semiconductor substrate 130, an upper electrode 140, and upper and lower electrode leads (not shown). Specifically, the lower electrode 120 is formed on the insulating substrate 110, and the specific formation of the lower electrode 120 will be discussed in detail below. A recess 133 is formed on the first surface 131 of the semiconductor substrate 130. The recess 133 may be formed by patterning the first surface 131 of the semiconductor substrate 130 by a photolithography technique, or may be formed by other methods. Do not want to limit it. The first surface 131 is opposed to the lower electrode 120 on the insulating substrate 110, and the semiconductor substrate 130 is bonded on the insulating substrate 110. It should be noted that the “relative” mentioned in the embodiment refers to the mutual opposition between the two, that is, the opposite direction. The lower electrode 120 is housed in the recess 133 and has a certain gap with the semiconductor substrate 130. Since the lower electrode 120 and the semiconductor substrate 130 have a gap in both the lateral direction and the longitudinal direction, they can be electrically insulated by the insulating substrate 110. A space formed between the insulating substrate 110 and the semiconductor substrate 130 constitutes a capacitor cavity 150. A portion of the semiconductor substrate 130 corresponding to the recess 133 (i.e., above the recess 133 shown in FIG. 1a) is formed with a doped region 140', which is the upper electrode of the capacitive pressure sensor. 140. In addition, the capacitive pressure sensor 100 further includes an upper electrode lead (not shown) and a lower electrode lead (not shown) connected to the upper electrode 140 and the lower electrode 120, respectively, and respectively extracts charges therein to detect capacitance. Changes, the specific connection method is not limited herein. The capacitive pressure sensor can avoid the use of expensive TSV technology for isolation by forming the upper and lower electrodes on the semiconductor substrate and the insulating substrate, respectively. Moreover, the technique of the embodiment can avoid the deep pit etching with complicated process, and the characteristics of the capacitor affected by the etching can be avoided. In addition, since the use of the SOI substrate is reduced, the manufacturing cost of the capacitive pressure sensor 100 can be reduced.

In an embodiment, the doped regions formed in the semiconductor substrate 130 are doped with boron and/or phosphorus to obtain a doped region having conductivity as the upper electrode 140 of the capacitive pressure sensor. Methods of doping include thermal diffusion techniques, ion implantation techniques, and the like, and the invention is not intended to be limiting.

Since the SOI wafer as the upper and lower electrodes of the capacitive pressure sensor used in the prior art is relatively expensive, in one embodiment, the lower electrode 120 is made of a metal as an electrode, such as aluminum, copper, etc. which are electrically conductive and inexpensive. In order to further reduce the cost, the insulating substrate 110 is made of a low cost glass substrate, and the semiconductor substrate 130 is made of inexpensive silicon as a substrate. Of course, other materials may be used for the above components. For example, the semiconductor substrate 130 may be an SOI wafer, but in another embodiment, the best balance between inexpensiveness and achieving the effects of the invention can be achieved.

With continued reference to FIG. 1a, in one embodiment, the bottom surface of the recess 133 has a thickness of 10 to 100 microns to the second surface 132 of the semiconductor substrate 130, the second surface 132 and the first surface 131 described above. relatively. The bottom surface of the groove 133 mentioned here refers to the lower surface of the portion where the groove 133 is recessed inward when the semiconductor substrate 130 is horizontally placed such that the opening of the groove 133 thereof is upward. The doped region of the upper electrode 140 is located in this region, and the thickness of the upper electrode 140 is related to the thickness of the region. The second surface 132 serves as a pressure receiving surface of the capacitive pressure sensor 100. When pressure is applied to the upper electrode 140, the upper electrode 140 is deformed so that the capacitance value of the capacitive pressure sensor 100 is changed, thereby measuring the pressure. Therefore, the distance from the bottom surface of the recess 133 to the second surface 132 is related to the desired range of the capacitive pressure sensor 100. Therefore, those skilled in the art can reasonably select the bottom surface of the recess 133 within the above range according to the desired range. The distance to the second surface 132.

In an embodiment, as shown in FIGS. 2a-2b, the lower electrode 120 overlies the surface of the insulating substrate 110 or is embedded within the insulating substrate 110. In practice, the method of covering the lower electrode 120 on the surface of the insulating substrate 110 is generally performed by forming an electrode material layer on the insulating substrate 110, and then patterning the electrode material layer by photolithography to form a lower layer. Electrode 120. While the lower electrode 120 is embedded in the insulating substrate 110, the surface of the insulating substrate 110 is generally patterned by photolithography to form a groove pattern corresponding to the lower electrode 120; then the groove pattern and the insulating liner are An electrode material layer is formed on the surface of the bottom 110; then the electrode material layer other than the groove pattern is removed to form the lower electrode 120. The manufacturing process of the present embodiment is simple, the cost is low, and the object of the embodiment can be better achieved.

The capacitive pressure sensor can avoid the use of expensive TSV technology for isolation by forming the upper and lower electrodes on the semiconductor substrate and the insulating substrate, respectively. Moreover, the technique of the embodiment can avoid the deep pit etching with complicated process, and the characteristics of the capacitor affected by the etching can be avoided. In addition, since the use of the SOI substrate is reduced, the manufacturing cost of the capacitive pressure sensor 100 can be reduced.

On the other hand, an embodiment also discloses a method for manufacturing the above capacitive pressure sensor. Referring to FIG. 1b, the method includes the following steps:

S1: providing an insulating substrate;

S2: forming a lower electrode and a lower electrode lead on the insulating substrate;

S3: providing a semiconductor substrate having a first substrate surface and a second substrate surface opposite the first substrate surface;

S4: forming a groove on a surface of the first substrate of the semiconductor substrate;

S5: performing a doping process to form a doped region in the semiconductor substrate under the recess, the doped region not reaching a second substrate surface of the semiconductor substrate;

S6: bonding the semiconductor substrate to the insulating substrate, wherein the lower electrode is received in the recess and has a gap with the semiconductor substrate;

S7: thinning the semiconductor substrate from the surface of the second substrate to the doped region;

S8: forming an upper electrode lead connected to the upper electrode.

In another embodiment, the method of the capacitive pressure sensor comprises the steps of:

First, an insulating substrate is provided.

Next, as shown in FIGS. 2a-2b, a lower electrode 120 and a lower electrode lead (not shown) are formed on the insulating substrate 110. The lower electrode 120 may be overlaid on the surface of the insulating substrate 110 or embedded in the insulating substrate 110, wherein the specific formation of the lower electrode and the lower electrode lead will be described in detail below.

Then, a semiconductor substrate is provided.

Next, as shown in Fig. 3a, a groove 133 is formed on the first substrate surface 131' of the semiconductor substrate 200. The shape of the groove 133 is as shown in Fig. 3a. Wherein, the formation of the recesses 133 on the semiconductor substrate 200 may be performed using photolithographic techniques known in the art, or may be formed by other means, and the invention is not intended to be limited thereto.

Then, referring to FIG. 3b, a doping process is performed on the semiconductor substrate 200 from the side where the recess 133 is located to form a doped region 140' in the semiconductor substrate 200 under the recess 133. To reduce the number of process steps, the mask 134 used in the doping process can be the mask 134 used to make the recesses 133. The doped region 140' does not reach the second substrate surface 210 of the semiconductor substrate, i.e., the lower end of the doped region 140' has a certain distance from the second substrate surface 210 of the semiconductor substrate 200. The second substrate surface 210 is opposite the first substrate surface 131'. By performing a doping process on the semiconductor substrate, a doped region having conductivity can be obtained as the upper electrode 140 mentioned above. The doping method may be a thermal diffusion technique, an ion implantation technique, or the like, and the invention is not intended to be limited thereto.

Next, as shown in FIG. 4a, the semiconductor substrate 200 on which the doped region 140' is formed is bonded to the insulating substrate 110 such that the lower electrode 120 is housed in the recess 133 of the semiconductor substrate 200 and exists between the semiconductor substrate 200. A certain gap in which the space formed between the lower electrode 120 and the semiconductor substrate 200 constitutes the capacitance cavity 150.

Then, in conjunction with Figures 4a-4b, the semiconductor substrate 200 is thinned from the second substrate surface 210 of the semiconductor substrate 200 up to the doped region 140'. The method of thinning can be performed by etching the semiconductor substrate 200 from the second substrate surface 210 of the semiconductor substrate 200 by using an etching technique commonly used in the art, such as by using a potassium hydroxide solution. When the doping region 140' is etched, the thinning is automatically stopped, thereby obtaining a doping region 140' having good conductivity as the upper electrode 140 of the capacitive pressure sensor of the present embodiment.

Finally, an upper electrode lead (not shown) is formed, which is connected to the upper electrode to draw the charge therein.

It should be noted that the fabrication of the lower electrode 120 (see FIGS. 2a-2b, including the steps) and the fabrication of the upper electrode 140 (FIGS. 3a-3b) are not sequential, and the two may be performed simultaneously or sequentially.

Referring back to FIG. 2a, in accordance with an embodiment, a method of forming a lower electrode 120 and a lower electrode lead (not shown) includes forming an electrode material layer on the insulating substrate 110, for example, using a known deposition process, and layering the electrode material Patterning is performed to form the lower electrode 120 and the lower electrode lead connected to the lower electrode 120. The method of patterning the electrode material layer is a photolithography process well known in the art and will not be described in detail herein. In addition, it can be understood that after the fabrication of the lower electrode lead is completed, a dielectric layer such as silicon oxide or the like is deposited on the lower electrode lead to insulate it from the surrounding device. The process can simultaneously complete the fabrication of the lower electrode and the lower electrode lead, and the process is simple and easy to implement.

Referring back to FIG. 2b, a method of forming the lower electrode 120 and the lower electrode lead includes the following steps, according to an embodiment:

The surface of the insulating substrate 110 is patterned to form groove patterns corresponding to the lower electrode 120 and the lower electrode lead. The method of patterning the insulating substrate 110 is a photolithography process well known in the art and will not be described in detail herein;

Forming an electrode material layer in the groove pattern and on the surface of the insulating substrate 110, for example, using a known deposition process;

The electrode material layer other than the groove pattern is removed to form the lower electrode 120 and the lower electrode lead connected to the lower electrode 120. It should be noted that a dielectric layer such as silicon oxide or the like needs to be deposited on the lower electrode lead after the lower electrode lead is formed to insulate it from the surrounding device. The process can also complete the fabrication of the lower electrode and the lower electrode lead in one operation, and the process is simple.

In an embodiment, the doped regions 140' formed in the semiconductor substrate 200 are doped with boron and/or phosphorus. Methods of doping include thermal diffusion techniques, ion implantation techniques, and the like, and the invention is not intended to be limiting. The doped regions doped with boron and/or phosphorus may serve as a thinned etch stop layer in a subsequent thinning process. Of course, for regions other than doping, it is also necessary to control the etching stop by etching time. Since the thinning can be automatically stopped by using boron and/or phosphorus as a dopant, the surface shape of the doped region 140' (see Fig. 4b) can be controlled more accurately. In still another embodiment, the etchant used for thinning is a potassium hydroxide solution. The etchant is more sensitive to the cessation of reaching the boron and/or phosphorus doped regions 140'.

The present invention has been described by the above-described embodiments, but it should be understood that the above-described embodiments are only for the purpose of illustration and description. Further, those skilled in the art can understand that the present invention is not limited to the above embodiments, and various modifications and changes can be made according to the teachings of the present invention. These modifications and modifications are all claimed in the present invention. Within the scope. The scope of the invention is defined by the appended claims and their equivalents.

Claims

A capacitive pressure sensor comprising:

Insulating substrate

a lower electrode formed on the insulating substrate;

a semiconductor substrate having a first surface and having a recess formed on the first surface, the first surface of the semiconductor substrate being opposite to the lower electrode and bonded to the insulating substrate, and The lower electrode is housed in the recess and has a gap with the semiconductor substrate;

An upper electrode, which is a doped region formed in a corresponding semiconductor substrate of the recess;

An upper electrode lead connected to the upper electrode;

A lower electrode lead is connected to the lower electrode.
The capacitive pressure sensor of claim 1 wherein said doped region is doped with boron and/or phosphorus.
A capacitive pressure sensor according to claim 1, wherein said insulating substrate is a glass substrate.
The capacitive pressure sensor according to claim 1, wherein said lower electrode is a metal electrode.
The capacitive pressure sensor of claim 1 wherein said semiconductor substrate is a silicon substrate.
The capacitive pressure sensor according to claim 1, wherein said semiconductor substrate has a second surface opposite said first surface, and a thickness of said bottom surface to said second surface of said groove is 10 -100 microns.
The capacitive pressure sensor according to claim 1, wherein said lower electrode covers or is embedded in a surface of said insulating substrate.
A method of making a capacitive pressure sensor, the method comprising:

Providing an insulating substrate;

Forming a lower electrode and a lower electrode lead on the insulating substrate;

Providing a semiconductor substrate having a first substrate surface and a second substrate surface opposite the first substrate surface;

Forming a groove on a surface of the first substrate of the semiconductor substrate;

Performing a doping process to form a doped region in the semiconductor substrate under the recess, the doped region not reaching a second substrate surface of the semiconductor substrate;

Bonding the semiconductor substrate to the insulating substrate, wherein the lower electrode is received in the recess and has a gap with the semiconductor substrate;

Thinning the semiconductor substrate from the surface of the second substrate to the doped region;

An upper electrode lead connected to the upper electrode is formed.
The method of claim 8 wherein the method of forming the lower electrode and the lower electrode lead comprises:

Forming an electrode material layer on the insulating substrate;

The electrode material layer is patterned to form the lower electrode and the lower electrode lead.
The method of claim 8 wherein the method of forming the lower electrode and the lower electrode lead comprises:

Patterning a surface of the insulating substrate to form a groove pattern corresponding to the lower electrode and the lower electrode lead;

Forming an electrode material layer on the groove pattern and a surface of the insulating substrate;

An electrode material layer other than the groove pattern is removed to form the lower electrode and the lower electrode lead.
The method of claim 8 wherein said insulating substrate is a glass substrate.
The method of claim 8 wherein said lower electrode is a metal electrode.
The method of claim 8 wherein said semiconductor substrate is a silicon substrate.
The method of claim 8 wherein said doped regions are doped with boron and/or phosphorus.
The method of claim 14 wherein said etchant used for thinning is a potassium hydroxide solution.