CN113845084A

CN113845084A - Capacitive pressure sensor and manufacturing method thereof

Info

Publication number: CN113845084A
Application number: CN202010599056.9A
Authority: CN
Inventors: 苏佳乐; 周国平; 张新伟; 夏长奉
Original assignee: CSMC Technologies Fab2 Co Ltd
Current assignee: CSMC Technologies Fab2 Co Ltd; CSMC Technologies Corp
Priority date: 2020-06-28
Filing date: 2020-06-28
Publication date: 2021-12-28
Also published as: WO2022001029A1

Abstract

The invention discloses a capacitance pressure sensor and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: providing a semiconductor substrate, and forming an injection layer on the semiconductor substrate; sequentially forming an oxide layer and a top silicon layer on the injection layer; etching the top silicon layer to form a deep groove matrix; etching the oxide layer to form a cavity; the top silicon layer is formed into a continuous silicon film to seal the cavity. The invention adopts the silicon migration technology for sealing to form a continuous and sealed upper electrode, and utilizes the deep groove as the release hole in the cavity forming process, thereby having simple process and higher efficiency, and greatly improving the productivity and the reliability.

Description

Capacitive pressure sensor and manufacturing method thereof

Technical Field

The invention relates to the field of semiconductors, in particular to a capacitive pressure sensor and a manufacturing method thereof.

Background

With the popularization of smart phones, MEMS pressure sensors have been widely developed.

The known capacitive pressure sensor mostly adopts a structure of polysilicon-sacrificial layer-polysilicon, in the process of manufacturing the existing capacitive pressure sensor, a two-layer polysilicon structure is often required to be released, and the sacrificial layer is required to be corroded, however, the polysilicon layer often has residual stress, warping is easy to occur after the release, the electrode performance is difficult to guarantee, the mechanical property of the polysilicon has a larger difference compared with that of the monocrystalline silicon, and on the other hand, the corrosion release time of the sacrificial layer is long, and the mass production is not facilitated.

To solve the above problems, the present invention provides a capacitive pressure sensor and a method for manufacturing the same.

Disclosure of Invention

In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

In order to overcome the problems existing at present, the invention provides, in a first aspect, a method for manufacturing a capacitive pressure sensor, comprising the steps of:

providing a semiconductor substrate, and forming an injection layer on the semiconductor substrate;

sequentially forming an oxide layer and a top silicon layer on the injection layer;

etching the top silicon layer to form a deep groove matrix exposing the oxide layer;

etching the oxide layer to form a cavity;

the top silicon layer is formed into a continuous silicon film to seal the cavity.

Illustratively, the method further comprises a top silicon layer thinning step after the step of sequentially forming the oxide layer and the top silicon layer on the injection layer and before the step of etching the top silicon layer to form the deep groove matrix.

Illustratively, the thickness of the oxide layer is the distance between two plates of the capacitive pressure sensor.

Illustratively, the critical dimension of the deep groove matrix is 0.6-1um and/or the distance between the deep grooves in the deep groove matrix is 0.6-1 um.

Illustratively, forming the top silicon layer into a continuous silicon film to seal the cavity includes a high temperature annealing step that causes silicon to migrate to form the top silicon layer into a continuous silicon film.

Illustratively, the method further comprises an electrode terminal forming step, wherein the electrode terminal comprises an upper electrode terminal and/or a lower electrode terminal.

Illustratively, the electrode terminal forming step includes an etching step including etching the top silicon layer to expose the oxide layer, etching the oxide layer to form an opening portion, and forming the lower electrode terminal in the opening portion.

Illustratively, the deep trench matrix serves as a release hole for the step of etching the oxide layer to form the cavity.

Illustratively, the oxide layer is a silicon oxide layer.

The second aspect of the invention also provides a capacitive pressure sensor prepared by the manufacturing method.

The continuous and closed upper electrode is formed by sealing by using a silicon migration technique. And the deep groove is used as a release hole in the cavity forming process, the process is simple, the efficiency is high, and the productivity and the reliability can be greatly improved.

Drawings

The following drawings of the invention are included to provide a further understanding of the invention. There are shown in the drawings, embodiments and descriptions thereof, which are used to explain the principles and apparatus of the invention. In the drawings, there is shown in the drawings,

FIG. 1 is a schematic diagram of a first step in the formation of a capacitive pressure sensor in accordance with one embodiment of the present invention;

FIG. 2 is a schematic diagram of a second step in the capacitive pressure sensor according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a third step in a capacitive pressure sensor in accordance with one embodiment of the present invention;

FIG. 4 is a schematic diagram of a fourth step in a capacitive pressure sensor in accordance with one embodiment of the present invention;

FIG. 5 is a schematic diagram of a fifth step in the formation of a capacitive pressure sensor in accordance with one embodiment of the present invention;

FIG. 6 is a schematic diagram of a sixth step in the capacitive pressure sensor, according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a seventh step in the formation of a capacitive pressure sensor in accordance with one embodiment of the present invention;

fig. 8 is a schematic structural diagram of a capacitive pressure sensor formed in an eighth step according to an embodiment of the present invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.

In order to provide a thorough understanding of the present invention, detailed steps and detailed structures will be set forth in the following description in order to explain the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.

The invention provides a manufacturing method of a capacitance pressure sensor, aiming at solving the problems in the prior art, and the manufacturing method comprises the following steps:

etching the oxide layer to form a cavity; the top silicon layer is formed into a continuous silicon film to seal the cavity.

The capacitive pressure sensor is manufactured by using an SON (silicon oxide nitride) process, and the capacitive pressure sensor is sealed by adopting a silicon migration technology to form a continuous and sealed upper electrode. The upper electrode forms a continuous silicon film, the mechanical property is superior to that of a polycrystalline silicon film, the residual stress can be greatly reduced, and the warpage after release is avoided, so that the good electrode performance is ensured. And the deep groove is used as a release hole in the cavity forming process, so that the oxide layer is etched more quickly, compared with the method that a small number of holes are formed at the edge to be used as release holes, the efficiency of the process is greatly improved, and meanwhile, the productivity is greatly improved. Compared with the traditional mode, the method for manufacturing the capacitive pressure sensor is simple in process and high in reliability.

Among them, the SON (Silicon-on-Nothing) process is an advanced hybrid technology developed for small-sized CMOS. The SON forms a localized silicon-on-insulator under the channel through an "air-bridge" structure. A hollow is formed under the gate stack by preferentially etching the thin epitaxial layer, and the hollow can be an air gap or filled with an oxide. SON is self-aligned under the channel in device fabrication. In some cases, bulk silicon can be used as the starting wafer instead of the more expensive SOI substrate, greatly reducing device cost.

The process of fabricating a capacitive pressure sensor by using the SON process according to the present invention will be described with reference to fig. 1 to 8, wherein fig. 1 is a schematic structural diagram of a capacitive pressure sensor formed in a first step according to an embodiment of the present invention; FIG. 2 is a schematic diagram of a second step in the capacitive pressure sensor according to an embodiment of the present invention; FIG. 3 is a schematic diagram of a third step in a capacitive pressure sensor in accordance with one embodiment of the present invention; FIG. 4 is a schematic diagram of a fourth step in a capacitive pressure sensor in accordance with one embodiment of the present invention; FIG. 5 is a schematic diagram of a fifth step in the formation of a capacitive pressure sensor in accordance with one embodiment of the present invention; FIG. 6 is a schematic diagram of a sixth step in the capacitive pressure sensor, according to an embodiment of the present invention; FIG. 7 is a schematic diagram of a seventh step in the formation of a capacitive pressure sensor in accordance with one embodiment of the present invention; fig. 8 is a schematic structural diagram of a capacitive pressure sensor formed in an eighth step according to an embodiment of the present invention.

As shown in fig. 1, which is a schematic structural diagram formed in the first step of the capacitive pressure sensor, through step 101: a doping implantation is performed on the substrate 110 to form an implanted layer 120 to serve as a lower electrode of the capacitive pressure sensor. Illustratively, the resistivity of the injection layer 120 is less than 0.01 ohm/cm.

Wherein, in the invention, the semiconductor substrate can be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. In some cases, the silicon substrate may be selected to be a bulk silicon substrate, which can greatly reduce device cost.

The implantation layer 120 is a heavily doped implantation, which may be an ion implantation or an atom implantation, for example.

In other embodiments, the implantation layer 120 may also be lightly doped, which is not limited in the present invention.

Illustratively, phosphorus or arsenic or the like may be doped, for example, by passing a gas containing phosphorus or arsenic.

The concentration of doping atoms or ions has a great influence on the material properties, and the doping by vapor deposition or ion beam sputtering can be selected during the implantation of the substrate.

As shown in fig. 2, which is a schematic diagram of a structure formed in the second step of the capacitive pressure sensor, through step 102: an oxide layer 130 is formed, as well as a top silicon layer 140.

Wherein the thickness of the oxide layer 130 is the distance between the two plates of the capacitive pressure sensor.

Illustratively, the oxide layer may be selected as a BOX layer, and specifically, a constituent material thereof may include silicon oxide (SiOx), the oxide layer is formed to prepare for the subsequent formation of a cavity, and an opening portion of an electrode is formed using a portion of the oxide layer so that the subsequently formed electrode portion can be in contact with the implantation layer 120.

The oxide layer may be a thermal oxide layer, a nitrogen oxide layer, a chemical oxide layer, or other suitable thin film layer. Also, the oxide layer may be formed, for example, by a suitable process such as thermal oxidation, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or Physical Vapor Deposition (PVD).

Illustratively, after the top silicon layer 140 is bonded to the oxide layer 130, a thinning step is further included, for example, the top silicon layer 140 is polished to 1-3 um.

The top silicon layer may be selected from a single crystal silicon layer or a polycrystalline silicon layer, and may be formed by an appropriate process such as epitaxy, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or Physical Vapor Deposition (PVD).

Wherein, the thinning step can select a physical thinning method or a chemical thinning method. Specifically, in the physical thinning process, a grinding machine can be selected for thinning, and specifically, carborundum grinding can be adopted. In the chemical thinning process, a mixed acid liquid may be used to achieve chemical thinning of the top silicon layer, and for example, the mixed liquid may be a hydrofluoric acid solution, such as a diluted hydrofluoric acid solution (DHF), a Buffered Oxide Etchant (BOE), or a buffered hydrofluoric acid (BHF).

As shown in fig. 3, which is a schematic structural diagram formed in the third step of the capacitive pressure sensor, through step 103: the deep trench matrix 150 is etched.

Illustratively, the Critical Dimension (CD) of the etched deep trench matrix may be 0.6 to 1um with a pitch of 0.6 to 1um using the patterned photoresist as a mask.

Wherein a suitable dry etch may be used to remove portions of the top silicon layer 140 to form the deep trench matrix 150.

For example, physical etching, chemical etching, or physicochemical etching may be selected. Wherein physical etching is also called sputter etching. Among them, Reactive Ion Etching (RIE) and high density plasma Etching (HDP) can be selected. The etching is carried out by the double functions of physical bombardment and chemical reaction of active ions on the substrate, and the advantages of good anisotropy and selectivity are achieved.

Illustratively, the deep trench matrix may also be selectively implemented using a plasma etch that etches the top silicon layer 140 at different rates. And the deep groove matrix can be quickly formed by selecting the optimal etching ratio.

As shown in fig. 4, which is a schematic structural diagram formed in the fourth step of the capacitive pressure sensor, through step 104: the oxide layer 130 is etched to form a continuous cavity 160.

Illustratively, a self-aligned mask may be formed by using the deep trench matrix formed in the oxide layer, and a suitable dry etching method or wet etching method may be used to remove a portion of the oxide layer 130, wherein preferably, a wet etching method may be used to remove a portion of the oxide layer 130.

Wherein a suitable dry etch may be used to remove portions of the oxide layer 130 to form the continuous cavity 160.

Illustratively, the continuous cavity 160 may also be selectively implemented using plasma etching.

In the invention, a SON process is combined, a deep groove matrix, also called a TRENCH matrix, is formed in the step 103, so that in the step 104, the deep groove matrix is taken as a release hole, the speed of etching the oxide layer is greatly accelerated, compared with the method that a small number of holes are formed at the edge of the release hole, the efficiency of the process is very high, and the productivity is greatly improved.

As shown in fig. 5, which is a schematic structural diagram formed in the fifth step of the capacitive pressure sensor, through step 105: high temperature annealing seals the cavity by allowing the top silicon to form a continuous silicon film 150 by silicon migration.

For example, when the top silicon is silicon, the seed layer formed by migration is single crystal silicon, and the epitaxial layer formed after epitaxy is still single crystal structure. In this step the top silicon with holes is migrated to form cavities by an annealing process performed in a non-oxygen atmosphere, for example, in the middle of hydrogen, nitrogen or other inert gas. The annealing temperature is greater than 800 ℃.

For example, the annealing process conditions are: reaction gas: hydrogen gas; reaction temperature: 800 ℃ to 1200 ℃, for example about 1000 ℃.

In the step, the silicon migration technology is adopted for sealing, the upper electrode forms a continuous silicon film, the mechanical property is superior to that of a polycrystalline silicon film, the residual stress can be greatly reduced, the warping after the release is avoided, and therefore the good electrode performance is guaranteed.

Therefore, compared with the traditional mode, the capacitive pressure sensor is simple in process and high in reliability.

As shown in fig. 6, which is a schematic structural diagram formed in the sixth step of the capacitive pressure sensor, through step 106: etching the top silicon layer 140 exposes the oxide layer 130.

Wherein the exposed oxide layer is a portion of the oxide layer 130.

Illustratively, a patterned masking layer, such as a photoresist layer, is formed on the oxide layer 130, and then the oxide layer 130 is etched using the masking layer as a mask.

In the step, hydrofluoric acid HF or diluted hydrofluoric acid DHF is selected for etching, wherein the composition of HF: H2O is 1:2-1:10, and the etching temperature is 20-25 ℃.

As shown in fig. 7, which is a schematic structural diagram formed in the seventh step of the capacitive pressure sensor, through step 107: and etching the oxide layer on the lower electrode.

Wherein the oxide layer 130 on the lower electrode is etched to form an opening. Wherein the lower electrode is an injection layer 120.

Illustratively, a patterned mask layer, such as a photoresist layer, is formed on the oxide layer 130, and then the oxide layer 130 is etched using the mask layer as a mask to form an opening. The patterned oxide layer can also be used as a self-aligned mask to perform the etching step, which can better reduce the complexity and cost of the process because no additional photoresist layer is needed.

As shown in fig. 8, which is a schematic structural diagram formed in the eighth step of the capacitive pressure sensor, through step 108: aluminum is deposited and electrode terminals are formed.

Wherein aluminum electrode terminals are formed on the upper electrode and the lower electrode, respectively.

Illustratively, the upper electrode tip 160 is formed on the surface of the top silicon layer 140, and the lower electrode tip 170 is formed in the opening formed in step 107.

Illustratively, the lower electrode terminal 170 contacts the injection layer 120 to achieve electrical connection.

The forming method of the upper electrode terminal and the lower electrode terminal may be a method commonly used in the art, and is not described herein again.

In summary, the sealing is performed by using the silicon migration technique to form a continuous and sealed upper electrode in combination with the characteristics of the SON process. The upper electrode forms a continuous silicon film, the mechanical property is superior to that of a polycrystalline silicon film, the residual stress can be greatly reduced, and the warpage after release is avoided, so that the good electrode performance is ensured. And, SON technology need do TRENCH's matrix, and the deep trouth is as the release hole in cavity formation process, therefore it is faster to etch the oxide layer, compares and opens a small amount of holes at the edge and does the release hole, and the efficiency of technology is very high, very big promotion productivity. Compared with the traditional mode, the method for manufacturing the capacitive pressure sensor is simple in process and high in reliability.

The invention also provides the capacitive pressure sensor prepared by the method.

Since the semiconductor device of the present invention is manufactured by the aforementioned method, it has the same advantages as the aforementioned embodiment.

The invention further provides an electronic device which comprises the capacitive pressure sensor, wherein the capacitive pressure sensor is prepared according to the method.

The electronic device of this embodiment may be any electronic product or device, such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, and the like, and may also be any intermediate product including a circuit. The electronic device of the embodiment of the invention has better performance due to the use of the semiconductor device.

The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A method of manufacturing a capacitive pressure sensor, comprising the steps of:

etching the oxide layer to form a cavity;

2. The method of claim 1, further comprising a top silicon layer thinning step after the step of sequentially forming an oxide layer and a top silicon layer on the implanted layer and before the step of etching the top silicon layer to form a deep trench matrix.

3. The method of manufacturing a capacitive pressure sensor according to claim 1, wherein the thickness of the oxide layer is the spacing between the two plates of the capacitive pressure sensor.

4. The method of claim 1, wherein the deep trench matrix has a critical dimension of 0.6-1um and/or a pitch between deep trenches in the deep trench matrix is 0.6-1 um.

5. The method of claim 1, wherein the step of forming the top silicon layer into a continuous silicon film to seal the cavity comprises a high temperature annealing step that causes silicon migration to form the top silicon layer into a continuous silicon film.

6. The method of manufacturing a capacitive pressure sensor according to claim 1 or 5, further comprising an electrode terminal forming step, the electrode terminal comprising an upper electrode terminal and/or a lower electrode terminal.

7. The method of manufacturing a capacitive pressure sensor according to claim 6, wherein the electrode terminal forming step includes an etching step including etching a top silicon layer to expose an oxide layer, etching the oxide layer to form an opening portion, and forming a lower electrode terminal in the opening portion.

8. The method of claim 1, wherein the deep trench matrix serves as a relief hole for the step of etching the oxide layer to form a cavity.

9. The method of manufacturing a capacitive pressure sensor according to claim 1, wherein the oxide layer is a silicon oxide layer.

10. A capacitive pressure sensor prepared by the manufacturing method according to any one of claims 1 to 9.