CN103449358A - Manufacturing method of closed cavity of micro-electromechanical system (MEMS) - Google Patents
Manufacturing method of closed cavity of micro-electromechanical system (MEMS) Download PDFInfo
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Abstract
The invention provides a manufacturing method of a closed cavity of a micro-electromechanical system (MEMS). The manufacturing method comprises the steps: forming a sacrificial oxidation layer on a semiconductor substrate, and etching the sacrificial oxidation layer to form a cavity boundary figure; depositing a stop layer of the cavity, and etching the cavity stop layer to form a cavity etching hole array; etching the sacrificial oxidation layer and the semiconductor substrate by the cavity etching hole array to form a cavity; filling the cavity etching hole array to form the closed cavity. The cavity stop layer is deposited on the semiconductor substrate, the sacrificial oxidation layer is formed on the semiconductor substrate, the sacrificial oxidation layer and the semiconductor substrate are etched by the cavity etching hole array formed on the cavity stop layer, so that the cavity is formed; and therefore, the minimum size of the cavity can greatly reduced to a certain extent, the minimum thickness of a top dielectric layer is reduced, a silicon wafer bonding process is omitted, the problems of interfaces holes and the like can be avoided, and the reliability of a device can be improved.
Description
Technical field
The present invention relates to micro-electromechanical system field, particularly a kind of preparation method of MEMS closed cavity.
Background technology
At present, as the Semiconductor substrate that can make the semiconductor device high performance, SOI(Silicon on Insulator, silicon-on-insulator) in widespread attention, SOI is that monocrystalline silicon piece embedded set one deck of a kind of routine plays the silica of insulating effect and the novel semi-conductor silicon materials that form, comprises silicon substrate, insulating barrier and top silicon layer.In prior art, the method for manufacturing the SOI material mainly contains:
Ion implantation technique: adopt the principle of Implantation oxygen, O +ion implanted, under silicon chip surface, is formed to one deck buried regions oxide layer by annealing in process, thereby obtain one deck top silicon layer on the SOI substrate.The silicon thin film good uniformity that this method obtains, but the damage that Implantation causes and defect are difficult to eliminate.
Si-Si bonding attenuated polishing technology: by a silicon chip, then with another wafer bonding, then carry out the high temperature anneal, two silicon chips are bonded together securely by silicon oxygen bond, then by a wafer thinning, polishing, obtain desired top silicon layer.The advantage of this method is that the silicon thin film perfection of lattice is good, reaches body silicon level fully, and film thickness can arbitrarily be controlled as required; Shortcoming is that uniformity and the boundary defect of film is difficult to control, and at present by improving bonding techniques and improving attenuate, polishing technology reduce injection defect, is SOI manufacturing technology commonly used in producing.
The smart peeling technology: adopt energetic ion to inject hydrogen ion injected to silicon chip, then with oxidation after silicon chip carry out Si-Si bonding, high annealing, the hydrogen sheet is peeled away from the hydrogen zone automatically, at the SOI substrate, obtains one deck top silicon layer.But silicon film surface is subject to the distribution influence of hydrogen, and surface ratio is more coarse, need to carry out polishing.
In microelectromechanical systems (MEMS), the method of utilizing integrated circuit processing technique to be combined with the micromechanics microtechnic, obtain the MEMS movable member, just need to make top silicon layer having on the SOI substrate of cavity, form buried regions cavity type soi structure (Cavity-Silicon on Insulator, CSOI).CSOI adopts above-mentioned Si-Si bonding attenuated polishing technology to be made, and the key step of its making comprises: oxidation, etching, bonding, attenuate, five processes of polishing.By a silicon chip, another silicon chip erosion goes out the cavity figure, and two silicon chips carry out bonding, carry out again the high temperature anneal, two silicon chips are bonded together securely by silicon oxygen bond, then by a wafer thinning, polishing, obtain desired buried regions cavity type soi structure.
Along with the development of MEMS technology, the application of CSOI is more and more general, but a series of technological challenge comes one after another thereupon, for example: CSOI makes need to carry out attenuate, polishing to a silicon chip, causes cost of manufacture too high, and needs external processing, process-cycle is long, and technical process is not controlled; On silicon chip, due to the cavity figure being arranged, the area of Si-Si bonding reduces, and firmly degree reduces, and even interface void etc. appears in local area.These problems all cause on the reliability of device the impact that can not estimate
Summary of the invention
The object of the present invention is to provide a kind of preparation method of MEMS closed cavity, do not need to use wafer bonding technique, solve CSOI in prior art and make the high cost caused, the problems such as interface void that the process-cycle is long and Si-Si bonding easily causes.
Technical scheme of the present invention is a kind of preparation method of MEMS closed cavity, comprises the following steps:
Semi-conductive substrate is provided, forms sacrificial oxide layer thereon;
Described sacrificial oxide layer is carried out to etching for the first time, form the border figure of cavity;
Deposition chamber stop-layer on described sacrificial oxide layer;
Described cavity stop-layer is carried out to etching for the second time, form cavity etched hole array;
By described cavity etched hole array, described sacrificial oxide layer is carried out to etching for the third time;
By described cavity etched hole array, described Semiconductor substrate is carried out to etching the 4th time, form cavity;
Fill described cavity etched hole array, form closed cavity.。
Further, the material of described Semiconductor substrate is monocrystalline silicon.
Further, the material of described sacrificial oxide layer is silica.
Further, described cavity stop-layer is the antiacid medium of low stress.
Further, described cavity stop-layer is silicon nitride or polysilicon.
Further, the described using plasma of etching for the second time carries out dry etching.
Further, described etching for the first time and for the third time etching all adopt BOE solution to carry out wet etching
Further, described the 4th etching adopts TMAH or KOH to carry out wet etching.
Further, filling the material that described cavity etched hole array adopts is polysilicon.
Further, adopt Low Pressure Chemical Vapor Deposition to deposit described polysilicon.
Compared with prior art, the present invention has the following advantages:
1, the present invention is by being formed with deposition chamber stop-layer on the Semiconductor substrate of sacrificial oxide layer, form cavity by form cavity etched hole array on the cavity stop-layer in order to etching sacrificial oxide layer and Semiconductor substrate again, save wafer bonding technique, the problems such as interface void of having avoided wafer bonding to cause, improved the reliability of device; And closed cavity is directly produced by etching, can significantly dwindle the minimum dimension that cavity can reach;
2, etching adopts polysilicon filled chamber etched hole array after forming cavity again, can define according to the thickness of the size of cavity etched hole array and needed top layer dielectric layer the thickness of polysilicon, dwindled to a certain extent the minimum thickness that the top layer dielectric layer can reach, solved CSOI for a long time and top layer can't have been done to thin technical barrier;
3, the present invention has saved in prior art and silicon chip has been carried out to the technical process such as attenuate, polishing, when being provided, saved lower cost solution the link of external processing, greatly reduce the production cycle, and solved because external processing causes the not controlled problem of technical process, further improved the reliability of device.
The accompanying drawing explanation
The manufacturing process flow chart that Fig. 1 is MEMS closed cavity in one embodiment of the invention.
The structural representation that Fig. 2～8 are the manufacturing process of MEMS closed cavity in one embodiment of the invention.
The specific embodiment
For making content of the present invention more clear understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art also is encompassed in protection scope of the present invention.
Secondly, the present invention utilizes schematic diagram to carry out detailed statement, and when example of the present invention is described in detail in detail, for convenience of explanation, schematic diagram does not amplify according to general ratio is local, should be to this as restriction of the present invention.
The manufacturing process flow chart that Fig. 1 is MEMS closed cavity in one embodiment of the invention, as shown in Figure 1, the present invention proposes a kind of preparation method of MEMS closed cavity, comprises the following steps:
Step S01: semi-conductive substrate is provided, forms sacrificial oxide layer thereon;
Step S02: described sacrificial oxide layer is carried out to etching for the first time, form the border figure of cavity;
Step S03: deposition chamber stop-layer on described sacrificial oxide layer;
Step S04: described cavity stop-layer is carried out to etching for the second time, form cavity etched hole array;
Step S05: described sacrificial oxide layer is carried out to etching for the third time by described cavity etched hole array;
Step S06: by described cavity etched hole array, described Semiconductor substrate is carried out to etching the 4th time, form cavity;
Step S07: fill described cavity etched hole array, form closed cavity.
The structural representation that Fig. 2～8 are the manufacturing process of MEMS closed cavity in one embodiment of the invention, please refer to shown in Fig. 1, and, in conjunction with Fig. 2～Fig. 8, describe the preparation method that the present invention proposes described MEMS closed cavity in detail:
In step S01, semi-conductive substrate 100 is provided, form sacrificial oxide layer 101 on described Semiconductor substrate 100, form the structure shown in Fig. 2.Described Semiconductor substrate 100 is monocrystalline silicon in the present embodiment, or well known to a person skilled in the art other Semiconductor substrate.The material of described sacrificial oxide layer 101 is silica, can adopt thermal oxidation method to form, or aumospheric pressure cvd method, Low Pressure Chemical Vapor Deposition deposition form.
In step S02, described sacrificial oxide layer 101 is carried out to etching for the first time, form the border figure 102 of cavity, form structure as shown in Figure 3.
In the present embodiment, etching is wet etching for the first time, adopts BOE solution to carry out etching to described sacrificial oxide layer, in other embodiments, can adopt other etching liquid or other etching mode.The border figure 102 of cavity, for determining the particular location of follow-up cavity on described Semiconductor substrate 100, is convenient in the subsequent technique scope definite at the border of cavity figure 102 carry out etching and is formed cavity.
In step S03, deposition chamber stop-layer 103 on described sacrificial oxide layer 101, form structure as shown in Figure 4.
Described cavity stop-layer 103 is deposited on the border figure 102 of described sacrificial oxide layer 101 and described cavity, for the top layer position of the cavity of determining follow-up formation.Described cavity stop-layer 103 is the antiacid medium of low stress, and in the present embodiment, the material of described cavity stop-layer 103 is silicon nitride or polysilicon.The thickness of described cavity stop-layer 103 determined by actual process conditions and device requirement, such as: the etching condition of the top layer dielectric thickness of required cavity, follow-up etching for the third time and the 4th etching etc.
In step S04, described cavity stop-layer 103 is carried out to etching for the second time, form cavity etched hole array 104, form structure as shown in Figure 5.
Described cavity etched hole array 104 is positioned on described cavity stop-layer 103 within being positioned at the scope of the definite cavity of described cavity border figure 102.For follow-up technique, sacrificial oxide layer 101 and the Semiconductor substrate 100 that can be positioned under cavity stop-layer 103 by described cavity stop-layer 103 etchings form cavity.
Described etching for the second time is dry etching, the described cavity stop-layer 103 of using plasma etching, for example, CF
3plasma, or well known to a person skilled in the art other plasma.The size of the etched hole that its etching forms and the number of etched hole array are decided by the size of required cavity, if the size of cavity is larger, answer the size of corresponding increase etched hole and the number of etched hole array, to facilitate sacrificial oxide layer 101 and the Semiconductor substrate 100 under etching cavity stop-layer 103.
In step S05, carry out etching for the third time by 104 pairs of described sacrificial oxide layers 101 of described cavity etched hole array, form the structure shown in Fig. 6.
Etching is wet etching for the third time, same with described etching phase for the first time, for the described sacrificial oxide layer 101 of etching, adopts BOE solution to carry out etching.Within the described sacrificial oxide layer be etched 101 is positioned at the definite cavity scope of described cavity border figure 102.
In step S06, carry out etching the 4th time by 104 pairs of described Semiconductor substrate 100 of described cavity etched hole array, form cavity 105, as shown in Figure 7.
After steps performed S05, sacrificial oxide layer 101 at described cavity border figure 102 within definite cavity scope is etched, expose Semiconductor substrate 100, then carry out etching the 4th time, by the described Semiconductor substrate exposed 100 of described cavity etched hole array 104 etchings, form cavity 105.
The 4th time etching is wet etching, needs to form cavity 105, and etching speed difference on different etching directions, consider the requirement of anisotropic etching, in the present embodiment, adopts KOH or TMAK to carry out etching to described Semiconductor substrate 100.
In the present invention, the space that the sacrificial oxide layer 101 be etched away is shared and the shared space of Semiconductor substrate 100 be etched away form cavity 105 jointly, therefore final cavity can decide according to length and the width of the material be etched, and can significantly dwindle the minimum dimension that cavity can reach to a certain extent.
In step S07, fill described cavity etched hole array 102, form closed cavity 106, as shown in Figure 8.
In the present embodiment, adopt polycrystalline silicon material 107 to fill described cavity etched hole array 102, according to cavity, the thickness of the thickness of actual required top layer medium and described cavity stop-layer 103 is determined the thickness of polycrystalline silicon material 107 depositions.Adopt chemical vapour deposition technique or the described polycrystalline silicon material 107 of other deposition well known by persons skilled in the art.
In the present invention, deposit spathic silicon material 107 on described cavity etched hole array 102, both form the top layer of closed cavity 106 jointly, have therefore dwindled to a certain extent the minimum thickness that top layer can reach, and have solved CSOI for a long time and top layer can't have been done to thin technical barrier.
In sum, the present invention is by being formed with deposition chamber stop-layer on the Semiconductor substrate of sacrificial oxide layer, form cavity by form cavity etched hole array on the cavity stop-layer in order to etching sacrificial oxide layer and Semiconductor substrate again, save wafer bonding technique, the problems such as interface void of having avoided wafer bonding to cause, improved the reliability of device; And closed cavity is directly produced by etching, can significantly dwindle the minimum dimension that cavity can reach; Etching adopts polysilicon filled chamber etched hole array after forming cavity again, can define according to the thickness of the size of cavity etched hole array and needed top layer dielectric layer the thickness of polysilicon, dwindled to a certain extent the minimum thickness that the top layer dielectric layer can reach, solved CSOI for a long time and top layer can't have been done to thin technical barrier; The present invention has saved in prior art and silicon chip has been carried out to the technical process such as attenuate, polishing, when being provided, saved lower cost solution the link of external processing, greatly reduce the production cycle, and solved because external processing causes the not controlled problem of technical process, further improved the reliability of device.
Foregoing description is only the description to preferred embodiment of the present invention, and not to any restriction of the scope of the invention, any change, modification that the those of ordinary skill in field of the present invention is done according to above-mentioned disclosure, all belong to the protection domain of claims.
Claims (10)
1. the preparation method of a MEMS closed cavity, is characterized in that, comprises the following steps:
Semi-conductive substrate is provided, forms sacrificial oxide layer thereon;
Described sacrificial oxide layer is carried out to etching for the first time, form the border figure of cavity;
Deposition chamber stop-layer on described sacrificial oxide layer;
Described cavity stop-layer is carried out to etching for the second time, form cavity etched hole array;
By described cavity etched hole array, described sacrificial oxide layer is carried out to etching for the third time;
By described cavity etched hole array, described Semiconductor substrate is carried out to etching the 4th time, form cavity;
Fill described cavity etched hole array, form closed cavity.
2. the preparation method of MEMS closed cavity as claimed in claim 1, is characterized in that, the material of described Semiconductor substrate is monocrystalline silicon.
3. the preparation method of MEMS closed cavity as claimed in claim 1, is characterized in that, the material of described sacrificial oxide layer is silica.
4. the preparation method of MEMS closed cavity as claimed in claim 1, is characterized in that, described cavity stop-layer is the antiacid medium of low stress.
5. the preparation method of MEMS closed cavity as claimed in claim 4, is characterized in that, described cavity stop-layer is silicon nitride or polysilicon.
6. the preparation method of MEMS closed cavity as claimed in claim 5, is characterized in that, the described using plasma of etching for the second time carries out dry etching.
7. the preparation method of MEMS closed cavity as claimed in claim 1, is characterized in that, described etching for the first time and for the third time etching all adopt BOE solution to carry out wet etching.
8. the preparation method of MEMS closed cavity as claimed in claim 1, is characterized in that, described the 4th etching adopts TMAH or KOH to carry out wet etching.
9. the preparation method of MEMS closed cavity as claimed in claim 1, is characterized in that, the material of filling described cavity etched hole array employing is polysilicon.
10. the preparation method of MEMS closed cavity as claimed in claim 9, is characterized in that, adopts Low Pressure Chemical Vapor Deposition to deposit described polysilicon.
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| TWI588918B (en) * | 2014-04-01 | 2017-06-21 | 亞太優勢微系統股份有限公司 | Micro-eletromechanical wafer structure having accurate gap and manufacturing method thereof |
| CN108147360A (en) * | 2018-01-08 | 2018-06-12 | 杭州士兰微电子股份有限公司 | MEMS structure, MEMS component and its manufacturing method |
| WO2019007324A1 (en) * | 2017-07-03 | 2019-01-10 | 无锡华润上华科技有限公司 | Method for manufacturing dual-cavity structure, and dual-cavity structure |
| CN111491244A (en) * | 2020-03-16 | 2020-08-04 | 歌尔微电子有限公司 | MEMS microphone processing method and MEMS microphone |
| CN112919405A (en) * | 2021-01-27 | 2021-06-08 | 中北大学南通智能光机电研究院 | In-situ film packaging method for RF MEMS switch |
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