CN103700643A - Adapter plate deep groove capacitor on basis of TSV (Through Silicon Via) process and manufacturing method thereof - Google Patents
Adapter plate deep groove capacitor on basis of TSV (Through Silicon Via) process and manufacturing method thereof Download PDFInfo
- Publication number
- CN103700643A CN103700643A CN201310718949.0A CN201310718949A CN103700643A CN 103700643 A CN103700643 A CN 103700643A CN 201310718949 A CN201310718949 A CN 201310718949A CN 103700643 A CN103700643 A CN 103700643A
- Authority
- CN
- China
- Prior art keywords
- electric capacity
- substrate
- interarea
- layer
- medium layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention relates to an adapter plate deep groove capacitor on the basis of a TSV (Through Silicon Via) process and a manufacturing method thereof and belongs to the technical field of semiconductor packaging. According to the technical scheme provided by the invention, the adapter plate deep groove capacitor on the basis of the TSV process comprises a substrate; the substrate is provided with a first main surface and a second main surface corresponding to the first main surface; a capacitor groove is formed in a doped region of the substrate; the groove bottom of the capacitor groove is positioned in the doped region; a capacitor medium body and a capacitor filling conductor are arranged in the capacitor groove; the capacitor filling conductor is in contact with the inner wall of the capacitor groove by the capacitor medium body; a first capacitor connecting electrode and a second capacitor connecting electrode are arranged above the first main surface of the substrate; the first capacitor connecting electrode is in ohmic contact with the doped region; the second capacitor connecting electrode is electrically connected with the capacitor filling conductor. The adapter plate deep groove capacitor has a compact structure and simple and convenient process steps; the high-density capacitor can be manufactured on an adapter plate; the adapter plate deep groove capacitor has good process compatibility and is safe and reliable.
Description
Technical field
The present invention relates to a kind of keyset deep-channel capacitor structure, especially a kind of keyset deep-channel capacitor and manufacture method thereof based on TSV technique, belongs to the technical field of semiconductor packages.
Background technology
At present, based on TSV(Through Silicon Via) the keyset technique of technology obtained the approval of industrial circle gradually, and relevant technology is day by day ripe.Due to keyset towards be system in package, so keyset is except providing the interconnect architecture of optimization also to need to provide the passive devices such as electric capacity, with sophisticated systems performance.Between the electric capacity of keyset or the interconnection layer on keyset, make capacity plate antenna in the industry at present, the density of the general electric capacity of this electric capacity is less, need to increase reticle, and complex process degree is higher.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, provide a kind of keyset deep-channel capacitor and manufacture method thereof based on TSV technique, its compact conformation, processing step is easy, can on keyset, manufacture high density capacitor, processing compatibility is good, safe and reliable.
According to technical scheme provided by the invention, the described keyset deep-channel capacitor based on TSV technique, comprises substrate; Described substrate has the first interarea and second interarea corresponding with described the first interarea; In the doped region of described substrate, be provided with electric capacity groove, the bottom land of electric capacity groove is positioned at described doped region; In electric capacity groove, be provided with capacitor dielectric body and electric capacity and fill conductor, described electric capacity filling conductor dbus is crossed capacitor dielectric body and is contacted with the inwall of electric capacity groove; The first interarea top of substrate is provided with the first electric capacity connecting electrode and the second electric capacity connecting electrode, the first electric capacity connecting electrode and doped region ohmic contact, and the second electric capacity connecting electrode is filled conductor with electric capacity and is electrically connected to.
Described capacitor dielectric body comprises first medium layer, second medium layer and the 3rd dielectric layer; Described first medium layer covers the inwall of electric capacity groove, and second medium layer is between first medium layer and the 3rd dielectric layer, and the 3rd dielectric layer is coated on electric capacity and fills on conductor.
On the first interarea of described substrate, by first medium layer and the 3rd dielectric layer, form surface media; Surface media is provided with connecting through hole, and described connecting through hole is positioned at the outside of electric capacity groove; In connecting through hole, be filled with the first connector, described the first connector is filled in connecting through hole and is supported on surface media, and the first electric capacity connecting electrode is by the first connector and doped region ohmic contact; The second connector that the second electric capacity connecting electrode is filled on conductor by electric capacity is electrically connected to electric capacity filling conductor; On surface media, be also coated with dielectric isolation layer, the first electric capacity connector, the second electric capacity connector pass in dielectric isolation layer.
In described substrate, be provided with link slot, the notch of described link slot points to the direction extension of the second interarea from the first interarea of substrate, in link slot, be provided with first medium layer, the 3rd dielectric layer and interconnection and fill conductor, first medium layer covers the inwall of link slot, the 3rd dielectric layer covers on first medium layer, and the 3rd dielectric layer fills conductor contact with interconnection and conductor is filled in coated described interconnection; Interconnection is filled conductor and is electrically connected to the interconnection connecting electrode of substrate the first interarea top.
Described first medium layer is silicon oxide layer, and second medium layer is silicon nitride layer, and the 3rd dielectric layer is silicon oxide layer, or the composite bed of silica and silicon nitride.
A manufacture method for keyset deep-channel capacitor based on TSV technique, the manufacture method of described keyset deep-channel capacitor comprises the steps:
A, provide substrate, described substrate has the first interarea and second interarea corresponding with described the first interarea; Substrate is adulterated, and to obtain doped region in substrate, described doped region points to the direction extension of the second interarea from the first interarea of substrate;
B, optionally shelter and the above-mentioned substrate of etching, to obtain required electric capacity groove and link slot in substrate, wherein, the bottom land of electric capacity groove is positioned at doped region;
C, on the first interarea of above-mentioned substrate, first medium layer is set, described first medium layer covers on the first interarea of substrate, and covers the inwall of electric capacity groove and the inwall of link slot;
D, on the first interarea of above-mentioned substrate, second medium layer is set, described second medium layer covers on first medium layer;
E, optionally shelter and second medium layer described in etching, remove the corresponding second medium layer in link slot and on substrate the first interarea, retain the second medium layer in electric capacity groove;
F, the 3rd dielectric layer is set on the first interarea of above-mentioned substrate, described the 3rd dielectric layer covers on the first medium layer and the second medium layer in electric capacity groove on the first medium layer on substrate the first interarea, in link slot, in electric capacity groove, by first medium layer, second medium layer and the 3rd dielectric layer, forms capacitor dielectric body; First medium layer on substrate the first interarea and the 3rd dielectric layer form surface media;
G, on the first interarea of above-mentioned substrate, electroplate packing material, described packing material covers substrate the first interarea top and is filled in electric capacity groove and link slot;
H, remove the packing material on above-mentioned substrate the first interarea, conductor is filled in the interconnection that the electric capacity that obtains being positioned at electric capacity groove is filled conductor and is positioned at link slot;
I, optionally shelter and etching surface dielectric layer, obtain connecting the connecting through hole of surface media, described connecting through hole is positioned at the outside of electric capacity groove, and be positioned at doped region directly over;
J, on the first interarea of above-mentioned substrate, interconnection structure is set, obtain the second connector, the first connector and the 3rd connector, the first connector be filled in connecting through hole and with doped region ohmic contact, the second connector is filled conductor with electric capacity and is electrically connected to, and the 3rd connector is filled conductor with interconnection and is electrically connected to;
K, on above-mentioned surface media, arrange dielectric isolation layer, interconnection connecting electrode, the first electric capacity connecting electrode and the second electric capacity connecting electrode; Dielectric isolation layer covers on surface media and the second connector, the first connector and the 3rd connector, interconnection connecting electrode is electrically connected to the 3rd connector, the first electric capacity connecting electrode is electrically connected to the first connector, and the second electric capacity connecting electrode is electrically connected to the second connector; Interconnection connecting electrode, the first electric capacity connecting electrode and the second electric capacity connecting electrode pass outside dielectric isolation layer.
Described step e comprises the steps:
On e1, the second medium layer on substrate the first interarea, photopolymer layer is set, described photopolymer layer covers on second medium layer;
E2, remove outer photopolymer layer directly over electric capacity groove notch, obtain being positioned at the dry film directly over electric capacity groove notch, described dry film is across on the notch at electric capacity groove and be supported on the second medium layer in electric capacity groove notch outside;
E3, utilize the selective protection of dry film, the second medium layer on etched substrate the first interarea, with remove in link slot and substrate the first interarea on corresponding second medium layer.
Described packing material comprises copper.The material of described substrate comprises silicon.
Described first medium layer is silicon oxide layer, and second medium layer is silicon nitride layer, and the 3rd dielectric layer is silicon oxide layer, or the composite bed of silica and silicon nitride.
Electric capacity groove is set in substrate, capacitor dielectric body and electric capacity are set in electric capacity groove and fill conductor, capacitor dielectric body adopts the structure of silica-silicon-nitride and silicon oxide, make to form electric capacity and have high density, the electric capacity of formation is drawn by the first electric capacity connecting electrode and the second electric capacity connecting electrode, manufacturing process and existing TSV process matching, without process complexity, processing compatibility is good, and compact conformation is safe and reliable.
Accompanying drawing explanation
Fig. 1 ~ Figure 13 is the concrete implementing process step of the present invention cutaway view, wherein
Fig. 1 is that the present invention obtains the cutaway view after doped region in substrate.
Fig. 2 is that the present invention obtains the cutaway view after electric capacity groove and link slot in substrate.
Fig. 3 is that the present invention arranges the cutaway view after first medium layer on the first interarea of substrate.
Fig. 4 is that the present invention arranges the cutaway view after second medium layer on the first interarea of substrate.
Fig. 5 obtains the cutaway view after dry film for this aspect on the first interarea of substrate.
Fig. 6 is that the present invention utilizes dry film to carry out the cutaway view after etching to second medium layer.
Fig. 7 is that the present invention removes the cutaway view after dry film.
Fig. 8 is that the present invention arranges the cutaway view after the 3rd dielectric layer on the first interarea of substrate.
Fig. 9 is that the present invention arranges the cutaway view after packing material on the first interarea of substrate.
Figure 10 is that the present invention obtains electric capacity filling conductor and turns the cutaway view of filling after electrode.
Figure 11 is that the present invention obtains the cutaway view after connecting through hole.
Figure 12 is that the present invention obtains the cutaway view after the first connector, the second connector and the 3rd connector.
Figure 13 is that the present invention obtains the cutaway view after the first electric capacity connecting electrode, the second electric capacity connecting electrode and interconnection connecting electrode.
Description of reference numerals: conductor is filled in 1-substrate, 2-doped region, 3-electric capacity groove, 4-first medium layer, 5-second medium layer, 6-dry film, 7-encapsulant layer, 8-connecting through hole, 9-the second connector, 10-the first connector, 11-the 3rd dielectric layer, 12-link slot, 13-interconnection, 14-electric capacity is filled conductor, 15-the 3rd connector, 16-dielectric isolation layer, 17-interconnection connecting electrode, 18-the first electric capacity connecting electrode, 19-the second electric capacity connecting electrode and 20-surface media.
Embodiment
Below in conjunction with concrete drawings and Examples, the invention will be further described.
As shown in figure 13: in order to obtain highdensity electric capacity in keyset, the present invention is based on the keyset deep-channel capacitor of TSV technique, comprise substrate 1; Described substrate 1 has the first interarea and second interarea corresponding with described the first interarea; In the doped region 2 of described substrate 1, be provided with electric capacity groove 3, the bottom land of electric capacity groove 3 is positioned at described doped region 2; In electric capacity groove 3, be provided with capacitor dielectric body and electric capacity and fill conductor 14, described electric capacity is filled conductor 14 and is contacted with the inwall of electric capacity groove 3 by capacitor dielectric body; The first interarea top of substrate 1 is provided with the first electric capacity connecting electrode 18 and the second electric capacity connecting electrode 19, the first electric capacity connecting electrodes 18 and doped region 2 ohmic contact, and the second electric capacity connecting electrode 19 is filled conductor 14 with electric capacity and is electrically connected to.
Particularly, the first electric capacity connecting electrode 18 and the second electric capacity connecting electrode 19 are for outwards drawing formation capacitance structure, doped region 2, electric capacity are filled between conductor 14 and capacitor dielectric body and are formed capacitance structure, and capacitor dielectric body can make the electric capacity in substrate 1 have higher density.In the embodiment of the present invention, the degree of depth of electric capacity groove 3 in substrate 1 be the degree of depth in substrate 1 lower than link slot 12.Meanwhile, the bottom land of electric capacity groove 3, in doped region 2, after the interior formation capacitance structure of electric capacity groove 3, makes whole electric capacity have good high frequency performance.
Described capacitor dielectric body comprises first medium layer 4, second medium layer 5 and the 3rd dielectric layer 11; Described first medium layer 4 covers the inwall of electric capacity groove 3, and second medium layer 5 is between first medium layer 4 and the 3rd dielectric layer 11, and the 3rd dielectric layer 11 is coated on electric capacity and fills on conductor 14.Described first medium layer 4 is silicon oxide layer, and second medium layer 5 is silicon nitride layer, and the 3rd dielectric layer 11 is the composite bed of silicon oxide layer or silica and silicon nitride.
On the first interarea of described substrate 1, by first medium layer 4 and the 3rd dielectric layer 11, form surface media 20; Surface media 20 is provided with connecting through hole 8, and described connecting through hole 8 is positioned at the outside of electric capacity groove 3; In connecting through hole 8, be filled with the first connector 10, described the first connector 10 is filled in connecting through hole 8 and is supported on surface media 20, and the first electric capacity connecting electrode 18 is by the first connector 10 and doped region 2 ohmic contact; The second connector 9 that the second electric capacity connecting electrode 9 is filled on conductor 14 by electric capacity is electrically connected to electric capacity filling conductor 14; On surface media 20, be also coated with dielectric isolation layer 16, the first electric capacity connectors 18, the second electric capacity connector 19 passes in dielectric isolation layer 16.
Above-mentioned for obtain the structure of deep-channel capacitor in substrate 1, in order to realize through hole, connect, in the embodiment of the present invention, in described substrate 1, be provided with link slot 12, the notch of described link slot 12 points to the direction extension of the second interarea from the first interarea of substrate 1, in link slot 12, be provided with first medium layer 4, the 3rd dielectric layer 11 and interconnection and fill conductor 13, first medium layer 4 covers the inwall of link slot 12, the 3rd dielectric layer 11 covers on first medium layer 4, and the 3rd dielectric layer 11 is filled conductor 13 with interconnection and contacted and be coated described interconnection filling conductor 13; Interconnection is filled conductor 13 and is electrically connected to the interconnection connecting electrode 17 of substrate 1 first interarea top.In the embodiment of the present invention, the above-mentioned schematic diagram that obtains capacitance structure and syndeton in substrate 1 of only having described, can also be as required carries out required structure setting at the second interarea of substrate 1.At the second interarea of substrate 1, required structure being set can be similar with arranging of the first interarea, and is not emphasis of the present invention, repeats no more herein.
As shown in Fig. 1 ~ Figure 13: the deep-channel capacitor structure of said structure, can prepare by following processing step, the manufacture method of described keyset deep-channel capacitor comprises the steps:
A, provide substrate 1, described substrate 1 has the first interarea and second interarea corresponding with described the first interarea; Substrate 1 is adulterated, and to obtain doped region 2 in substrate 1, described doped region 2 points to the direction extension of the second interarea from the first interarea of substrate 1;
As shown in Figure 1: substrate 1 can be selected silicon substrate, on the first interarea of substrate 1, utilize diffusing, doping or ion implantation technology to adulterate at the desired zone of substrate 1, and utilize diffusion technology carry out ion-activated and advance, at the interior formation doped region 2 of substrate 1; At the interior formation doped region 2 of substrate 1, be conventional processing step, repeat no more herein.
B, optionally shelter and the above-mentioned substrate 1 of etching, to obtain required electric capacity groove 3 and link slot 12 in substrate 1, wherein, the bottom land of electric capacity groove 3 is positioned at doped region 2;
As shown in Figure 2: to the first interarea of substrate 1, utilize photoetching and deep reaction ion etching technique to form blind hole, obtain electric capacity groove 3 and link slot 12, wherein, by electric capacity groove 3, can form required high density capacitor, utilize link slot 12 to prepare the required through hole syndeton of keyset.Link slot 12 is positioned at the region outside doped region 2.The degree of depth of electric capacity groove 3 is less than the degree of depth of link slot 12, the bore of electric capacity groove 3 is less than the bore of link slot 12, thereby be less than at the etch rate that substrate 1 is interior while preparing electric capacity groove 3 etch rate of making link slot 12, realize more shallow electric capacity groove 3, and capacitance structure that must be more shallow.The degree of depth of electric capacity groove 3 can regulate by different bores are set.
C, on the first interarea of above-mentioned substrate 1, first medium layer 4 is set, described first medium layer 4 covers on the first interarea of substrate 1, and covers the inwall of electric capacity groove 3 and the inwall of link slot 12;
As shown in Figure 3: described first medium layer 4 is silicon oxide layer, described first medium layer 4 can form by chemical vapor deposition or oxidation technology on substrate 1, first medium layer 4 can be as the resilient coating between silicon substrate and the second medium layer 5 of employing silicon nitride, avoid silicon nitride directly to contact and cause stress excessive with silicon, produce the situation of defects on silicon surfaces.
D, on the first interarea of above-mentioned substrate 1, second medium layer 5 is set, described second medium layer 5 covers on first medium layer 4;
As shown in Figure 4: utilize chemical vapor deposition, on the first interarea of substrate 1, second medium layer 5 is set, second medium layer 5 is silicon nitride layer, because silicon nitride has high-k, therefore, can improve capacitance density.The first medium layer 4 that second medium layer 5 covers on the first interarea covers the first medium layer 4 on electric capacity groove 3 and link slot 12 sidewalls simultaneously.
E, optionally shelter and second medium layer 5 described in etching, remove the corresponding second medium layer 5 in link slot 12 and on substrate 1 first interarea, retain the second medium layer 5 in electric capacity groove 3;
As shown in Fig. 5, Fig. 6 and Fig. 7: in order to make keyset have less parasitic capacitance, in the embodiment of the present invention, need to remove the second medium layer 5 in link slot 12, in order to remove second medium layer 5, described step e specifically comprises the steps:
On e1, the second medium layer 5 on substrate 1 first interarea, photopolymer layer is set, described photopolymer layer covers on second medium layer 5;
E2, remove outer photopolymer layer directly over electric capacity groove 3 notches,, obtain being positioned at the dry film 6 directly over electric capacity groove 3 notches, described dry film 6 is across on the notch at electric capacity groove 3 and be supported on the second medium layer 5 in electric capacity groove 3 notches outsides;
By dry film 6, can block second medium layer 5 that dry film contacts with described dry film 6 and the second medium layer 5 in electric capacity groove 3.
E3, utilize the selective protection of dry film 6, the second medium layer 5 on etched substrate 1 first interarea optionally, to remove the corresponding second medium layer 5 in link slot 12 and on substrate 1 first interarea.
At the second medium layer 5 not blocked by dry film 6, can remove by etching technics; After second medium layer 5 is removed, dry film 6 to be removed, the second medium layer 5 that is positioned at electric capacity groove 3 can guarantee the density of electric capacity.
F, the 3rd dielectric layer 11 is set on the first interarea of above-mentioned substrate 1, described the 3rd dielectric layer 11 covers on the first medium layer 4 and the second medium layer 5 in electric capacity groove 3 on the first medium layer 4 and second medium layer 5 on substrate 1 first interarea, in link slot 12, in electric capacity groove 3, by first medium layer 4, second medium layer 5 and the 3rd dielectric layer 11, forms capacitor dielectric body; First medium layer 4 on substrate 1 first interarea and the 3rd dielectric layer 11 form surface media 20;
As shown in Figure 8: the 3rd dielectric layer 11 adopts silica, and the capacitor dielectric body of the rear formation silica-silicon-nitride and silicon oxide of the 3rd dielectric layer 11 is set; In the embodiment of the present invention, the 3rd dielectric layer 11 can also be the lamination layer structure of silica and silicon nitride, after first medium layer 4 and the 3rd dielectric layer 11 stacks, forms surface media 20.
G, on the first interarea of above-mentioned substrate 1, electroplate packing material, described packing material covers substrate 1 first interarea top and is filled in electric capacity groove 3 and link slot 12;
As shown in Figure 9: after electroplating packing material, obtain encapsulant layer 7, described encapsulant layer 7 covers on surface media 20 and is filled in respectively in electric capacity groove 3 and link slot 12.In the specific implementation, before electroplating packing material, need to utilize PVD technique to make barrier layer and Seed Layer, then utilize electroplating technology to electroplate packing material, described packing material can be selected copper.
H, remove the packing material on above-mentioned substrate 1 first interarea, conductor 13 is filled in the interconnection that the electric capacity that obtains being positioned at electric capacity groove 3 is filled conductor 14 and is positioned at link slot 12;
As shown in figure 10: after electroplating encapsulant layer 7, need to anneal or surface metal chemistry mechanical polishing process, to remove packing material and the barrier layer on the first interarea, the temperature of described annealing, packing material and the barrier layer of removing on the first interarea are common process.
I, optionally shelter and etching surface dielectric layer 20, obtain connecting the connecting through hole 8 of surface media 20, described connecting through hole 8 is positioned at the outside of electric capacity groove 3, and be positioned at doped region 2 directly over;
As shown in figure 11: in order to draw capacitance structure, need to make connecting through hole 8, the bottom of connecting through hole 8 is doped region 2.
J, on the first interarea of above-mentioned substrate 1, interconnection structure is set, obtain the second connector 9, the first connector 10 and the 3rd connector 15, the first connector 10 be filled in connecting through hole 8 and with doped region 2 ohmic contact, the second connector 9 is filled conductor 14 with electric capacity and is electrically connected to, and the 3rd connector 15 is filled conductor 13 with interconnection and is electrically connected to;
As shown in figure 12: on the first interarea of substrate 1, by techniques such as deposits, obtain the first connector 10, the second connector 9 and the 3rd connector 15, the first connector 10 is filled in connecting through hole 8 and is supported on surface media 20, the second connector 9 is directly filled after conductor 14 contacts and is electrically connected to electric capacity, and the 3rd connector 15 is filled after conductor 13 contacts and is electrically connected to interconnection.Further, the 3rd connector 15 has also needed necessary interconnection structure after being electrically connected to interconnection filling conductor 13, and the interconnection structure of described necessity arranges and operates according to different interconnection structures.
K, on above-mentioned surface media 20, arrange dielectric isolation layer 16, interconnection connecting electrode 17, the first electric capacity connecting electrode 18 and the second electric capacity connecting electrode 19; Dielectric isolation layer 16 covers on surface media 20 and the second connector 9, the first connector 10 and the 3rd connector 15, interconnection connecting electrode 17 is electrically connected to the 3rd connector 15, the first electric capacity connecting electrode 18 is electrically connected to the first connector 10, and the second electric capacity connecting electrode 19 is electrically connected to the second connector 9; Interconnection connecting electrode 17, the first electric capacity connecting electrode 18 and the second electric capacity connecting electrode 19 pass outside dielectric isolation layer 16.
As shown in figure 13: in order to carry out the connection of drawing of through hole connection and electric capacity, guarantee the reliability of drawing, dielectric isolation layer 16 is also set on the first interarea, described dielectric isolation layer 16 covers on the first connector 10, the second connector 9 and the 3rd connector 15, then by the interconnection connecting electrode 17, the first electric capacity connecting electrode 18 and the second electric capacity connecting electrode 19 and outside being connected that pass outside dielectric isolation layer 16, interconnection connecting electrode 17, the first electric capacity connecting electrode 18 and the second electric capacity connecting electrode 19 form the form of salient point.
By above-mentioned technique, on the first interarea of substrate 1, complete the structures such as through hole connection, electric capacity of keyset, can also be as required at the second interarea of substrate 1, the follow-up structures such as connection be set, follow-up structure no longer describes in detail herein.
The present invention is at the interior electric capacity groove 3 that arranges of substrate 1, interior capacitor dielectric body and the electric capacity filling conductor 14 of arranging of electric capacity groove 3, capacitor dielectric body adopts the structure of silica-silicon-nitride and silicon oxide, make to form electric capacity and there is high density, the electric capacity forming is drawn by the first electric capacity connecting electrode 18 and the second electric capacity connecting electrode 19, in substrate 1, by being set, link slot 12 and interconnection fill conductor 13 formation through hole syndetons, manufacturing process and existing TSV process matching, without process complexity, compact conformation, processing compatibility is good, safe and reliable.
Claims (10)
1. the keyset deep-channel capacitor based on TSV technique, comprises substrate (1); Described substrate (1) has the first interarea and second interarea corresponding with described the first interarea; It is characterized in that: in the doped region (2) of described substrate (1), be provided with electric capacity groove (3), the bottom land of electric capacity groove (3) is positioned at described doped region (2); In electric capacity groove (3), be provided with capacitor dielectric body and electric capacity and fill conductor (14), described electric capacity is filled conductor (14) and is contacted with the inwall of electric capacity groove (3) by capacitor dielectric body; The first interarea top of substrate (1) is provided with the first electric capacity connecting electrode (18) and the second electric capacity connecting electrode (19), the first electric capacity connecting electrode (18) and doped region (2) ohmic contact, the second electric capacity connecting electrode (19) is filled conductor (14) with electric capacity and is electrically connected to.
2. the keyset deep-channel capacitor based on TSV technique according to claim 1, is characterized in that: described capacitor dielectric body comprises first medium layer (4), second medium layer (5) and the 3rd dielectric layer (11); Described first medium layer (4) covers the inwall of electric capacity groove (3), and second medium layer (5) is positioned between first medium layer (4) and the 3rd dielectric layer (11), and the 3rd dielectric layer (11) is coated on electric capacity and fills on conductor (14).
3. the keyset deep-channel capacitor based on TSV technique according to claim 2, is characterized in that: on the first interarea of described substrate (1), by first medium layer (4) and the 3rd dielectric layer (11), form surface media (20); Surface media (20) is provided with connecting through hole (8), and described connecting through hole (8) is positioned at the outside of electric capacity groove (3); In connecting through hole (8), be filled with the first connector (10), described the first connector (10) is filled in connecting through hole (8) and is supported on surface media (20) above, and the first electric capacity connecting electrode (18) is by the first connector (10) and doped region (2) ohmic contact; The second connector (9) that the second electric capacity connecting electrode (9) is filled on conductor (14) by electric capacity is electrically connected to electric capacity filling conductor (14); On surface media (20), be also coated with dielectric isolation layer (16), the first electric capacity connector (18), the second electric capacity connector (19) pass in dielectric isolation layer (16).
4. the keyset deep-channel capacitor based on TSV technique according to claim 2, it is characterized in that: in described substrate (1), be provided with link slot (12), the notch of described link slot (12) points to the direction extension of the second interarea from the first interarea of substrate (1), in link slot (12), be provided with first medium layer (4), conductor (13) is filled in the 3rd dielectric layer (11) and interconnection, first medium layer (4) covers the inwall of link slot (12), the 3rd dielectric layer (11) covers on first medium layer (4), the 3rd dielectric layer (11) is filled conductor (13) with interconnection and is contacted and be coated described interconnection filling conductor (13), interconnection is filled conductor (13) and is electrically connected to the interconnection connecting electrode (17) of substrate (1) first interarea top.
5. the keyset deep-channel capacitor based on TSV technique according to claim 2, it is characterized in that: described first medium layer (4) is silicon oxide layer, second medium layer (5) is silicon nitride layer, and the 3rd dielectric layer (11) is silicon oxide layer, or the composite bed of silica and silicon nitride.
6. a manufacture method for the keyset deep-channel capacitor based on TSV technique, is characterized in that, the manufacture method of described keyset deep-channel capacitor comprises the steps:
(a), provide substrate (1), described substrate (1) to there is the first interarea and second interarea corresponding with described the first interarea; Substrate (1) is adulterated, and to obtain doped region (2) in substrate (1), described doped region (2) points to the direction extension of the second interarea from the first interarea of substrate (1);
(b), optionally shelter and the above-mentioned substrate of etching (1), to obtain required electric capacity groove (3) and link slot (12) in substrate (1), wherein, the bottom land of electric capacity groove (3) is positioned at doped region (2);
(c), first medium layer (4) is set on the first interarea of above-mentioned substrate (1), described first medium layer (4) covers on the first interarea of substrate (1), and covers the inwall of electric capacity groove (3) and the inwall of link slot (12);
(d), second medium layer (5) is set on the first interarea of above-mentioned substrate (1), described second medium layer (5) covers on first medium layer (4);
(e), optionally shelter and second medium layer (5) described in etching, remove the corresponding second medium layer (5) in link slot (12) and on substrate (1) first interarea, retain the second medium layer (5) in electric capacity groove (3);
(f), the 3rd dielectric layer (11) is set on the first interarea of above-mentioned substrate (1), the first medium layer (4) that first medium layer (4) is upper, link slot (12) is interior and the second medium layer (5) in electric capacity groove (3) that described the 3rd dielectric layer (11) covers on substrate (1) first interarea are upper, and electric capacity groove (3) is interior by first medium layer (4), second medium layer (5) and the 3rd dielectric layer (11) formation capacitor dielectric body; First medium layer (4) on substrate (1) first interarea forms surface media (20) with the 3rd dielectric layer (11);
(g), on the first interarea of above-mentioned substrate (1), electroplate packing material, described packing material covers substrate (1) first interarea top and is filled in electric capacity groove (3) and link slot (12);
(h), remove the packing material on above-mentioned substrate (1) first interarea, obtain being positioned at the interconnection filling conductor (13) that the electric capacity of electric capacity groove (3) is filled conductor (14) and is positioned at link slot (12);
(i), optionally shelter and etching surface dielectric layer (20), obtain connecting the connecting through hole (8) of surface media (20), described connecting through hole (8) is positioned at the outside of electric capacity groove (3), and be positioned at doped region (2) directly over;
(j), on the first interarea of above-mentioned substrate (1), interconnection structure is set, obtain the second connector (9), the first connector (10) and the 3rd connector (15), the first connector (10) be filled in connecting through hole (8) and with doped region (2) ohmic contact, the second connector (9) is filled conductor (14) with electric capacity and is electrically connected to, and the 3rd connector (15) is filled conductor (13) with interconnection and is electrically connected to;
(k), dielectric isolation layer (16), interconnection connecting electrode (17), the first electric capacity connecting electrode (18) and the second electric capacity connecting electrode (19) are set on above-mentioned surface media (20); Dielectric isolation layer (16) covers on surface media (20) and the second connector (9), the first connector (10) and the 3rd connector (15), interconnection connecting electrode (17) is electrically connected to the 3rd connector (15), the first electric capacity connecting electrode (18) is electrically connected to the first connector (10), and the second electric capacity connecting electrode (19) is electrically connected to the second connector (9); Interconnection connecting electrode (17), the first electric capacity connecting electrode (18) and the second electric capacity connecting electrode (19) pass outside dielectric isolation layer (16).
7. the manufacture method of the keyset deep-channel capacitor based on TSV technique according to claim 6, is characterized in that, described step (e) comprises the steps:
(e1) on the second medium layer (5), on substrate (1) first interarea, photopolymer layer is set, described photopolymer layer covers on second medium layer (5);
(e2), outer photopolymer layer directly over removal electric capacity groove (3) notch, obtain being positioned at the dry film (6) directly over electric capacity groove (3) notch, described dry film (6) is across on the notch in electric capacity groove (3) and be supported on the second medium layer (5) in electric capacity groove (3) notch outside;
(e3), utilize the selective protection of dry film (6), the second medium layer (5) on etched substrate (1) first interarea, to remove the corresponding second medium layer (5) in link slot (12) and on substrate (1) first interarea.
8. the manufacture method of the keyset deep-channel capacitor based on TSV technique according to claim 6, is characterized in that: described packing material comprises copper.
9. the manufacture method of the keyset deep-channel capacitor based on TSV technique according to claim 6, is characterized in that: the material of described substrate (1) comprises silicon.
10. the manufacture method of the keyset deep-channel capacitor based on TSV technique according to claim 6, it is characterized in that: described first medium layer (4) is silicon oxide layer, second medium layer (5) is silicon nitride layer, and the 3rd dielectric layer (11) is silicon oxide layer, or the composite bed of silica and silicon nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310718949.0A CN103700643B (en) | 2013-12-23 | 2013-12-23 | A kind of keyset deep-channel capacitor based on TSV technique and manufacture method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310718949.0A CN103700643B (en) | 2013-12-23 | 2013-12-23 | A kind of keyset deep-channel capacitor based on TSV technique and manufacture method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103700643A true CN103700643A (en) | 2014-04-02 |
| CN103700643B CN103700643B (en) | 2016-07-06 |
Family
ID=50362126
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310718949.0A Active CN103700643B (en) | 2013-12-23 | 2013-12-23 | A kind of keyset deep-channel capacitor based on TSV technique and manufacture method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103700643B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104409442A (en) * | 2014-11-28 | 2015-03-11 | 中国科学院上海微系统与信息技术研究所 | Deep groove structure capacitance and manufacturing method thereof |
| CN105679734A (en) * | 2016-03-07 | 2016-06-15 | 中国科学院上海微系统与信息技术研究所 | Integrated passive component adapter plate and preparation method thereof |
| CN106711083A (en) * | 2015-11-16 | 2017-05-24 | 美光科技公司 | Semiconductor structure and fabricating method thereof |
| CN107402593A (en) * | 2017-08-10 | 2017-11-28 | 宁波大学 | It is a kind of based on silicon hole array without electric capacity LDO circuit outside piece |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1717794A (en) * | 2002-11-27 | 2006-01-04 | 半导体元件工业有限责任公司 | Semiconductor device with parallel plate trench capacitor |
| US20080291601A1 (en) * | 2005-11-08 | 2008-11-27 | Nxp B.V. | Integrated Capacitor Arrangement for Ultrahigh Capacitance Values |
| CN101379619A (en) * | 2006-01-09 | 2009-03-04 | 国际商业机器公司 | Semiconductor structure including trench capacitor and trench resistor |
| US20100155897A1 (en) * | 2008-12-23 | 2010-06-24 | International Business Machines Corporation | Deep trench varactors |
| CN102254872A (en) * | 2010-05-20 | 2011-11-23 | 台湾积体电路制造股份有限公司 | Semiconductor structure and method of forming semiconductor component |
-
2013
- 2013-12-23 CN CN201310718949.0A patent/CN103700643B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1717794A (en) * | 2002-11-27 | 2006-01-04 | 半导体元件工业有限责任公司 | Semiconductor device with parallel plate trench capacitor |
| US20080291601A1 (en) * | 2005-11-08 | 2008-11-27 | Nxp B.V. | Integrated Capacitor Arrangement for Ultrahigh Capacitance Values |
| CN101379619A (en) * | 2006-01-09 | 2009-03-04 | 国际商业机器公司 | Semiconductor structure including trench capacitor and trench resistor |
| US20100155897A1 (en) * | 2008-12-23 | 2010-06-24 | International Business Machines Corporation | Deep trench varactors |
| CN102254872A (en) * | 2010-05-20 | 2011-11-23 | 台湾积体电路制造股份有限公司 | Semiconductor structure and method of forming semiconductor component |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104409442A (en) * | 2014-11-28 | 2015-03-11 | 中国科学院上海微系统与信息技术研究所 | Deep groove structure capacitance and manufacturing method thereof |
| CN106711083A (en) * | 2015-11-16 | 2017-05-24 | 美光科技公司 | Semiconductor structure and fabricating method thereof |
| CN106711083B (en) * | 2015-11-16 | 2019-10-11 | 美光科技公司 | Semiconductor structure and preparation method thereof |
| CN105679734A (en) * | 2016-03-07 | 2016-06-15 | 中国科学院上海微系统与信息技术研究所 | Integrated passive component adapter plate and preparation method thereof |
| CN105679734B (en) * | 2016-03-07 | 2018-05-25 | 中国科学院上海微系统与信息技术研究所 | Integrated passive components pinboard and preparation method thereof |
| CN107402593A (en) * | 2017-08-10 | 2017-11-28 | 宁波大学 | It is a kind of based on silicon hole array without electric capacity LDO circuit outside piece |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103700643B (en) | 2016-07-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103193193B (en) | MEMS and forming method thereof | |
| CN107785273B (en) | Semiconductor device and method for manufacturing the same | |
| CN104037176B (en) | Contact structures and the semiconductor memory component using the contact structures | |
| CN110301037A (en) | Three-dimensional memory structure and its manufacturing method | |
| CN103632949B (en) | The forming method of the hot oxygen medium layer of the inter polysilicon of groove type double-layer grid MOS | |
| CN103700643B (en) | A kind of keyset deep-channel capacitor based on TSV technique and manufacture method thereof | |
| CN104485288A (en) | Manufacturing method of ultrathin glass adapter plate | |
| CN103515300A (en) | Method for forming air gap in metal interconnection process | |
| CN103219303B (en) | The encapsulating structure of a kind of TSV back side small opening and method | |
| CN103178019B (en) | Method for manufacturing word lines of embedded flash memory | |
| CN103474394A (en) | TSV process method without metal CMP | |
| CN103811307B (en) | Semiconductor device and forming method thereof | |
| CN104701161B (en) | A kind of process of preparing of groove-shaped Schottky diode | |
| CN111403404B (en) | Storage structure and preparation method thereof | |
| CN103700644B (en) | Based on pinboard deep-channel capacitor and the manufacture method thereof of TSV technique | |
| CN104465728A (en) | Gate structure of separation gate power device and process method | |
| CN102569180B (en) | The manufacture method of power MOS contact hole | |
| CN102130036A (en) | Method for producing shallow trench isolating structure | |
| CN101996929B (en) | Forming method of dual-damascene structure and semiconductor structure | |
| CN105336672A (en) | Semiconductor structure and formation method therefor | |
| CN104347548A (en) | Semiconductor device and manufacturing method thereof | |
| CN116097919A (en) | Preparation method of three-dimensional memory | |
| CN103187356B (en) | The manufacture method of a kind of semiconductor chip and intermetallic dielectric layer | |
| CN108109996B (en) | Diode-based antistatic adapter plate for integrated circuit and preparation method thereof | |
| CN102364674B (en) | Contact hole etching method, integrate circuit (IC) manufacturing method and IC |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |