KR101767654B1 - Semicondctor devices having through electrodes insulated by air gaps and methods for fabricating the same - Google Patents

Abstract

The present invention relates to a semiconductor device and a method of manufacturing the same, and includes a substrate including an active surface and an inactive surface opposite thereto, a penetrating electrode penetrating the substrate, a trench provided between the substrate and the penetrating electrode, And a lower insulating layer covering the inactive surface of the substrate and extending to the inside of the trench to form an air gap between the substrate and the penetrating electrode in the trench.

Description

FIELD OF THE INVENTION [0001] The present invention relates to a semiconductor device having a through electrode having an air gap insulation structure,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor, and more particularly, to a semiconductor device having a penetrating electrode having an air-gap insulating structure and a manufacturing method thereof.

(TSV) technology that penetrates a semiconductor substrate has evolved. Since the penetrating electrode penetrates the semiconductor substrate, there is a need to improve the insulating property with the semiconductor substrate. Conventionally, an oxide film is formed along the sidewalls of the penetrating electrode for insulation between the semiconductor substrate and the penetrating electrode.

The thickness of the insulating film may need to be increased according to the demand for quick operation characteristics of the penetrating electrode. As the thickness of the insulating film increases, the stress may increase, and the step coverage may be decreased along the aspect ratio of the penetrating electrode, so that the increase in the thickness of the insulating film may be limited. In addition, as the semiconductor device is reduced in size, the size of the penetrating electrode, for example, when the penetrating electrode has a cylindrical shape, can be difficult to ensure the thickness margin of the insulating film as the diameter becomes smaller. As a result, the characteristic of the penetrating electrode may be deteriorated.

It is an object of the present invention to provide a semiconductor device having a penetrating electrode having an excellent insulating characteristic and an excellent electrical characteristic, and a method of manufacturing the same.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a substrate including an active surface and an inactive surface opposite to the active surface; A penetrating electrode passing through the substrate; A trench provided between the substrate and the penetrating electrode; And a lower insulating layer covering the inactive surface of the substrate and extending into the trench to form an air gap between the substrate and the penetrating electrode in the trench.

In the element of the present embodiment, the lower insulating film includes: an external insulating film covering the inactive surface of the substrate; And an inner insulating film extending from the outer insulating film to extend into the trench and forming a wall defining the air gap.

The device of the present embodiment may further include a liner film provided between the penetrating electrode and the inner insulating film and surrounding the sidewall of the penetrating electrode.

In the device of this embodiment, the substrate may include an inner surface spaced apart from the penetrating electrode by the trench. And a liner film provided between the inner surface of the substrate and the inner insulating film to cover the inner surface of the substrate.

The device of this embodiment may further include an upper insulating film covering the active surface of the substrate. The trench may be opened at one side toward the inactive side of the substrate and the other side toward the active side of the substrate may be closed by the top insulating film.

The device of this embodiment may further include an interlayer insulating film provided between the substrate and the upper insulating film. The penetrating electrode may further penetrate the interlayer insulating film.

In the device of this embodiment, the air gap may extend vertically along the sidewalls of the penetrating electrode between the inactive surface and the active surface of the substrate.

In the element of the present embodiment, the air gap may extend perpendicularly along the side wall of the penetrating electrode between the inactive surface of the substrate and the upper insulating film.

In the device of this embodiment, the lower insulating film may include a first lower insulating film and a second lower insulating film. The first lower insulating layer may include an external insulating layer covering the inactive surface of the substrate and an internal insulating layer extending from the external insulating layer to seal the trench. Wherein the second lower insulating film is provided between the inactive surface of the substrate and the external insulating film and into the trench so as to cover the inactive surface of the substrate with the external insulating film and define the air gap with the internal insulating film You can build a wall.

According to another aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate having a horizontal active surface, a horizontal inactive surface opposite to the active surface, and an inactive surface between the active surface and the inactive surface, A substrate comprising a surface; A penetrating electrode vertically penetrating the substrate and spaced apart from the inner surface; An air gap provided between the inner surface and the penetrating electrode, the air gap extending along the penetrating electrode; And a lower insulating film covering the inactive surface and forming a wall that further covers the inner surface and the side wall of the penetrating electrode to define the air gap.

In the device according to another embodiment of the present invention, the lower insulating film may include: an external insulating film covering the inactive surface; And an inner insulating layer extending from the outer insulating layer and covering the inner surface and the sidewalls of the penetrating electrode. The inner insulating film may form a wall defining the air gap.

In the element according to another embodiment of the present invention, it may further comprise a liner film covering the side wall of the penetrating electrode. The inner insulating film and the liner film may be interposed between the penetrating electrode and the air gap. The inner insulating film may be interposed between the inner surface and the air gap.

In the element according to another embodiment of the present invention, it may further comprise a liner film covering the inner surface. The liner film and the inner insulating film may be interposed between the inner surface and the air gap. The inner insulating film may be interposed between the penetrating electrode and the air gap.

In the device according to another embodiment of the present invention, the outer insulating film is a double film, and the inner insulating film may be a single film.

In the device of another embodiment of the present invention, the inner surface may be a linear shape extending along the penetrating electrode, a concave shape in a direction toward the penetrating electrode, or a wave shape in which a concave shape is repeated in a direction toward the penetrating electrode Lt; / RTI >

An element of this other embodiment, comprising: an integrated circuit disposed on the active surface; An interlayer insulating film provided on the active surface to cover the integrated circuit; And an upper insulating layer covering the interlayer insulating layer.

The device of another embodiment of the present invention may further include an upper wiring provided on the active surface, the interlayer insulating film, and the upper insulating film to electrically connect the penetrating electrode to the integrated circuit, And a lower wiring electrically connecting the penetrating electrode to an external device.

In the element according to another embodiment of the present invention, the upper wiring may be provided on the interlayer insulating film. The penetrating electrode may further penetrate the interlayer insulating film and be connected to the upper wiring. The air gap may be provided between the inactive surface and the active surface, or may be provided between the inactive surface and the top wiring.

In the device of another embodiment of the present invention, the upper wiring may be provided on the upper insulating film. The penetrating electrode may further penetrate the interlayer insulating film and the upper wiring, and may be connected to the upper wiring. The air gap may be provided between the inactive surface and the active surface, or may be provided between the inactive surface and the top wiring.

In the device of another embodiment of the present invention, the upper wiring may be provided on the active surface. The penetrating electrode may be connected to the upper wiring through the substrate. The air gap may be provided between the inactive surface and the upper wiring.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: providing a substrate including an upper surface and a lower surface opposite to the upper surface; Forming a penetrating electrode partially penetrating the substrate from the upper surface toward the lower surface; Defining an inactive surface of the substrate that recesses the bottom surface to expose a portion of the through electrode; Forming a trench that surrounds the penetrating electrode and separates the penetrating electrode from the substrate; Forming a lower insulating film covering the inactive surface; And forming an air gap surrounded by the lower insulating film in the trench.

In the method of this embodiment, the substrate may be planarized to remove a portion of the penetrating electrode protruding from the inactive surface. The substrate may be planarized after the air gap is formed.

In the method of this embodiment, forming the penetrating electrode may include: forming a hole in the substrate extending from the upper surface toward the lower surface; Forming a liner film extending along an inner wall of the hole; And forming a conductive film covering the liner film in the hole to fill the hole.

In the method of this embodiment, forming the trench may include etching the portion of the substrate surrounding the penetrating electrode to form the trench surrounding the penetrating electrode. The trench may expose an inner surface of the substrate spaced apart from the liner film surrounding the sidewall of the penetrating electrode, and may have an opening at one side facing the inactive surface.

In the method of this embodiment, forming the penetrating electrode may include: forming a hole in the substrate extending from the upper surface toward the lower surface; Forming a sacrificial film and a liner film extending along the inner wall of the hole; And forming a conductive film covering the liner film and the sacrificial film in the hole and filling the hole.

In the method of this embodiment, forming the trench may include: recessing the lower surface to expose the liner film and the sacrificial film; And selectively etching the sacrificial layer to form the trench surrounding the penetrating electrode.

In the method of this embodiment, forming the liner film and the sacrificial film may include forming the liner film that covers the sacrificial film after forming the sacrificial film covering the inner wall of the hole. The forming of the trench may include etching the sacrificial film formed between the liner film and the substrate. The trench may expose an inner surface of the substrate spaced apart from the liner film surrounding the sidewall of the penetrating electrode, and may have an opening at one side facing the inactive surface.

In the method of the present embodiment, forming the liner film and the sacrificial film may include forming the sacrificial film covering the liner film after forming the liner film covering the inner wall of the hole. The forming of the trench may include etching the sacrificial layer formed between the penetrating electrode and the liner film. The trench exposes a sidewall of the penetrating electrode that is spaced apart from the liner film covering the inner surface of the substrate and the liner film. The trench may have an opening at one side facing the inactive surface.

In the method of the present embodiment, forming the trench may further include etching the exposed portion of the liner film through the inactive surface.

In the method of the present embodiment, forming the lower insulating film may include: forming an external insulating film covering the inactive surface; And forming an inner insulating film extending from the outer insulating film and extending to the inside of the trench, the inner insulating film forming a wall surrounding the air gap by sealing an inlet of the trench.

In the method of the present embodiment, forming the lower insulating film may include: forming a first lower insulating film including an external insulating film covering the inactive surface of the substrate and an internal insulating film extending from the external insulating film of the substrate to seal the entrance of the trench, Forming; And a second insulating layer provided between the inactive surface of the substrate and the external insulating layer and inside the trench so as to cover the inactive surface of the substrate together with the external insulating layer and form a wall surrounding the air gap, And forming a lower insulating film. The second lower insulating film may be formed, and then the first lower insulating film may be formed.

In the method of the present embodiment, at least one of forming an upper wiring connected to the penetrating electrode on the upper surface of the substrate, and forming a lower wiring connected to the penetrating electrode on the inactive surface of the substrate As shown in FIG.

According to the present invention, since a gap filled with vacuum or air is provided between the through electrode and the substrate, the dielectric constant is very close to 1 or 1, so that an excellent electrical insulating effect can be obtained. Further, since the liner film covering the side wall of the penetrating electrode exposed through the gap is further provided, when the penetrating electrode is expanded or twisted, contact with the substrate can be prevented, thereby eliminating defective phenomena such as short- Furthermore, since the lower insulating film covering the lower surface of the substrate is further extended into the air gap, the contact between the penetrating electrode and the substrate can be prevented and the stress buffer can be added. Thus, there is an effect that the structural and electrical characteristics of the semiconductor device can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. FIG.
FIG. 1B is an enlarged cross-sectional view of a portion of FIG. 1A. FIG.
Fig. 1C is a sectional view showing a modification of Fig. 1B. Fig.
FIG. 1D is an enlarged cross-sectional view of a part of FIG. 1A. FIG.
FIG. 1E is a sectional view showing a modification of FIG. 1D. FIG.
FIG. 1F is an enlarged sectional view of a part of FIG. 1A.
2A to 2J are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Figures 2k-2n are cross-sectional views illustrating variations of Figure 2j.
3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 3D is a sectional view showing a modification of Fig. 3C. Fig.
4A to 4C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
5A to 5C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
6A to 6F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Figures 6G and 6H are cross-sectional views showing variants of Figure 6F.
7A to 7F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Figures 7g and 7h are cross-sectional views showing variants of Figure 7f.
8A is a block diagram illustrating a memory card having a semiconductor device according to an embodiment of the present invention.
8B is a block diagram showing an information processing system using semiconductor devices according to an embodiment of the present invention.

Hereinafter, a semiconductor device having a penetrating electrode having an air gap insulating structure according to the present invention and a method of manufacturing the same will be described in detail with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages of the present invention and its advantages over the prior art will become apparent from the detailed description and claims that follow. In particular, the invention is well pointed out and distinctly claimed in the claims. The invention, however, may best be understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. Like reference numerals in the drawings denote like elements throughout the various views.

<Device example>

1A is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1A, a semiconductor device 1 may include a conductive connection portion 120 for vertically passing an electrical signal through a substrate 100. The conductive connection 120 may include a penetrating electrode 108 passing through the substrate 100 vertically. The conductive connection part 120 is in contact with the penetrating electrode 108 and is connected to the upper wiring 110 disposed on the upper surface 100a of the substrate 100 and the penetrating electrode 108, And a lower wiring 116 disposed on the lower wiring 116. Each of the upper surface 100a and the lower surface 100c may be a generally flat surface extending in the horizontal direction perpendicular to the thickness direction of the substrate 100. [

The upper wiring 110 may extend horizontally along the upper surface 100a of the substrate 100 and the lower wiring 116 may extend horizontally along the lower surface 100c of the substrate 100. [ At least one of the upper wiring 110 and the lower wiring 116 may be rewired. The lower wiring 116 may be provided with a solder ball 118 as a connection terminal capable of electrically connecting the semiconductor element 1 to another apparatus, for example, another semiconductor element or a printed circuit board. Although not shown in detail in the drawing, a connection terminal may be further attached to the upper wiring 110.

The penetrating electrode 108 may vertically penetrate the substrate 100 and contact the upper wiring 110 and the lower wiring 116. An electrical signal transmitted through the upper wiring 110 may be transmitted through the substrate 100 vertically through the penetrating electrode 110 to the lower wiring 116 or vice versa.

The upper surface 100a and the lower surface 100c of the substrate 100 can be covered with the protective film 124 and the lower insulating film 114, respectively. The protective film 124 and the lower insulating film 114 protect and electrically isolate the substrate 100 from the external environment. The conductive connection 120 may be electrically isolated from the substrate 100. For example, the protective film 124 electrically isolates the upper wiring 110 from the upper surface 100a of the substrate 100, and the lower insulating film 114 protects the lower wiring 116 from the lower surface 100c of the substrate 100 So that it can be electrically isolated. The penetrating electrode 108 can be electrically insulated from the inner surface 100s of the substrate 100 by the air gap 112. [ The inner surface 100s may be a generally vertical surface connecting the upper surface 100a and the lower surface 100c.

The substrate 100 may include a gap or trench 111 extending vertically along the penetrating electrode 108 to surround the penetrating electrode 108. The lower insulating film 114 formed along the lower surface 100c of the substrate 100 has an outer insulating film 114a covering the lower surface 100c and a lower insulating film 114b which hermetically seals the trench 111, And an inner insulating film 114b formed on the inner wall of the trench 111. [ The inside of the trench 111 is defined by the inner insulating film 114b formed along the inner wall of the trench 111 and an air gap 112 which is substantially perpendicular to the penetrating electrode 108 can be formed. The air gap 112 may be filled with vacuum or air. The penetrating electrode 108 and the substrate 100 are electrically insulated by the air gap 112 whose dielectric constant is very close to 1 or 1, so that the penetrating electrode 108 and the substrate 100 are insulated by a silicon oxide film having a dielectric constant of 3.8 to 4.2, Lt; / RTI &gt;

An insulating liner film 106 surrounding the side wall of the penetrating electrode 108 may be further formed. Liner layer 106 may include oxide or a polymer film (for example:: SiO ₂₎ or nitride film (SiN example). The liner film 106 may surround the penetrating electrode 108 and extend from the upper wiring 110 to the lower wiring 116 along the side walls thereof. The penetrating electrode 108 and the substrate 100 can be electrically insulated by the inner insulating film 114b and the liner film 106 in addition to the air gap 112. [ When the penetrating electrode 108 is made of copper which is very easy to diffuse, the liner film 106 including the nitride film (SiN) can also serve as a barrier for preventing diffusion of copper.

When the penetrating electrode 108 and the substrate 100 are made of different materials, the penetrating electrode 108 may expand or twist due to the CTE mismatch. In this case, since there is a liner film 106, an inner insulating film 114b and an air gap 112 between the penetrating electrode 108 and the substrate 100, there is a fear that the penetrating electrode 108 directly contacts the substrate 100 Not at all. In addition, when the penetrating electrode 108 is severely inflated or twisted, the internal insulating film 114b may preferentially break down. As such, the inner insulating film 114b can serve as a stress buffer, so that the stress that may be applied to the penetrating electrode 108 and / or the substrate 100 can be mitigated or eliminated.

The liner film 106, the lower insulating film 114, and the air gap 112 in the semiconductor element 1 may be variously modified in shape and structure. These variations will be clearly understood with reference to the following description.

An integrated circuit electrically connected to the conductive connection part 120, an interlayer insulating film covering the integrated circuit, and a metal wiring electrically connected to the integrated circuit are formed between the substrate 100 and the protective film 124 as described below . The penetrating electrode 108 may be classified into one of Via Last, Via Middle and Via First structures.

<Biama Middle>

Fig. 1B is an enlarged cross-sectional view of a portion of Fig. 1A. Fig. 1C is a sectional view showing a modification of Fig. 1B.

Referring to FIG. 1B, the penetrating electrode 108 may be a formed via-structure after the integrated circuit 95 is formed and before the upper wiring 110 and the metal wiring 111 are formed. The interlayer insulating film 101 is formed on the upper surface 100a of the substrate 100 and includes a first interlayer insulating film 101a covering the integrated circuit 95 and a second interlayer insulating film 101b formed on the first interlayer insulating film 101a, And a second interlayer insulating film 101b covering the metal wiring 111. [ The penetrating electrode 108 can penetrate the substrate 100 and the first interlayer insulating film 101a. The protective film 124 may be formed on the second interlayer insulating film 101b and may open the bonding pad 105 connected to the metal wiring 111. [

The trench 111 penetrates the substrate 100 so that the air gap 112 can be defined between the upper surface 100a and the lower surface 100c of the substrate 100. [ The upper wiring 110 can be electrically connected to the integrated circuit 95 so that the penetrating electrode 108 can be electrically connected to the integrated circuit 95. The upper wiring 110 may be referred to as a first metal wiring M1 and the metal wiring 111 may be referred to as a second metal wiring M2.

Referring to FIG. 1C, the trench 111 may extend through the substrate 100 and further penetrate the first interlayer insulating film 101a. Accordingly, the air gap 112 can be extended to the region where the first interlayer insulating film 101a is formed.

<Biarast>

FIG. 1D is an enlarged cross-sectional view of a part of FIG. 1A. Fig. 1E is a sectional view showing a modification of Fig. 1D.

1D, the penetrating electrode 108 penetrates the substrate 100 and is provided with an integrated circuit 95 formed on the upper surface 100a of the substrate 100 and an interlayer insulating film 101 ). &Lt; / RTI &gt; According to the present embodiment, the penetrating electrode 108 can be a via-last structure formed after the integrated circuit 95 and the metal wiring 111 are formed. A protective film 124 may be provided between the upper wiring 110 and the interlayer insulating film 101 and the penetrating electrode 108 may penetrate the protective film 124 further.

The trench 111 penetrates the substrate 100 so that the air gap 112 can be defined between the top surface 100a and the bottom surface 100c of the substrate 100. [ The upper wiring 110 may be electrically connected to the integrated circuit 95 via a bonding pad 105. [ A part of the upper wiring 110 may be extended to contact the bonding pad 105. The metal wiring 111 may be referred to as a first metal wiring M1 and the upper wiring 110 may be referred to as a second metal wiring M2.

Referring to FIG. 1E, the trench 111 can further penetrate the interlayer insulating film 101 in addition to the substrate 100, and the air gap 112 can be extended to the region where the interlayer insulating film 101 is formed.

<Via First>

FIG. 1F is an enlarged sectional view of a part of FIG. 1A.

Referring to FIG. 1F, the penetrating electrode 108 may be a via-first structure formed before the integrated circuit 95, the upper wiring 110, and the metal wiring 111 are formed. An interlayer insulating film 101 may be formed on the upper surface 100a of the substrate 100. [ The interlayer insulating film 101 covers the first interlayer insulating film 101a covering the integrated circuit 95 and the upper wiring 110 and the bonding pad 105 covering the metal wiring 111 formed on the first interlayer insulating film 101a. The second interlayer insulating film 101b exposing the second interlayer insulating film 101b. The upper wiring 110 may be referred to as a first metal wiring M1 and the metal wiring 111 may be referred to as a second metal wiring M2.

The trench 111 penetrates the substrate 100 so that the air gap 112 can be defined from the upper surface 100a to the lower surface 100c of the substrate 100. [ The upper wiring 110 may be electrically connected to the integrated circuit 95 via the metal wiring 111 or directly. An insulating film 109 may be further formed on the upper surface 100a of the substrate 100 to insulate the upper wiring 110 from the substrate 100. [ As another example, the liner film 106 may extend to the upper surface 100a of the substrate 100 and be further formed between the upper wiring 110 and the upper surface 100a of the substrate 100. [

<Method Example 1>

2A to 2J are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2A, a substrate 100 may be provided. The substrate 100 may be composed of silicon or a semiconductor containing silicon. The upper insulating film 102 may be formed on the upper surface 100a of the substrate 100. [ A hole 104 having a depth penetrating the upper insulating film 102 and not reaching the lower surface 100b of the substrate 100 can be formed. The hole 104 can be formed by an etching or laser drilling process. Each of the upper surface 100a and the lower surface 100b may be a flat surface in a substantially horizontal direction.

The fabrication method of this embodiment can be applied to implement both non-ferromagnetic, non-ferromagnetic, and non-ferrous structures. 1B or 1C, the upper insulating film 102 may be the first interlayer insulating film 101a shown in FIG. 1B, and the upper surface 100a of the substrate 100 may have a first An integrated circuit 95 covered with an interlayer insulating film 101a may be formed. 1D or 1E, the upper insulating film 102 may be an interlayer insulating film 101 and the upper surface 100a of the substrate 100 may be covered with an interlayer insulating film 101. In this case, An integrated circuit 95 and a metal wiring 111 may be formed. For example, in the case of implementing the via-first structure as shown in FIG. 1F, the upper insulating film 102 may be an insulating film 109, and the substrate 100 may be a bare wafer in which no integrated circuit is formed.

Referring to FIG. 2B, a liner film 106 may be formed. The liner film 106 can be formed by depositing an insulating material such as an oxide film (e.g., SiOx) or a nitride film (e.g., SiNx) or a polymer film. The liner film 106 may be conformally deposited along the inner wall of the hole 104 to have a U-shape. The liner film 106 may be formed not only on the inner wall of the hole 104 but also on the upper insulating film 102. [

Referring to FIG. 2C, the hole 104 may be filled with a conductor to form the penetrating electrode 108. The penetrating electrode 108 may be formed by a process such as deposition, epitaxial growth, plating, or the like, such as polysilicon, metal, or a combination thereof. For example, metal or polysilicon such as copper or tungsten may be deposited relatively thick on the substrate 100, and the penetrating electrode 108 may be formed by planarizing the upper insulating film 102 to expose it. When the penetrating electrode 108 is formed of copper, it may be necessary to form a barrier film capable of preventing diffusion of copper. According to an example, when the liner film 106 is formed of a nitride film (e.g., SiN, Si ₃ N ₄ ), the liner film 106 may serve as a barrier of copper, so that the necessity of further forming a separate barrier film is reduced It may be absent.

Referring to FIG. 2D, an upper wiring 110 connected to the penetrating electrode 108 may be formed on the upper surface 100a of the substrate 100 selectively. The upper wiring 110 may be formed by depositing or plating a metal. As another example, it is possible to simultaneously form the penetrating electrode 108 and the upper wiring 110 by depositing and patterning a metal having a comparatively sufficient thickness so that the hole 104 is filled on the upper surface 100a of the substrate 100. [ As another example, the process of forming the upper wiring 110 can be skipped.

Referring to FIG. 2E, the bottom surface 100b of the substrate 100 may be recessed to expose the penetrating electrode 108. FIG. The recess process may be performed by using an etching process using an etchant capable of selectively removing a material constituting the substrate 100, for example, silicon, until the bottom surface 100c capable of exposing the penetrating electrode 106 is exposed You can proceed. As another example, the penetrating electrode 108 can be exposed by grinding the surface 100d to such an extent that the penetrating electrode 108 is not exposed by the grinder and etching the surface 100d. As another example, the recessing process can be carried out by a chemical mechanical polishing process. As another example, the substrate 100 may be removed to the face 100d by a grinding or chemical-mechanical polishing process, and the face 100d may be spin-etched. Spin etching can proceed by providing an etchant to the surface 100d while rotating the substrate 100. [ Spin etching can be dry or wet etching. For example, spin etching can be performed by providing a mixed solution of hydrofluoric acid and nitric acid or a vapor state of the mixed solution on the surface 100d. As another example, spin etching may be performed by using a mixed gas containing hydrogen bromide (HBr) and chlorine (Cl ₂ ), a mixed gas containing sulfur hexafluoride (SF ₆ ) and chlorine (Cl ₂ ) (Cl ₂ ) and sulfur hexafluoride (SF ₆ ) to the surface (100d). The recessing process can be performed in a relatively short period of time by, for example, in-situ grinding or chemical-mechanical polishing and spin etching. A supporting member 93 such as a tape or a glass substrate may be adhered to the substrate 100 during the recessing process so that the supporting member 93 can support the substrate 100 and prevent the top surface 100a from being damaged have. The upper surface 100a of the substrate 100 may be an active surface, and the lower surface 100c may be an inactive surface. The bottom surface 100c may be substantially flat in the horizontal direction. In this specification, the upper surface 100a is referred to as an active surface and the lower surface 100c is used in combination with the term inactive surface.

Referring to FIG. 2F, a mask 92 may be formed on the inactive surface 100c of the substrate 100. FIG. For example, after the substrate 100 is turned upside down so that the active face 100a faces downward and the inactive face 100c faces upward, the substrate 100 is surrounded and penetrated around the through electrode 108 by coating and patterning of the photoresist, A mask 92 spaced apart from the sidewalls of the electrode 108 may be formed. The trench 111 can be formed by partially removing the substrate 100 by the etching process using the mask 92. [ The trenches 111 may be blocked by the upper insulating film 102 at one side and opened at the opposite side. The mask 92 may be removed by an ashing process.

According to the present embodiment, an anisotropic dry process may be used to form the trenches 111 extending along the penetrating electrode 108 and surrounding the penetrating electrode 108. The inner surface 100s of the substrate 100 and the liner film 106 surrounding the penetrating electrode 108 can be exposed by the trench 111. [ The distance W1 between the inner surface 100s of the substrate 100 and the liner film 106 or the trench 111 may be substantially the same along the penetrating electrode 108. [ As another example, the width W1 of the trench 111 may become smaller or larger along the penetrating electrode 108. [ The inner surface 100s may be a surface extending substantially straight or obliquely linearly connecting the active surface 100a and the inactive surface 100c.

Referring to FIG. 2G, the lower insulating film 114 may be formed by depositing an oxide, a nitride, or a polymer by a deposition process (e.g., CVD). The lower insulating film 114 extending from the inactive surface 100c of the substrate 100 to the inside of the trench 111 may be formed according to the step coverage characteristic or the deposition process condition. The lower insulating film 114 is extended to the inside of the trench 111 and the overhang 114d is intentionally generated at or near the entrance of the trench 111 so that the entrance of the trench 111 is connected to the lower insulating film 114).

Referring to FIG. 2H, the trench 111 may be closed by the lower insulating layer 114 to form the air gap 112. The lower insulating film 114 may include an external insulating film 114a covering the inactive surface 114a of the substrate 100 and an internal insulating film 114b extending into the inside of the trench 111. [ The protruding portion 108b of the penetrating electrode 108 protruding from the inactive surface 100c can be surrounded by the lower insulating film 114. [ An air gap 112 surrounded by the inner insulating film 114a may be formed in the trench 111. [ The air gap 112 is generally filled with air and can have a dielectric constant close to one. Or the air gap 112 may be in a vacuum state so that the dielectric constant may be one. The penetrating electrode 108 and the inner surface 100s of the substrate 100 are spaced apart by the liner film 106, the air gap 112 having a very low dielectric constant (e.g., approximately 1), and the inner insulating film 114b It can be electrically insulated.

Referring to FIG. 2i, protrusions (108b in FIG. 2H) of the penetrating electrode 108 can be removed by a planarization process. The planarization process may be carried out by employing a chemical mechanical polishing process, a grinding process, a dry process, or a combination thereof. The planarization process can proceed to such an extent that the external insulating film 114a remains on the inactive surface 100c. The liner film 106 and the lower insulating film 114 that surround the protruding portion 108b of the penetrating electrode 108 can be removed together during the planarization process.

Referring to FIG. 2J, a lower wiring 116 connected to the penetrating electrode 108 can be selectively formed on the non-active surface 100c of the substrate 100. FIG. Thus, a semiconductor element 1 similar to that shown in Fig. 1A can be formed. The lower wiring 116 can be rewired. A solder ball 118 may be further connected to the lower wiring 116 as a connection terminal. As another example, the solder ball 118 may be directly attached to the penetrating electrode 108 without forming the lower wiring 116. As another example, a solder ball may be further attached on the upper wiring 110. As another example, if the upper wiring 110 is not formed, a solder ball may be attached to the penetrating electrode 108.

&Lt; Modifications of Method Example 1 >

Figures 2k to 2n are cross-sectional views illustrating variations of Figure 2j. The modifications shown in Figs. 2k to 2n may be applied to all the embodiments disclosed herein.

Referring to FIG. 2K, the liner film 106 may be formed to cover the upper insulating film 102 as described above with reference to FIG. 2B. Thus, the liner film 106 can extend over the active surface 100a of the substrate 100 at the sidewall of the penetrating electrode 108. [

Referring to FIG. 21, the trench 111 may be formed further through the upper insulating film 102, so that the air gap 112 can be expanded. When forming the extended trench 111, the liner film 106 may be etched together with the upper insulating film 102, and etch damage may be applied to the sidewalls of the penetrating electrode 108. In order to prevent the liner film 106 from being etched, the upper insulating film 102 and the liner film 106 may be formed of a material having an etch selectivity ratio.

Referring to FIG. 2m, an insulator may be deposited relatively quickly on the inactive surface 100c to cause overhang at the entrance of the trench 111 and to prevent the insulator from further expanding into the interior of the trench 111. The lower insulating film 114 including the inner insulating film 114b covering the entrance of the trench 111 and the outer insulating film 114a covering the inactive surface 100c can be formed. The trench 111 may be formed as an air gap 112 by being sealed by an inner insulating film 114b. The penetrating electrode 108 and the inner surface 100s of the substrate 100 are spaced apart and electrically insulated by the liner film 106 and the air gap 112. The liner film 106 can prevent direct contact between the inner surface 100s of the substrate 100 and the penetrating electrode 108. [

Referring to Figure 2n, the process of forming the liner film 106 may be skipped. The inner insulating film 114b covers the sidewall of the penetrating electrode 108 and can serve as a liner film.

&Lt; Method 2 >

3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 3D is a sectional view showing a modification of FIG. 3C.

Referring to FIG. 3A, the substrate 100 may be selectively etched by a similar process as described with reference to FIGS. 2A to 2F to form a trench 111 surrounding the through electrode 108. FIG. The second lower insulating film 134 may be formed before forming the lower insulating film 114 (FIG. 3B). The second lower insulating film 134 may be formed in a bent shape along the profile of the inactive surface 100c of the substrate 100. [ The second lower insulating film 134 may be formed in conformity with the inner wall of the trench 111 so that the liner film 106 and the second lower insulating film 134 are overlapped on the sidewalls of the penetrating electrode 108 . The second lower insulating film 134 may be formed to cover the passive surface 100c of the substrate 100 and surround the penetrating electrode 108. [ As an example, a deposition process having a relatively slow growth rate such that the second lower insulating film 134 is formed by depositing an insulator (e.g., an oxide film, a nitride film, a polymer or the like) but not the entrance of the trench 111 .

Referring to FIG. 3B, a lower insulating layer 114 may be formed on the second lower insulating layer 134. For example, the insulator may be relatively rapidly deposited on the second lower insulating film 134 to cause an overhang at the entrance of the trench 111 to form the lower insulating film 114. The lower insulating film 114 may include an external insulating film 114a covering the second lower insulating film 134 on the inactive surface 100c and an internal insulating film 114b covering the entrance of the trench 111. [ The inner insulating film 114b may not extend further into the inside of the trench 111. [ According to this embodiment, the air gap 112 surrounded by the second lower insulating film 134 and the inner insulating film 114a may be formed. A double layer structure in which an external insulating layer 114a is laminated on the second lower insulating layer 134 may be formed on the inactive surface 100c of the substrate 100. Inside the trench 111, ) May be formed.

Referring to FIG. 3C, the projecting portion (108b in FIG. 3B) of the penetrating electrode 108 can be removed by the planarization process. Alternatively, the lower wiring 116 connected to the penetrating electrode 108 can be further formed. The lower insulating film 114, the second lower insulating film 134, and the liner film 106 that surround the protruding portion 108b of the penetrating electrode 108 can be further removed by the planarization process. An air gap 112 is formed between the penetrating electrode 108 and the inner surface 100s of the substrate 100 so that the penetrating electrode 108 can be electrically insulated from the substrate 100. [ A liner film 106 and a second lower insulating film 134 are formed on the sidewalls of the penetrating electrode 108. A second lower insulating film 134 is formed on the inner surface 100s of the substrate 100 Contact between the inner surface 100s of the substrate 100 and the penetrating electrode 108 can be prevented. When the penetrating electrode 108 includes copper, at least one of the liner film 106 and the second lower insulating film 134 may be formed of a nitride film to serve as a copper diffusion barrier film.

As another example, as shown in FIG. 3D, a planarization process (see FIG. 3B) in which the protruding portion (108b in FIG. 3B) of the penetrating electrode 108 is removed without forming the lower insulating film 134 after the second lower insulating film 134 is formed . The solder ball 119 may be attached to the penetrating electrode 108. According to the present embodiment, the trench 111 has an open shape and can serve as an air gap provided between the penetrating electrode 108 and the inner surface 100s of the substrate 100. [

&Lt; Method 3 >

4A to 4C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 4A, the substrate 100 may be selectively etched by a similar process as described with reference to FIGS. 2A to 2F to form the trench 111 surrounding the through electrode 108. FIG. For example, a mask 92 may be formed on the inactive surface 100c of the substrate 100, and the substrate 100 may be etched by isotropic dry etching using a mask 92 to form the trench 111. [ The substrate 100 covered with the mask 92 is undercut so that the inner surface 100s of the substrate 100 may have a substantially concave shape in a direction looking at the penetrating electrode 108. [ Accordingly, the trench 111 can have a convex profile whose width W2 increases and then decreases along the penetrating electrode 108. [0050]

Referring to FIG. 4B, a lower insulating layer 114 covering the inactive surface 100c of the substrate 100 and the protruding portion 108b of the penetrating electrode 108 can be formed. The lower insulating film 114 may include an external insulating film 114a covering the inactive surface 100c and an internal insulating film 114b extending into the inside of the trench 111 and blocking the entrance of the trench 111. [ Accordingly, an air gap 112 having a generally convex profile surrounded by the inner insulating film 114b may be formed in the trench 111. [

Referring to FIG. 4C, the projecting portion (108b in FIG. 4B) of the penetrating electrode 108 can be removed by the planarization process. A lower wiring 116 and / or a solder ball 118 which selectively connects to the penetrating electrode 108 can be further formed. According to this example, the air gap 112 can have a convex profile, so that the possibility of contact between the penetrating electrode 108 and the substrate 100 can be minimized.

&Lt; Method 4 >

5A to 5C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 5A, the substrate 100 may be selectively etched by a similar process as described with reference to FIGS. 2A to 2F to form the trench 111 surrounding the through electrode 108. FIG. For example, the isotropic etching and the polymer deposition may be repeated several times to remove a portion of the substrate 100 adjacent to the penetrating electrode 108. According to this, the inner surface 100s of the substrate 100 can be formed with a scallop-shaped trench 111 by repeating the undercutted concave shape. The width W3 of the trench 111 can be repeatedly increased or decreased along the side wall of the penetrating positive electrode 108. [ As the number of repetitions of the isotropic etching and the polymer deposition is increased, the inner surface 100s of the substrate 100 may be changed from a scallop pattern to a flat pattern. Accordingly, even if an isotropic etching process is used, the trench 111 having vertical sidewalls similar to those using the anisotropic etching process can be formed.

Referring to FIG. 5B, a lower insulating layer 114 covering the inactive surface 100c of the substrate 100 and the protruding portion 108b of the penetrating electrode 108 can be formed. The lower insulating film 114 may include an external insulating film 114a covering the inactive surface 100c of the substrate 100 and an internal insulating film 114b extending into the interior of the trench 111. [ An air gap 112 having a generally wavy profile surrounded by an inner insulating film 114a may be formed inside the trench 111. [

5C, the protruding portion (108b in FIG. 5B) of the penetrating electrode 108 is removed by the planarizing process and the lower wiring 116 and / or the solder ball 118 selectively connected to the penetrating electrode 108 .

&Lt; Method 5 >

6A to 6F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. Figs. 6G and 6H are cross-sectional views showing variations of Fig. 6F.

6A, a hole 104 is formed by etching or laser drilling a substrate 100, and a sacrificial layer 136 and a liner layer 106 are formed in the hole 104. The liner film 106 and the sacrificial film 136 can be formed by depositing an oxide film, a nitride film, or a polymer film. The sacrificial layer 136 may be formed in a U-shape along the inner wall of the hole 104. As another example, the sacrificial layer 136 may be formed in a shape that extends along the inner wall of the hole 104 and along the active surface 100a of the substrate 100. The liner film 106 may be formed in a form that covers the sacrificial layer 136 and the active surface 100a of the substrate 100 by depositing a sacrifice layer 136 and a material having an etch selectivity. For example, the liner film 106 may be formed of an oxide film or a nitride film, and the sacrifice film 136 may be formed of a polymer film. As another example, the liner film 106 may be formed of a polymer film or nitride film and the sacrificial film 136 may be formed of an oxide film or vice versa. As another example, when the substrate 100 is composed of monocrystalline silicon, the sacrificial layer 136 may be formed of polycrystalline silicon, and the liner layer 106 may be formed of an oxide layer or a nitride layer.

Referring to FIG. 6B, a penetrating electrode 108 may be formed in the hole 104. The penetrating electrode 108 may be formed to cover the liner film 106 in the hole 104. The upper wiring 110 connected to the penetrating electrode 108 can be further formed. As another example, the penetrating electrode 108 and the upper wiring 110 can be formed at the same time. As another example, the formation process of the upper wiring 110 can be skipped.

Referring to FIG. 6C, the substrate 100 may be etched by using an etchant, a grinding process, a chemical mechanical polishing process, a spin etching process, or a combination thereof, It is possible to recess the lower surface 100b of the base 100. The thickness of the substrate 100 is reduced by the recesses, and an inactive surface 100c for exposing the penetrating electrode 108 can be produced. The recess process may expose a portion of the sacrificial layer 136 surrounding the penetrating electrode 108.

Referring to FIG. 6D, the sacrificial layer 136 may be removed by etching using an etchant capable of selectively removing the sacrificial layer 136 (FIG. 6C). In one example, the sacrificial layer 136 can be removed after the substrate 100 is turned upside down. Accordingly, the trench 111 extending along the penetrating electrode 108 can be formed. If the sacrificial layer 136 is formed of a polymer layer, the sacrifice layer 136 may be removed by an ashing process to form the trench 111. Polycrystalline silicon and single crystal silicon may have different etching rates. For example, when the sacrifice layer 136 is formed of polycrystalline silicon, the sacrifice layer 136 is selectively removed because the etching rate is relatively larger than that of the substrate 100, which is a single crystal silicon, to form the trench 111 have.

Referring to FIG. 6E, a lower insulating film 114 covering the inactive surface 100c of the substrate 100 and the protruding portion 108b of the penetrating electrode 108 can be formed. The lower insulating film 114 includes an external insulating film 114a covering the inactive surface 100c of the substrate 100 and an internal insulating film 114b extending to the inside of the trench 111 to block the entrance of the trench 111 . An air gap 112 surrounded by the inner insulating film 114a may be formed inside the trench 111. [

Referring to FIG. 6F, the projecting portion (108b in FIG. 6E) of the penetrating electrode 108 can be removed by the planarization process. Alternatively, the lower wiring 116 and / or the solder ball 118 connected to the penetrating electrode 108 may be further formed. According to the present embodiment, since the trench 111 can be formed without etching the substrate 100, etching damage to the substrate 100 can be eliminated.

As another example, an upper insulating film 102 may be further formed on the active surface 100a of the substrate 100, as shown in FIG. 6G. The trench 111 may be formed further through the upper insulating film 102 so that the air gap 112 may extend toward the upper wiring 110.

6H, the inner insulating film 114b of the lower insulating film 114 can be limitedly extended to the inside of the trench 111 to such an extent that the opening of the trench 111 can be blocked. The air gap 112 may not be surrounded by the inner insulating film 114b.

&Lt; Method 6 >

7A to 7F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. Figs. 7G and 7H are cross-sectional views showing variations of Fig. 7F.

Referring to FIG. 7A, a hole 104 may be formed by etching or laser drilling a substrate 100, and a liner film 106 may be formed in the hole 104. The liner film 106 may have a U-shape along the inner wall of the hole 104. As another example, the liner film 106 may be formed in a shape that extends along the inner wall of the hole 104 and along the active surface 100a of the substrate 100. The sacrificial film 136 can be formed in the hole 104. [ The sacrificial layer 136 may be formed by depositing a material having an etch selectivity with the liner layer 106 to cover the liner layer 106 in the hole 104. For example, the liner film 106 may be formed of an oxide film or a nitride film, and the sacrifice film 136 may be formed of a polymer film. As another example, the liner film 106 may be formed of a polymer film or nitride film and the sacrificial film 136 may be formed of an oxide film or vice versa. As another example, the sacrificial film 136 may be formed of a polysilicon film and the liner film 106 may be formed of a nitride film, an oxide film, or a polymer film.

Referring to FIG. 7B, a penetrating electrode 108 may be formed in the hole 104. The penetrating electrode 108 may be formed to cover the sacrificial layer 136 in the hole 104. The upper wiring 110 connected to the penetrating electrode 108 can be further formed. The penetrating electrode 108 and the upper wiring 110 can be formed at the same time. Or the upper wiring 110 may not be formed.

Referring to FIG. 7C, the bottom surface 100b of the substrate 100 may be recessed to expose the penetrating electrode 108 by etching, grinding, chemical mechanical polishing, spin etching, or a combination thereof. The substrate 100 may have a reduced thickness and an inactive surface 100c closer to the active surface 100a than the bottom surface 100b by the recess process. The liner film 106 can be exposed from the inactive surface 100c and can selectively remove the exposed liner film 106. [

Referring to FIG. 7D, the sacrificial layer 136 may be removed by etching using an etchant capable of selectively removing the sacrificial layer 136 (FIG. 7C). Accordingly, the trench 111 extending along the penetrating electrode 108 can be formed. According to the present embodiment, the liner film 106 may be provided on the inner surface 100s of the substrate 100. [

7E, a lower insulating film 114 covering the inactive surface 100c of the substrate 100 and the protruding portion 108b of the penetrating electrode 108 can be formed. The lower insulating film 114 has an outer insulating film 114a covering the inactive surface 114a of the substrate 100 and an outer insulating film 114b extending into the trench 111 to form an air gap 112 by blocking the inlet of the trench 111 And may include an inner insulating film 114b.

7F, the protruding portion (108b in FIG. 7E) of the penetrating electrode 108 is removed by the planarization process and the lower wiring 116 and / or the solder ball 118 selectively connected to the penetrating electrode 108 . Even if the liner film 106 is formed on the inner surface 100s of the substrate 100 according to the present embodiment, since the inner insulating film 114b can be formed by being extended to the inside of the trench 111, The same structure as that in which the liner film is formed on the sidewall of the sidewall is obtained.

As another example, an upper insulating film 102 may be further formed on the active surface 100a of the substrate 100, as shown in FIG. 7G. The trench 111 may be formed further through the upper insulating film 102 so that the air gap 112 can extend toward the upper wiring 110.

7H, the inner insulating film 114b of the lower insulating film 114 can be limitedly extended to the inside of the trench 111 to such an extent that the opening of the trench 111 can be blocked.

<Application example>

8A is a block diagram illustrating a memory card having a semiconductor device according to an embodiment of the present invention.

8A, a memory card 1200 may include a memory controller 1220 that controls the overall exchange of data between a host and a memory 1210. The SRAM 1221 may be used as an operating memory of the central processing unit 1222. [ The host interface 1223 may have a data exchange protocol of the host connected to the memory card 1200. [ The error correction code 1224 can detect and correct an error included in the data read from the memory 1210. The memory interface 1225 interfaces with the memory 1210. The central processing unit 1222 can perform all control operations for data exchange of the memory controller 1220. [ The memory 1210 may include a semiconductor memory device 1 having a penetrating electrode according to an embodiment of the present invention.

8B is a block diagram illustrating an information processing system using semiconductor devices according to an embodiment of the present invention.

8B, an information processing system 1300 may include a memory system 1310 with semiconductor devices 1 according to an embodiment of the present invention. The information processing system 1300 may include a mobile device, a computer, or the like. In one example, the information processing system 1300 includes a memory system 1310, a modem 1320, a central processing unit 1330, a RAM 1340, and a user interface 1350 that are electrically coupled to the system bus 1360 . The memory system 1310 may include a memory 1311 and a memory controller 1312 and may be configured substantially the same as the memory card 1200 of FIG. 8A. The memory system 1310 may store data processed by the central processing unit 1330 or externally input data. The information processing system 1300 may be provided as a memory card, a solid state disk, a camera image sensor, and other application chipsets.

It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and it will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit of the invention. The appended claims should be construed to include other embodiments.

Claims (32)

A substrate comprising an active surface and an inactive surface opposite thereto;
A penetrating electrode passing through the substrate;
A trench provided between the substrate and the penetrating electrode;
An insulating liner film provided on a sidewall of the penetrating electrode; And
A lower insulating layer covering an inactive surface of the substrate and extending into the trench to form an air gap between the substrate and the penetrating electrode in the trench;
Including,
Wherein the lower insulating film comprises:
An external insulating layer covering the inactive surface of the substrate; And
And an inner insulating film extending from the outer insulating film to extend into the trench and defining an air gap by sealing an inlet of the trench,
The inner walls of the trench and the insulating liner film are partially exposed to the air gap, and the inner walls of the exposed trench and the exposed insulating liner film define the edge of the air gap. The method according to claim 1,
Wherein the distance between the substrate and the penetrating electrode is thicker than the thickness of the insulating liner film. delete delete The method according to claim 1,
And an upper insulating layer covering an active surface of the substrate, wherein the trench is open at one side toward the inactive surface of the substrate and the other side toward the active surface of the substrate is sealed by the upper insulating layer. 6. The method of claim 5,
Further comprising an interlayer insulating film provided between the substrate and the upper insulating film, wherein the penetrating electrode further penetrates the interlayer insulating film. The method according to claim 6,
Wherein the air gap extends vertically along a side wall of the penetrating electrode between an inactive surface and an active surface of the substrate. The method according to claim 6,
Wherein the air gap extends vertically along the side wall of the penetrating electrode between the inactive surface of the substrate and the upper insulating film. A substrate comprising an active surface and an inactive surface opposite thereto;
A penetrating electrode passing through the substrate;
A trench provided between the substrate and the penetrating electrode;
An insulating liner film provided on a sidewall of the penetrating electrode; And
And a lower insulating layer covering the inactive surface of the substrate and extending to the inside of the trench to form an air gap between the substrate and the penetrating electrode in the trench,
Wherein the lower insulating film includes a first lower insulating film and a second lower insulating film,
Wherein the first lower insulating film includes an outer insulating film covering the inactive surface of the substrate and an inner insulating film extending from the outer insulating film to seal the trench; And
Wherein the second lower insulating film is provided between the inactive surface of the substrate and the external insulating film and into the trench so as to cover the inactive surface of the substrate with the external insulating film and define the air gap with the internal insulating film A semiconductor device that forms a wall.
A substrate including a horizontal active surface, an inactive surface opposite to the active surface, and an inner surface connecting the active surface and the inactive surface;
A penetrating electrode vertically penetrating the substrate and spaced apart from the inner surface of the substrate;
An air gap extending between the inner surface of the substrate and a sidewall of the penetrating electrode, the air gap extending along the penetrating electrode;
An insulating liner film between the inner surface of the substrate and the penetrating electrode; And
And a lower insulating film defining the air gap,
Wherein the substrate has a trench provided between the substrate and the penetrating electrode,
Wherein the lower insulating film comprises:
An external insulating film covering the inactive surface; And
And an inner insulating film extending from the outer insulating film and extending to the inside of the trench, and sealing the entrance of the trench to define the air gap. 11. The method of claim 10,
Wherein the inner insulating film is provided on the inner surface of the substrate and the side wall of the penetrating electrode,
Wherein the inner insulating film forms a wall defining the air gap. 12. The method of claim 11,
Wherein the insulating liner film covers the side wall of the penetrating electrode,
Wherein the inner insulating film is interposed between the penetrating electrode and the air gap, and the inner insulating film is interposed between the inner surface and the air gap.
12. The method of claim 11,
Wherein the insulating liner film covers the inner surface of the substrate,
Wherein the insulating liner film and the inner insulating film are interposed between the inner surface and the air gap, and the inner insulating film is interposed between the penetrating electrode and the air gap.
12. The method of claim 11,
Wherein the external insulating film is a double film, and the internal insulating film is a single film. 11. The method of claim 10,
Said inner surface comprising:
A linear shape extending along the penetrating electrode;
A concave shape in a direction toward the penetrating electrode; And
A wave form in which a concave shape is repeated in a direction toward the through electrode;
Wherein the semiconductor device is a semiconductor device. 11. The method of claim 10,
An integrated circuit disposed on the active surface;
An interlayer insulating film provided on the active surface to cover the integrated circuit; And
An upper insulating film covering the interlayer insulating film;
. 17. The method of claim 16,
An upper wiring provided on one of the active surface, the interlayer insulating film, and the upper insulating film to electrically connect the penetrating electrode to the integrated circuit, and an upper wiring provided on the lower insulating film to electrically connect the penetrating electrode to an external device And a lower wiring connected to the semiconductor chip. 18. The method of claim 17,
The upper wiring is provided on the interlayer insulating film,
Wherein the penetrating electrode is further connected to the upper wiring through the interlayer insulating film,
Wherein the air gap is provided between the inactive surface and the active surface, or between the inactive surface and the top wiring. 18. The method of claim 17,
The upper wiring is provided on the upper insulating film,
The penetrating electrode is further connected to the upper wiring through the interlayer insulating film and the upper wiring,
Wherein the air gap is provided between the inactive surface and the active surface, or between the inactive surface and the top wiring. 18. The method of claim 17,
The upper wiring is provided on the active surface,
The penetrating electrode is connected to the upper wiring through the substrate,
And the air gap is provided between the inactive surface and the upper wiring. Providing a substrate comprising an upper surface and a lower surface opposite to the upper surface;
Forming a penetrating electrode partially penetrating the substrate from the upper surface toward the lower surface;
Defining an inactive surface of the substrate that recesses the bottom surface to expose a portion of the through electrode;
Forming a trench that surrounds the penetrating electrode and separates the penetrating electrode from the substrate;
Forming a lower insulating film covering the inactive surface; And\
Forming an air gap surrounded by the lower insulating film in the trench,
The penetrating electrode is formed by:
Forming a hole in the substrate extending from the upper surface toward the lower surface;
Forming an insulating liner film and a sacrificial film extending along the inner wall of the hole; And
And forming a conductive film covering the insulating liner film and the sacrificial film to fill the hole. Providing a substrate comprising an upper surface and a lower surface opposite to the upper surface;
Forming a penetrating electrode partially penetrating the substrate from the upper surface toward the lower surface;
Defining an inactive surface of the substrate that recesses the bottom surface to expose a portion of the through electrode;
Forming a trench that surrounds the penetrating electrode and separates the penetrating electrode from the substrate;
Forming a lower insulating film covering the inactive surface; And\
Forming an air gap surrounded by the lower insulating film in the trench,
The penetrating electrode is formed by:
Forming a hole in the substrate extending from the upper surface toward the lower surface;
Forming an insulating liner film and a sacrificial film extending along the inner wall of the hole; And
Forming a conductive film covering the insulating liner film and the sacrificial film and filling the holes;
Wherein the semiconductor device is a semiconductor device. delete delete delete delete delete delete delete delete delete delete

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