CN114852948B

CN114852948B - MEMS sensor integrated device based on through silicon via and manufacturing method thereof

Info

Publication number: CN114852948B
Application number: CN202210474084.7A
Authority: CN
Inventors: 王琛; 张思勉; 武逸飞; 邓晓楠; 柯声贤
Original assignee: Tsinghua University
Current assignee: Tsinghua University
Priority date: 2022-04-29
Filing date: 2022-04-29
Publication date: 2024-04-02
Anticipated expiration: 2042-04-29
Also published as: CN114852948A

Abstract

The present disclosure relates to a through silicon via based MEMS sensor integrated device and a method of manufacturing the same. The device comprises: a plurality of sensors vertically stacked and an interconnection layer between the sensors, each sensor including a sensor body and a substrate carrying the sensor body and provided with a plurality of through silicon vias; the test electrode of the sensor main body is positioned above the matrix and connected to the corresponding through silicon vias, and the sensitive material layer covers the test electrode; the sensitive layer holes of each interconnection layer are used for accommodating sensitive material layers of the sensors below; two ends of interconnection lines respectively arranged in a plurality of line through holes of each interconnection layer are respectively connected to the test electrode of the lower sensor and the silicon through holes of the upper sensor, each silicon through hole in each sensor respectively belongs to different silicon through hole groups, the silicon through holes in each silicon through hole group are connected in series through the interconnection lines, and symmetry axes of the silicon through holes in at least one silicon through hole group coincide. The device has higher integration density, smaller package size, lower power consumption and cost and wide application range.

Description

MEMS sensor integrated device based on through silicon via and manufacturing method thereof

Technical Field

The disclosure relates to the technical field of integrated circuit packaging, in particular to a MEMS sensor integrated device based on a through silicon via and a manufacturing method thereof.

Background

As the level of fabrication increases, microelectromechanical systems (Micro Electro Mechanical System, MEMS) technology is increasingly being applied to the sensor field. Compared with the traditional sensor, the MEMS sensor has smaller volume, lighter weight, lower power consumption and lower cost, and is more suitable for integration on intelligent equipment and wearable equipment. Therefore, MEMS sensors are becoming one of the important directions in this field.

While advancing the miniaturization of the sensor, the design of the sensor chip in the related art is challenged. For example, device miniaturization requires higher reliability and smaller volume three-dimensional packaging; the sensitive film coating process needs to be better compatible with the wafer-level preparation process; the more efficient wafer-level ball placement process and packaging process design are required. In addition, the sensor is miniaturized, and higher requirements are also put on industrial mass production of miniature sensors. The complex and tiny device structure requires more strict failure analysis and stress control in the whole production process, and targets of batch production and low cost require that the device adopts wafer-level packaging, and the preparation requirement of the sensitive film is compatible with micro-nano processing technology and wafer-level substrates.

Therefore, how to improve a thin film sensor and a method for manufacturing the same that can solve the above-mentioned problems is a need for solving the problems.

The sensor is an indispensable device for realizing the sensing of air and environment by the electronic equipment. Therefore, the sensor is widely applied to various fields such as environment, energy, petrochemical industry, medical treatment, industry, national defense and the like, and becomes one of the high and new technological development directions of various countries. Along with the development of microelectronic technology and the improvement of chip integration, the miniaturization, low power consumption and high comprehensive performance of the sensor become development trend.

The Micro-Electro-Mechanical System (MEMS) technology integrates a heating element and a sensitive element of a sensing device, and compared with the traditional ceramic substrate-based sensor, the Micro-structure gas sensor adopting the MEMS technology has the advantages of small volume, low power consumption, high sensitivity, good repeatability, easy mass production and the like, so that the Micro-structure gas sensor becomes a research hot spot.

In order to further expand the functional range and application field of the micro-sensor device, the micro-system needs to be driven to have a higher integration density, smaller package size, lower power consumption and lower cost structure. However, the typical structure of the MEMS sensor in the related art still needs to adopt a packaging mode of wire bonding lead-out electrodes, and cannot realize wafer level packaging, so that the size of the device is limited by external packaging and cannot be further reduced, the advantages of the MEMS processing technology for manufacturing the miniaturized device cannot be fully exerted, the preparation of a high-density array of the sensor is not facilitated, and the application range of the sensor is limited.

How to provide a MEMS sensor integrated device with higher integration density, smaller package size, lower power consumption and lower cost is a technical problem to be solved.

Disclosure of Invention

In view of this, the present disclosure proposes a through silicon via based MEMS sensor integrated device and a method of manufacturing the same.

According to an aspect of the present disclosure, there is provided a through silicon via based MEMS sensor integrated device, the device comprising: a plurality of sensors vertically stacked and an interconnection layer between two adjacent sensors, each of the sensors including a sensor body and a base body for carrying the sensor body;

the substrate is provided with a plurality of through silicon vias; the sensor body includes a test electrode and a layer of sensitive material; the test electrode is positioned above the matrix and connected to each corresponding through silicon via; the sensitive material layer covers a target area of the test electrode;

each interconnection layer comprises a sensitive layer hole and a plurality of wire through holes, wherein each wire through hole is provided with an interconnection wire, two ends of each interconnection wire are respectively connected to a test electrode of a sensor below the interconnection layer and a silicon through hole of a sensor above the interconnection layer, and each sensitive layer hole is used for accommodating a sensitive material layer of the sensor below the interconnection layer;

The plurality of through silicon vias in each sensor respectively belong to different through silicon via groups, each through silicon via group comprises through silicon vias which are connected in series through the interconnection lines in the plurality of through silicon vias in each sensor, and symmetry axes of the through silicon vias in at least one through silicon via group coincide.

In one possible implementation, the base body further includes a substrate, a dielectric layer, and a first insulating layer;

the dielectric layer covers at least part of the area of the first surface of the substrate, and each silicon through hole penetrates through the substrate and the dielectric layer;

the first insulating layer covers the second surface of the substrate and at least exposes a through hole area corresponding to each through silicon hole;

wherein the test electrode is located above the dielectric layer.

In one possible implementation, the sensor body further includes: the electrode and the second insulating layer are heated,

the heating electrode is positioned above the dielectric layer and connected with each corresponding silicon through hole;

the second insulating layer is positioned above the dielectric layer and covers the surface of the heating electrode except the first connecting region, and is provided with at least two electrode through holes, and each electrode through hole exposes a silicon through hole connected with the test electrode;

The test electrode is located above the second insulating layer, the target area is overlapped with the heating electrode, and the test electrode is connected to each corresponding through silicon via through the electrode via.

In one possible implementation, symmetry axes of the through-silicon vias in each through-silicon via group are coincident, and straight lines where symmetry axes of the through-silicon vias in different through-silicon via groups are located are different.

In one possible implementation, there is at least one misaligned group of through-silicon vias in a plurality of the groups of through-silicon vias, symmetry axes of at least two through-silicon vias in the plurality of the misaligned group of through-silicon vias are misaligned,

and the metal wiring is used for connecting the heating electrode of the sensor below the interconnection layer and the through silicon hole of the sensor above the interconnection layer.

In one possible implementation, the plurality of sensors includes a gas sensor, a temperature sensor, and an acceleration sensor, wherein the gas sensor is located above the temperature sensor and the acceleration sensor is located below the temperature sensor.

In one possible implementation, the apparatus further includes: the sensor at the lowest layer of the plurality of sensors and the alarm module are fixed on the substrate and are electrically connected through the substrate,

the alarm module is used for sending out alarm prompts under the condition that the alarm conditions are met according to the detection results of the sensors.

In one possible implementation, each through silicon via has a diameter of 20 μm to 50 μm and an aspect ratio of 5:1 to 10:1.

In one possible implementation, the shape of the heating electrode comprises a malleable shape including any of a serpentine shape, an S-shape; and/or

The test electrode comprises an interdigital electrode, the target area is a periodic pattern area of the interdigital electrode, and the ductile-shaped area of the heating electrode and the target area are matched in size and overlapped in position.

According to another aspect of the present disclosure, there is provided a method for manufacturing a through silicon via-based MEMS sensor integrated device, characterized by comprising: a sensor manufacturing step and a sensor stacking step,

The sensor manufacturing steps include: preparing a dielectric layer on a first surface of a substrate; manufacturing a plurality of through silicon vias penetrating through the substrate and the dielectric layer; preparing a first insulating layer on the second surface of the substrate, and etching the first insulating layer to at least expose a through hole area corresponding to each silicon through hole to obtain a matrix of the sensor; manufacturing a test electrode above the dielectric layer; manufacturing a sensitive material layer above a target area of the test electrode to obtain a sensor main body, and finishing the preparation of the sensor;

the sensor stacking step includes: preparing an interconnect layer over a lowermost sensor based on a stacking order of a plurality of sensors in the device; etching the interconnection layer to form a sensitive layer hole and a plurality of line through holes so as to expose the sensitive material layer through the sensitive layer hole and expose the test electrode through each line through hole; filling metal in the wire through hole to form an interconnection wire; fixing an upper sensor adjacent to the lowermost sensor above the lowermost sensor to the interconnect layer; and taking the upper layer sensor as the lowest layer sensor to continuously fix the next sensor until all the sensors are stacked.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

The MEMS sensor integrated device based on the through silicon via and the manufacturing method thereof provided by the embodiment of the disclosure have the advantages of higher integration density, smaller packaging size, lower power consumption and lower cost, and wide application range.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features and aspects of the present disclosure and together with the description, serve to explain the principles of the disclosure.

Fig. 1 and 2 are schematic structural diagrams of a MEMS sensor integrated device based on through silicon vias according to an embodiment of the present disclosure.

Fig. 3A and 3B are schematic structural diagrams of a sensor in a MEMS sensor integrated device based on through silicon vias according to an embodiment of the present disclosure.

Fig. 4 illustrates a schematic structure of a heating electrode according to an embodiment of the present disclosure.

Fig. 5 shows a schematic structural view of a test electrode according to an embodiment of the present disclosure.

Fig. 6 shows a schematic structural diagram of a sensitive material layer according to an embodiment of the present disclosure.

FIG. 7 illustrates a schematic diagram of the relative positions of a heater electrode, a test electrode, and a layer of sensitive material according to an embodiment of the present disclosure.

Fig. 8 shows a schematic structural diagram of a through silicon via based MEMS sensor integrated device according to an embodiment of the present disclosure.

Fig. 9 shows a schematic structural diagram of a through silicon via based MEMS sensor integrated device according to an embodiment of the present disclosure.

Fig. 10 shows a schematic structural diagram of a cap layer in a through silicon via based MEMS sensor integrated device according to an embodiment of the present disclosure.

Fig. 11 shows a schematic structural diagram of a through silicon via based MEMS sensor integrated device according to an embodiment of the present disclosure.

Fig. 12 shows a flowchart of a method of manufacturing a through silicon via based MEMS sensor integrated device according to an embodiment of the present disclosure.

Fig. 13 illustrates a schematic diagram of a process of fabricating a sensor in a method of fabricating a through silicon via based MEMS sensor integrated device according to an embodiment of the present disclosure.

Fig. 14 shows a schematic process diagram of sensor stacking in a method of manufacturing a through silicon via based MEMS sensor integrated device according to an embodiment of the present disclosure.

Fig. 15 is a schematic view showing a process of manufacturing a through silicon via in a method of manufacturing a through silicon via-based MEMS sensor integrated device according to an embodiment of the present disclosure.

Detailed Description

Various exemplary embodiments, features and aspects of the disclosure will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

In addition, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.

In order to solve the technical problems, the present disclosure provides a MEMS sensor integrated device based on through silicon vias and a manufacturing method thereof, and the manufactured device has higher integration density, smaller package size, lower power consumption and lower cost, and wide application range.

Fig. 1 and 2 are schematic structural diagrams of a MEMS sensor integrated device based on through silicon vias according to an embodiment of the present disclosure. As shown in fig. 1 and 2, the device comprises a plurality of vertically stacked sensors each comprising a sensor body and a base 1 for carrying the sensor body, and an interconnect layer 51 between two of the sensors adjacent to each other.

As shown in fig. 1 and 2, the substrate 1 is provided with a plurality of through silicon vias 15. The sensor body comprises a test electrode 20 and a layer of sensitive material 21. The test electrode 20 is located above the base 1 and connected to the corresponding each through silicon via 15. The sensitive material layer 21 covers the target area of the test electrode 20.

As shown in fig. 1 and 2, each of the interconnection layers 51 includes a sensitive layer hole 511 and a plurality of line through holes 512, wherein an interconnection line 513 is disposed in each of the line through holes 512, and two ends of each interconnection line 513 are respectively connected to a test electrode 20 of a sensor below the interconnection layer 51 and a through silicon hole 15 of a sensor above the interconnection layer 51, and each sensitive layer hole 511 is used for accommodating a sensitive material layer 21 of the sensor below the interconnection layer 51. The sensitive layer hole 511 may be a through hole as shown in fig. 1 and fig. 2. Alternatively, if the operation of the sensitive material layer 21 is not affected by the coverage of the upper film layer, the interconnect layer 51 may not have the sensitive layer hole 511, and at this time, the interconnect layer 51 directly covers the surface of the sensitive material layer 21.

In one possible implementation, as shown in fig. 1 and fig. 2, the plurality of through-silicon vias 15 in each of the sensors respectively belong to different through-silicon via groups, and each through-silicon via group includes through-silicon vias 15 connected in series by the interconnection line among the plurality of through-silicon vias 15 in each of the sensors, and symmetry axes of the through-silicon vias 15 in at least one of the through-silicon via groups coincide. For example, as shown in fig. 1 and 2, the plurality of through-silicon vias 15 in the dashed box 80 belong to the same through-silicon via group, and symmetry axes of the through-silicon vias 15 overlap.

In one possible implementation, as shown in fig. 2, there may be at least one misaligned through-silicon via group among the plurality of through-silicon vias 15 of the misaligned through-silicon via group, the symmetry axes of at least two through-silicon vias 15 being misaligned. Metal wiring 514 is also provided in interconnect layer 51, which metal wiring 514 is used to connect the test electrode of the sensor below the interconnect layer with the through silicon via of the sensor above the interconnect layer, and/or which metal wiring 514 is used to connect the heater electrode of the sensor below the interconnect layer with the through silicon via of the sensor above the interconnect layer. Each of the plurality of through-silicon via groups may be a non-overlapping through-silicon via group.

In this embodiment, the substrate 11 may be a silicon substrate. The material of the sensitive material layer can be oxide, metal, high polymer and the like, and different materials can be switched according to actual needs. The sensitive material layer can be formed by film forming processes such as self-assembly, whole wafer coating, sputtering and the like, and patterning is realized by photoetching, so that the sensitive material layer is better compatible with wafer-level manufacturing technology. When the specificity of the sensitive material layer changes in the sensing process, the electric signals at the two ends of the test electrode can change, and corresponding detection can be realized by reading the signal change.

In one possible implementation, as shown in fig. 3A and 3B, the base 1 further includes a substrate 11, a dielectric layer 12, and a first insulating layer 16. The dielectric layer 12 covers at least a part of the area of the first surface of the substrate 11, and each through silicon via 15 penetrates through the substrate 11 and the dielectric layer 12. The first insulating layer 16 covers the second face of the substrate 11 and exposes at least via areas 17 corresponding to each of the through silicon vias 15. Wherein the test electrode 20 is located above the dielectric layer 12.

In this implementation, the dielectric layer is used to isolate the substrate from the test electrodes in the sensor body and the heating electrodes described below. The dielectric layer may be an ONO dielectric layer, and the ONO dielectric layer may be silicon oxide (SiO ₂ ) Silicon nitride (SiN) _x ) OxygenThe silicon layer can be prepared by adopting a plasma enhanced chemical vapor deposition method (Plasma Enhanced Chemical VaporDeposition, PECVD) and other processes. Since silicon nitride and silicon oxide have opposite thermal expansion characteristics, additional stress due to thermal expansion can be reduced in a high temperature process, so that the dielectric layer can be provided as an ONO dielectric layer. For example, as shown in fig. 3B, the dielectric layer 12 may include a silicon oxide layer 121, a silicon nitride layer 122, and a silicon oxide layer 123.

In this embodiment, the material of the first insulating layer may be an insulating material such as silicon oxide, and the thickness of the first insulating layer may be 300nm to 1000nm. The material and the dimensions of the dielectric layer and the first insulating layer can be set by those skilled in the art according to actual needs, and the disclosure is not limited thereto.

In a possible implementation, as shown in fig. 3B, in the case where the sensitive material layer 21 in the manufactured sensor needs to be heated to a certain temperature to operate normally, the sensor body further includes: heating electrode 18 and second insulating layer 19. The heating electrode 18 is located above the dielectric layer 12 and connected to each corresponding through silicon via 15. The second insulating layer 19 is located above the dielectric layer 12 and covers the surface of the heating electrode 18 except the first connection region 181 (shown in fig. 4). The second insulating layer 19 is provided with at least two electrode through holes 191, and each electrode through hole 191 exposes the through silicon via 15 to which the test electrode 20 is connected. Wherein the test electrode 20 is located above the second insulating layer 19 and the target region overlaps the heating electrode 18, and is connected to the corresponding each of the through-silicon vias 15 through the electrode via 191.

In this implementation, the heating electrode 18 is used to generate heat when energized, and these heats can heat the sensitive material layer 21 in the sensor body, and adjust the temperature of the sensitive material layer 21, so that the sensitive material layer 21 is at an operating temperature during the operation of the sensor, and the sensor body is guaranteed to perform corresponding detection. If the sensor is a gas sensor (i.e. a sensor for detecting the kind and/or concentration of a gas in the external environment), the sensor body may further include a heating electrode 18 and a second insulating layer 19, and the material of the sensitive material layer 21 may be a gas-sensitive material, and the gas-sensitive material may be specifically combined with gas molecules after being heated. The second insulating layer 19 serves to insulate the test electrode 20 and the heating electrode 18 so that the test electrode 20 and the heating electrode 18 are not communicated with each other. The material of the second insulating layer 19 may be an insulating material such as silicon oxide, silicon nitride, or the like, which is not limited in the present disclosure.

Fig. 4 illustrates a schematic structure of a heating electrode according to an embodiment of the present disclosure. Fig. 5 shows a schematic structural view of a test electrode according to an embodiment of the present disclosure. Fig. 6 shows a schematic structural diagram of a sensitive material layer according to an embodiment of the present disclosure. FIG. 7 illustrates a schematic diagram of the relative positions of a heater electrode, a test electrode, and a layer of sensitive material according to an embodiment of the present disclosure. Wherein the second insulating layer 19 is not shown in fig. 7 for more clearly illustrating the relative positional relationship of the heating electrode 18, the test electrode 20 and the sensitive material layer 21 in space.

In one possible implementation, the shape of the heater electrode 18 may comprise a malleable shape, which may comprise a serpentine, S-shaped, etc. malleable shape as shown in fig. 4, 7. In this way, the length of the heating electrode can be increased. The heating electrode 18 may include an ductile-shape region M1, a first connection region 181 for connecting the through-silicon via 15, and a first wire region 182 for realizing connection between the ductile-shape region M1 and the first connection region 181.

In one possible implementation, as shown in fig. 5, the test electrodes 20 may be interdigitated electrodes. The fingers of the interdigital electrodes which are not communicated with each other can be communicated through the sensitive material layer 21 covered on the fingers. The test electrode 20 may include a periodic pattern region M2, a second connection region 201 for connecting the through silicon via 15, and a second wire region 202 for realizing connection between the periodic pattern region M2 and the second connection region 201. The target area may be a periodic pattern area M2.

Wherein the width w1 of the ductile shaped region M1 and the first wire region 182 in the heating electrode 18 is equal to the width w2 of the interdigital electrode (i.e., the width of the periodic pattern region M2 and the second connection region 201), i.e., w1=w2. The distance s1 between the strip-shaped metals in the ductile-shape region M1 is the same as the distance s2 between the fingers in the interdigitated electrodes (i.e., the distance between the strip-shaped metals in the periodic pattern region M2), i.e., s1=s2. And w1 and s1 may be equal. The malleable shape region M1 is the same size as the periodic pattern region M2. The number of cycles of the extendable shape area M1 and the periodic pattern area M2 may be the same, wherein the number of cycles of the extendable shape area M1 is 4 as shown in fig. 4 and 7, and the number of cycles of the periodic pattern area M2 is 4 as shown in fig. 5 and 7. The thickness of the heating electrode 18 and the thickness of the test electrode 20 may be the same, and the thickness may be 80nm to 150nm, for example, the thicknesses of the heating electrode 18 and the test electrode 20 are set to 110nm.

In this implementation, the materials of the heating electrode 18 and the test electrode 20 may be titanium (Ti), platinum (Pt), or the like, which is not limited by the present disclosure.

In one possible implementation, as shown in fig. 6 and 7, the sensitive material layer 21 may be self-assembled clusters of spherical sensitive material 211. The size of the sensitive material layer 21 may be slightly smaller than or equal to the size of the periodic pattern area M2, so that the sensitive material layer 21 may completely cover the periodic pattern area M2, and ensure the circuit conduction of the sensor.

In the present embodiment, the dimensions of the sensitive material layer 21, the test electrode 20, and the heating electrode 18 may be set according to the size setting requirements of the sensor. Assuming that the dimensions of the sensitive material layer 21 are determined to be 100 μm×100 μm to 300 μm×300 μm according to the size setting of the sensor, s1, s2, w1, w2 may be 5 μm to 20 μm, and the lengths of the test electrode 20, the heating electrode 18 may be 35 μm to 380 μm. It will be appreciated by those skilled in the art that the dimensions, materials, etc. of the various parts of the sensor body may be set as desired, and this disclosure is not limited thereto.

Fig. 8 shows a schematic structural diagram of a through silicon via based MEMS sensor integrated device according to an embodiment of the present disclosure. In one possible implementation, as shown in fig. 8, the apparatus may include a substrate 71 and an alarm module 61. The lowest sensor among the plurality of sensors and the alarm module 61 are fixed to the substrate 71 and electrically connected to each other through the substrate 71. The alarm module 61 is configured to send an alarm prompt when it is determined that the alarm condition is met according to the detection result of each sensor. Wherein the lowermost sensor and the alarm module 61 may be electrically connected by a wire layer 711 inside the substrate 71.

In this implementation, the alarm module may send out an alarm prompt through one or more of sound, vibration, light, etc., which is not limited by the present disclosure.

In this embodiment, the number of sensors in the device may be set according to actual needs. The order of vertical stacking may also be set according to the function of the sensors in the device, which is not limiting to the present disclosure. For example, assuming that three sensors are included in a device, a gas sensor, a temperature sensor, and an acceleration sensor, respectively, the gas sensor is located above the temperature sensor and the acceleration sensor is located below the temperature sensor in the device. Thus, the gas sensor is positioned on the top layer, so that the gas sensor can accurately detect specific gases in the environment. The temperature sensor of the intermediate layer can detect the temperature in the environment. And the acceleration sensor is arranged on the bottom layer, so that the whole device can be ensured to detect the vibration of the installation position of the device. The device comprising the gas sensor, the temperature sensor and the acceleration sensor can realize a highly integrated and miniaturized multifunctional industrial production environment monitoring and alarming system, detect toxic gas leakage, fire and abnormal vibration in a factory, and send out an alarming prompt through the alarming module when the abnormality is found. The alarm module can also report to the upper side under the condition that the alarm condition is met according to the detection result of each sensor, such as a control center, a monitoring center and the like of a factory, so that related personnel can respond to the processing in time.

Fig. 9 shows a schematic structural diagram of a through silicon via based MEMS sensor integrated device according to an embodiment of the present disclosure. In one possible implementation, as shown in fig. 9, to ensure the safety of the top sensor of the device, the device may include a capping layer to improve the reliability and stability of the device. When the top sensor is an acceleration sensor, a pressure sensor, or the like, which does not require contact with the external environment, the cap layer may include a cap substrate 31 and a bonding ring 32 as shown in fig. 9. The first side of the cap substrate 31 is provided with a receiving groove 312, and at least part of the top layer sensor is located in the receiving groove 312. The bonding ring 32 is disposed on the first surface of the cap substrate 31 and surrounds the accommodating groove 312 in a closed manner, so as to fixedly connect the top sensor and the cap layer together.

Fig. 10 shows a schematic structural diagram of a cap layer in a through silicon via based MEMS sensor integrated device according to an embodiment of the present disclosure. In one possible implementation, as shown in fig. 10, if the top layer sensor in the device is a gas sensor, the cap layer may further include a gas permeable membrane layer 33 and a dust screen layer 34. The second face of the cap substrate 31 may be provided with a vent hole 311 connected to the receiving groove 312 at a position corresponding to a target area of the test electrode in the top-layer sensor. The air-permeable film layer 33 is located above the second surface of the cap substrate 31 and covers at least the vent holes 311. And a dust-proof mesh layer 34 which is positioned on the second surface of the cap substrate 31 and covers at least a region of the ventilation film layer 33 corresponding to the ventilation holes 311, wherein a plurality of through holes 341 are provided in a portion of the dust-proof mesh layer 34 corresponding to the ventilation holes 311.

In this embodiment, the breathable film layer 33 may cover the entire area of the second surface of the cap substrate 31 (as shown in fig. 11), or may cover only the area of the second surface of the cap substrate 31 corresponding to the ventilation holes 311. The gas permeable membrane layer 33 has a selective passage that allows gas to enter the vent holes 311, blocking contaminants on the order of ten microns from entering the vent holes 311. For example, the material of the breathable film layer 33 may be a polymer. In this way, contamination and damage of the sensitive material layer in the sensor by contaminants can be avoided. The material and thickness of the breathable film layer can be set by those skilled in the art according to actual needs, and the present disclosure is not limited thereto.

In this embodiment, the dust-proof mesh layer 34 may cover the entire region of the air-permeable membrane layer 33 (as shown in fig. 10), or may cover only the region of the air-permeable membrane layer 33 corresponding to the ventilation holes 311. The size of the dust-proof mesh layer 34 and the ventilation film layer 33 may be the same or different, and the present disclosure is not limited thereto. The dust screen layer 34 is used for preventing large particle dirt such as dust from falling into the gas sensor on the top layer through the vent holes 311, so as to avoid pollution and mechanical damage to the sensitive material layer in the gas sensor caused by the large particle dirt. The material of the dust-proof mesh layer 34 may be a material such as metal that can resist corrosion by corrosive gas to improve the reliability of the sensor. For example, the material of the dust-proof mesh layer 34 may be Pt. The thickness of the dust-proof mesh layer 34 may be 100nm to 300nm. The material and thickness of the dust-proof mesh layer can be set according to actual needs by those skilled in the art, and the present disclosure is not limited thereto.

In a possible implementation manner, if the top sensor in the device is a gas sensor, the cap layer may further include only a dust-proof layer (i.e. not including a gas-permeable membrane layer), where the dust-proof layer is located on the second surface of the cap substrate 31 and covers at least the area corresponding to the vent hole 311, and the area of the dust-proof layer that covers at least the vent hole 311 is provided with a plurality of through holes 341.

In this embodiment, the thickness of the cap layer may be 200 micrometers to 400 micrometers, and the substrate 11 and the cap substrate 31 may be made of materials such as silicon, so that the two materials have high compatibility with the device layer manufacturing process, and the matching of the contact strength between the substrate and the bonding ring is ensured. The material of the cap layer may also be glass or the like, which is not limited by the present disclosure.

In this embodiment, the base body in the cap layer and the top layer sensor may be the same size, similar thickness, or the same structure. Therefore, the substrate and the cap layer in the top layer sensor can be ensured to have equivalent mechanical properties, and problems caused by mismatch of expansion coefficients, compressive strength and the like in bonding and subsequent operation can be avoided. The material of the bonding ring 32 may be a material that bonds easily to the substrate in the top layer sensor, for example, the material of the bonding ring 32 may be a metal such as gold (Au). In order to ensure the reliability of the fixed connection between the cap layer and the substrate in the top sensor, the width w3 and the thickness h of the bonding ring may be set, for example, w3 may be 100 μm to 150 μm, and h may be 150nm. The bonding ring 32 may surround the receiving groove and be located at an edge of the first face of the cap substrate 31.

In this embodiment, the bonding ring 32 may be secured to the top sensor substrate by bonding to fixedly connect the cap layer to the top sensor substrate. The structure of the bond connection with the bond ring 32 is different due to the difference in the structure of the base body and the sensor body of the top sensor, and is schematically illustrated by the bonding means one, two, three, four, five.

Bonding mode one:

if the top sensor body further includes a second insulating layer and a heating electrode, and the dielectric layer 12 covers the area of the first surface of the substrate 11 corresponding to the accommodating groove 312, and the second insulating layer 19 also covers at most the exposed dielectric layer 12, the bonding ring 32 is fixedly connected to the first surface of the substrate 11 by bonding, so that the base body and the cap layer are fixedly connected together, and the sensor body and the dielectric layer 12 are located in the accommodating groove 312.

Bonding mode II:

if the top sensor body further includes a second insulating layer and a heating electrode, and the dielectric layer 12 covers the entire area of the first surface of the substrate 11, and the second insulating layer 19 also covers at most the exposed area of the dielectric layer 12 corresponding to the accommodating groove 312, the bonding ring 32 is fixedly connected to the dielectric layer 12 by a bonding manner, so that the substrate and the cap layer are fixedly connected together, and the sensor body is located in the accommodating groove 312.

And a bonding mode III:

if the top sensor body further includes a second insulating layer and a heating electrode, and the dielectric layer 12 covers the entire area of the first surface of the substrate 11 and the second insulating layer also covers the entire area of the exposed dielectric layer 12, the bonding ring 32 is fixedly connected to the second insulating layer 19 by bonding, so that the base body and the cap layer are fixedly connected together, and at least the sensitive material layer 21 is located in the accommodating groove 312.

And a bonding mode is four:

if the top sensor body includes only the test electrode and the sensitive material layer, and the dielectric layer 12 covers the area of the first surface of the substrate 11 corresponding to the accommodating groove 312, the bonding ring 32 is fixedly connected to the first surface of the substrate 11 by bonding, so that the base body and the cap layer are fixedly connected together, and the sensor body and the dielectric layer 12 are located in the accommodating groove 312.

And a fifth bonding mode:

if the top sensor body only includes the test electrode and the sensitive material layer, and the dielectric layer 12 covers the entire area of the first surface of the substrate 11, the bonding ring 32 is fixedly connected to the dielectric layer 12 by bonding, so that the base body and the cap layer are fixedly connected together, and at least the sensitive material layer 21 in the sensor body is located in the accommodating groove 312.

In one possible implementation, the sensor may further comprise a processing module for controlling the energization of the heating electrodes in each sensor in the device such that, during operation of the device, the heating electrodes of the sensor provided with the heating electrodes are energized to heat the layer of sensitive material to an operating temperature. In the working process of the device, the processing module is also used for controlling the electrifying of the test electrodes in the sensors, the processing module itself or the corresponding detection module is controlled to monitor the current flowing through the test electrodes in the sensors, and the relevant data for the object detected by the sensors is determined according to the monitoring result and is used as the detection result. Wherein the detection object may be gas, temperature, humidity, acceleration, speed, etc., which is not limited by the present disclosure.

In this embodiment, the position, size and shape of the receiving groove 312 may be set according to the position, size and shape of the sensor body, so that at least the sensitive material layer 21 of the top sensor is located in the receiving groove 312. The depth of the receiving groove 312 may be 100 micrometers to 300 micrometers.

For example, if the dimensions of the sensitive material layer 21 are 100 μm×100 μm to 300 μm×300 μm, the accommodating groove 312 may have a rectangular parallelepiped structure with dimensions of 500 μm×500 μm×100 μm (100 μm is depth).

Fig. 11 shows a schematic structural diagram of a through silicon via based MEMS sensor integrated device according to an embodiment of the present disclosure. In one possible implementation, as shown in fig. 11, the device may also include a device electrode 41. Device electrodes 41 are disposed in the corresponding via regions 17 and electrically connected to the corresponding through silicon vias 15. By connecting the device electrode 41 under the through-silicon via 15 in this way, planar metal wiring can be reduced, and the test region and the electric region can be effectively isolated, thereby improving the device reliability and realizing the device miniaturization.

The via area 17 of the underlying sensor in the device may be larger than the cross-sectional area of the corresponding through-silicon via 15, with a metal electrode deposition layer 40 disposed in the via area 17. The metal electrode deposition layer 40 is located at each of the via areas 17 and covers each of the via areas 17. The material of the metal electrode deposition layer 40 may be titanium (Ti), platinum (Pt), gold (Au), or the like. The thickness of the metal electrode deposition layer 40 may be 550nm. The metal electrode deposition layer 40 can facilitate the subsequent preparation of the device electrode 41 by a ball implantation mode, and ensure the smooth proceeding of ball implantation. Those skilled in the art may set the materials and dimensions of the metal electrode deposition layer and the device electrode according to actual needs, and the present disclosure is not limited thereto. The device electrode 41 may be a metal ball manufactured by a ball-implanting method such as laser ball-implanting, and the material of the metal ball may be lead-tin alloy (PbSn) or the like.

In some embodiments, as shown in fig. 1, the symmetry axes of the through-silicon vias 15 in each of the through-silicon via groups coincide, and the symmetry axes of the through-silicon vias 15 in different through-silicon via groups are not in the same straight line. Therefore, the series connection of a plurality of sensors can be realized by means of the through silicon vias, the integration level of the device is improved, and the thickness of the device is reduced.

In the present embodiment, each through silicon via 15 is disposed below the first connection region 181 of the heating electrode 18 or the second connection region 201 of the test electrode 20, and the filler metal in each through silicon via 15 contacts the heating electrode 18 or the test electrode 20 on the first surface of the substrate 11. The metal-filled lower sensor test electrodes or heater electrodes in the through silicon vias 15 are connected. The through silicon vias 15 in the lowermost sensor may be connected to an external such that the detected signal is input to the processing circuit. In this way, through-silicon vias 15 serve as interconnect lines to achieve three-dimensional packaging of the wafer, spatially isolating the interconnect lines from the circuit region and the test region, thereby achieving longitudinal integration of the MEMS sensor in the device, and enabling a reduction in thickness of the device. The silicon through hole interconnection technology can realize the up-and-down electrical conduction of a plurality of sensors in the device, is favorable for realizing the multi-layer stacking of the sensors and the ICs, and has the characteristics of high performance, high density, low power consumption and the like.

In one possible implementation, through-silicon vias 15 may be large-aperture, high aspect ratio through-silicon vias, the diameter of through-silicon vias 15 may be 20 μm to 50 μm, and the aspect ratio may be 5:1 to 10:1. Thus, the preparation of interconnection lines aiming at the high-current high-power MEMS sensor and the transverse and longitudinal integrated structures thereof can be realized.

Fig. 12 shows a flowchart of a method of manufacturing a through silicon via based MEMS sensor integrated device according to an embodiment of the present disclosure. Fig. 13 illustrates a schematic diagram of a process of fabricating a sensor in a method of fabricating a through silicon via based MEMS sensor integrated device according to an embodiment of the present disclosure. Fig. 14 shows a schematic process diagram of sensor stacking in a method of manufacturing a through silicon via based MEMS sensor integrated device according to an embodiment of the present disclosure. Fig. 15 is a schematic view showing a process of manufacturing a through silicon via in a method of manufacturing a through silicon via-based MEMS sensor integrated device according to an embodiment of the present disclosure.

As shown in fig. 12 to 15, the method includes: a sensor manufacturing step and a sensor stacking step. In fig. 13, the sensor shown in fig. 3B is schematically used as an example, fig. 14, the 3 sensors manufactured based on fig. 13 are schematically used as examples, and fig. 15 schematically shows only a manufacturing process of one through silicon via of the plurality of through silicon vias for simplicity, which illustrates a flow of a manufacturing method of the device. The sensor manufacturing step is performed before the sensor stacking step.

As shown in fig. 12, the sensor manufacturing steps may include: a base body manufacturing step and a sensor body manufacturing step. The substrate manufacturing step includes steps S501 to S503. The sensor body manufacturing step includes steps S504 to S505.

In step S501, a dielectric layer 12 is prepared on the first surface of the substrate 11, where the dielectric layer 12 may be a silicon oxide layer 121, a silicon nitride layer 122, and a silicon oxide layer 123. The dielectric layer 12 may be prepared using a PECVD process.

In step S502, the substrate 11 and the dielectric layer 12 are etched, and the substrate 11 is thinned to form a plurality of through silicon vias 15.

As shown in fig. 15, step S502 may include:

etching the substrate 11 and the dielectric layer 12 by using a BOSCH process to form a plurality of blind holes 13 with high aspect ratio required by preparing the sensor; the silicon oxide insulating layer 131 is prepared on the surface of the blind hole 13 by a thermal oxidation method, a PECVD method, a low-pressure chemical vapor deposition method (Low Pressure Chemical VaporDeposition, LPCVD) method and the like, wherein the insulating layer is manufactured by the thermal oxidation method, so that the insulating layer can be prevented from being damaged by subsequent high temperature. And then preparing a barrier layer 132 of TiN, ti/W and other materials on the surface of the insulating layer 131 by adopting an atomic layer deposition (Atomiclayer deposition, ALD) process or a physical vapor deposition (Physical Vapor Deposition, PVD) process and the like, wherein the thickness of the barrier layer 132 can be 50-150 nm. The seed layer 133 of Cu or other material is prepared on the surface of the barrier layer by physical vapor deposition, atomic layer deposition, electroless plating, etc., and the thickness of the seed layer 133 may be 500nm to 1 μm. The blind via 13 may be filled with a conductive metal such as copper using a plating process or the like to form a metal structure 14 as shown in fig. 13, and then may be annealed to partially relieve the stress from the filled metal. Since the metal structure 14 is also electroplated on the dielectric layer 12, the metal structure 14 on the dielectric layer 12 may be polished by a chemical mechanical polishing (Chemical Mechanical Polishing, CMP) process or the like. The second side of the substrate 11 is thinned after polishing until the blind holes 13 are exposed, resulting in through silicon vias 15. Wherein the insulating layer 131, the barrier layer 132 and the seed layer 133 in the through silicon via are not shown in fig. 13 for simplicity. The insulating layer serves to electrically insulate the metal pillars in the through-silicon via 15 from the substrate 11. The barrier layer serves to prevent electrode metal in the metal pillars in the through-silicon via 15 from diffusing into the insulating layer and substrate 11.

The dielectric layer 12 may be etched by using an etching technique such as inductively coupled plasma (Inductively Coupled Plasma, ICP), and the substrate 11 may be etched by using a Bosch process, to finally form a plurality of blind holes 13.

In step S503, a first insulating layer 16 is prepared on the second surface of the substrate 11, and the first insulating layer 16 is etched to expose at least the via region 17 corresponding to each through-silicon via 15, thereby completing the manufacture of the substrate.

Wherein the first insulating layer 16 can be prepared by PECVD, metal diffusion in the through silicon via at high temperature can be avoided. The via areas may then be patterned using a photolithographic process, and then the first insulating layer 16 is etched using a dry etching process such as an ICP process until the via areas 17 are exposed. Then, a metal electrode deposition layer 40 can be deposited in the through hole region 14 by means of magnetron sputtering or metal deposition such as evaporation coating, and the metal electrode deposition layer is used as a contact region for subsequent ball implantation (the manufacturing step of the contact region is an optional step). Through polishing in the process of preparing the through silicon vias and thinning in the step S503, wafer warpage caused by film stress can be eliminated, and smooth implementation of subsequent processes is ensured.

The manufacturing steps of the sensor main body are as follows: including steps S504 to S505.

In step S504, the test electrode 20 is prepared on the surface of the dielectric layer 12.

The surface of the dielectric layer 12 may be coated with photoresist, after patterning the photoresist based on the structure and the size of the test electrode 20, the area of the surface of the dielectric layer 12 where the test electrode 20 needs to be prepared is exposed, and then the test electrode 20 is formed by performing metal deposition in a metal deposition manner such as magnetron sputtering or evaporation coating, and then the redundant photoresist on the surface of the dielectric layer 12 is removed.

In step S505, the sensitive material layer 21 is manufactured over the target area of the test electrode 20, completing the manufacture of the sensor body.

The patterning is performed above the target area of the test electrode 20 by adopting a photolithography method, an area of the surface of the test electrode 20, where the sensitive material layer 21 needs to be prepared, is exposed, then the sensitive material layer 21 is obtained after the sensitive material is coated and the photoresist is stripped by adopting a coating method, and the sensor main body is obtained.

In one possible implementation, if the sensor body further includes a heater electrode and a second insulating layer (as shown in fig. 3B), the steps of manufacturing the sensor body may include: a heater electrode 18 is fabricated on the surface of the dielectric layer 12. Manufacturing a second insulating layer 19 on the heating electrode 18 and the surface of the exposed dielectric layer 12; etching the second insulating layer 19 to form an electrode via 191 so that a through-silicon via of the plurality of through-silicon vias 15 for connection with the test electrode 20 is exposed through the electrode via 191; manufacturing a test electrode 20 with a target area overlapped with the heating electrode 18 on the second insulating layer 19, and connecting the test electrode 20 with a corresponding through silicon via 15 through an electrode via 191; a layer 21 of sensitive material is manufactured over the target area, completing the manufacture of the sensor body.

In this implementation, photoresist may be coated on the surface of the dielectric layer 12, after patterning the photoresist based on the structure and size of the heating electrode 18, the area of the surface of the dielectric layer 12 where the heating electrode 18 needs to be manufactured is exposed, and metal deposition is performed by a metal deposition manner such as magnetron sputtering or evaporation coating to form the heating electrode, and then the redundant photoresist on the surface of the dielectric layer 12 is removed. The second insulating layer may be deposited using a PECVD process. The surface of the second insulating layer 19 may be coated with photoresist, and after patterning the photoresist based on the position and size of the through-silicon vias 15 connected to the test electrode 20, the second insulating layer 19 is etched by a dry etching process, exposing the through-silicon vias 15 for connection to the test electrode 20, and then removing the excess photoresist on the surface of the second insulating layer 19. The surface of the second insulating layer 19 may be coated with a photoresist, after patterning the photoresist based on the structure and size of the test electrode 20, the area of the surface of the second insulating layer 19 where the test electrode 20 needs to be prepared is exposed, and then the test electrode 20 is formed by performing metal deposition in a metal deposition manner such as magnetron sputtering or evaporation coating, and then removing the redundant photoresist on the surface of the second insulating layer 19. Patterning the upper part of the target area of the test electrode 20 by adopting a photoetching mode, exposing the second insulating layer 19 and the area of the surface of the test electrode 20, which is required to be provided with the sensitive material layer 21, then coating the sensitive material by adopting a coating mode, and stripping photoresist to obtain the sensitive material layer 21, thereby obtaining the sensor main body.

In the case where the device further includes a cap layer, the method of manufacturing the device further includes a cap layer manufacturing step, the cap layer manufacturing step (i.e., manufacturing the cap layer as shown in fig. 9) may include: a bonding ring 32 is prepared on the first side of the cap substrate 31. The first surface of the cap substrate 31 is etched to form a receiving groove 312.

The bonding ring region may be patterned by photolithography, then deposited by metal deposition such as magnetron sputtering or evaporation plating, and then stripped of the excess glue layer to obtain the bonding ring 32. The first surface of the cap substrate 31 may be patterned in a region corresponding to the receiving groove by photolithography, and the cap substrate 31 in the patterned region is etched using a BOSCH process to form the receiving groove 312.

In one possible implementation, if the sensor is a gas sensor, the cap layer manufacturing step (i.e., manufacturing the cap layer shown in fig. 10) may include: the cap substrate 31 is etched to form a vent hole 311 penetrating the cap substrate 31 and corresponding to the target region. Wherein the cap substrate 31 may be etched using a BOSCH process to form the vent holes 311. The first surface of the cap substrate 31 is etched to form a receiving groove 312 connected to the vent hole 311. The first surface of the cap substrate 31 may be patterned by photolithography in a region corresponding to the receiving groove, and the cap substrate 31 in the patterned region is etched by a BOSCH process to form the receiving groove 312. A previously prepared breathable film is attached to the second surface of the cap substrate 31 and covers at least the vent holes 311, thereby forming a breathable film layer 33. A dust-proof layer is prepared above the air-permeable film layer 33, and a dust-proof layer 34 having a plurality of through holes 341 is formed to cover at least a portion of the air-permeable film layer 33. The dust-proof layer may be patterned by photolithography, exposing the area above the air-permeable film layer 33 and above the second surface of the cap substrate where the dust-proof layer needs to be prepared, depositing metal by magnetron sputtering or evaporation plating to form the dust-proof layer, and removing the redundant photoresist to complete the preparation of the dust-proof layer 34.

In one possible implementation, if the sensor is a gas sensor and the cap layer includes a dust screen layer but does not include a gas permeable membrane layer, the cap layer manufacturing step may include: and etching the cap substrate to form vent holes which penetrate through the cap substrate and correspond to the target area. Etching the first surface of the cap substrate to form a containing groove connected with the vent hole. The dust-proof layer can be patterned in a photoetching mode, the area, above the second surface of the cap substrate, of which the dust-proof layer needs to be prepared is exposed, the dust-proof layer is formed by metal deposition in a metal deposition mode such as magnetron sputtering or evaporation coating, and then redundant photoresist is removed, so that the dust-proof layer is prepared, and the dust-proof layer with a plurality of through holes at least covering part of the vent holes is obtained.

In one possible implementation, if the device includes a cap layer, the top layer sensor manufacturing step or the sensor stacking step may also include a fixed attachment step. The step of fixedly connecting includes fixedly connecting the bonding ring 32 to the base body by bonding so that at least the sensitive material layer 21 of the top sensor is located in the receiving groove 312.

Wherein a compressive stress in the reverse direction can be applied to the top layer sensor or to the stacked plurality of sensor devices during bonding to further mitigate warpage.

According to the difference between the matrix and the main structure of the sensor, the step of fixedly connecting can comprise any one of the following implementation modes:

if the sensor body of the top sensor does not include the heating electrode and the second insulating layer, and the dielectric layer 12 covers the area of the first surface of the substrate 11 corresponding to the accommodating groove 312, the bonding ring 32 is fixedly connected to the first surface of the substrate 11 by bonding, so that the base body and the cap layer are fixedly connected together, and the sensor body and the dielectric layer 12 are located in the accommodating groove 312.

If the sensor body of the top sensor does not include the heating electrode and the second insulating layer, and the dielectric layer 12 covers the entire area of the first surface of the substrate 11, the bonding ring 32 is fixedly connected to the dielectric layer 12 by bonding, so that the base body and the cap layer are fixedly connected together, and at least the sensitive material layer 21 in the sensor body is located in the accommodating groove 312.

If the sensor body of the top sensor includes the heating electrode 18 and the second insulating layer 19, and the dielectric layer 12 covers the area of the first surface of the substrate 11 corresponding to the accommodating groove 312, and the second insulating layer 19 also covers at most the exposed dielectric layer 12, the bonding ring 32 is fixedly connected to the first surface of the substrate 11 by bonding, so that the base body and the cap layer are fixedly connected together, and the sensor body and the dielectric layer 12 are located in the accommodating groove 312.

If the sensor body of the top sensor includes the heating electrode 18 and the second insulating layer 19, and the dielectric layer 12 covers the entire area of the first surface of the substrate 11, and the second insulating layer 19 also covers at most the exposed area of the dielectric layer 12 corresponding to the accommodating groove 312, the bonding ring 32 is fixedly connected with the dielectric layer 12 by bonding, so that the substrate and the cap layer are fixedly connected together, and the sensor body is located in the accommodating groove 312.

If the sensor body of the top sensor includes the heating electrode 18 and the second insulating layer 19, and the dielectric layer 12 covers the entire area of the first surface of the substrate 11 and the second insulating layer 19 also covers the entire area of the exposed dielectric layer 12, the bonding ring 32 is fixedly connected to the second insulating layer 19 by bonding, so that the substrate and the cap layer are fixedly connected together, and at least the sensitive material layer 21 is located in the accommodating groove 312.

The sensor stacking step includes: step S506-step S508.

In step S506, the interconnect layer 51 is prepared above the lowest sensor based on the stacking order of the plurality of sensors in the device. The interconnect layer 51 is etched to form a sensitive layer hole 511 and a plurality of line through holes 512 to expose the sensitive material layer 21 through the sensitive layer hole 511 and the test electrode 20 through each of the line through holes 512.

Wherein an interconnect layer 51 may be grown directly over the lowermost sensor using CVD or the like. The interconnect layer 51 may be a dielectric layer (Interposer), and the material of the interconnect layer may be SiGI, si, or the like. The interconnect layer may be lithographically etched or the like to form a sensitive layer hole 511 and a plurality of line vias 512.

In step S507, the interconnect line 513 is formed by filling metal in the line via 512. Metal filling may be performed in the line via 512 by PVD or the like to form the interconnect line 513.

In step S508, an upper sensor adjacent to the lowermost sensor above the lowermost sensor is fixed to the interconnect layer 51. And then the upper layer sensor is used as the lowest layer sensor to continuously fix the next sensor until all the sensors are stacked.

In one possible implementation, if there is at least one misaligned through-silicon via group in the plurality of through-silicon via groups, symmetry axes of at least two through-silicon vias in the plurality of through-silicon vias of the misaligned through-silicon via group are misaligned, the sensor stacking step may further include: the preparation of the metal wiring is performed during the manufacture of the interconnect layer 51 so that the metal wiring can connect the test electrode of the sensor below the interconnect layer and the through silicon via of the sensor above the interconnect layer and/or the metal wiring is used to connect the heater electrode of the sensor below the interconnect layer and the through silicon via of the sensor above the interconnect layer.

In one possible implementation, if the device includes a device electrode, the method may further include an electrode fabrication step: ball implantation is performed in the through hole area of the lowest layer of sensor to form a device electrode 41, and the preparation of the device is completed. Wherein, the ball can be planted by adopting a laser ball planting mode.

It should be noted that, although the above embodiments are described as examples of a MEMS sensor integrated device based on through silicon vias and a method of manufacturing the same, the present disclosure should not be limited thereto, as those skilled in the art will appreciate. In fact, the user can flexibly set each step and each part of the device according to personal preference and/or practical application scene, so long as the technical scheme of the disclosure is met.

The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the technical improvements in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A through silicon via based MEMS sensor integrated device, the device comprising: a plurality of sensors vertically stacked and an interconnection layer between two adjacent sensors, each of the sensors including a sensor body and a base body for carrying the sensor body;

2. The apparatus of claim 1, wherein the base further comprises a substrate, a dielectric layer, and a first insulating layer;

wherein the test electrode is located above the dielectric layer.

3. The apparatus of claim 2, wherein the sensor body further comprises: the electrode and the second insulating layer are heated,

4. The apparatus of claim 1, wherein axes of symmetry of the through-silicon vias in each of the through-silicon via groups coincide and the lines of symmetry of the through-silicon vias in different ones of the through-silicon via groups are not identical.

5. The apparatus of claim 1 or 3, wherein at least one misaligned through-silicon via group is present in a plurality of said through-silicon via groups, the symmetry axes of at least two through-silicon vias in the plurality of through-silicon vias of said misaligned through-silicon via group being misaligned,

6. The device of claim 1, wherein the plurality of sensors includes a gas sensor, a temperature sensor, and an acceleration sensor, the gas sensor being located above the temperature sensor and the acceleration sensor being located below the temperature sensor in the device.

7. The apparatus of claim 1, wherein the apparatus further comprises: the sensor at the lowest layer of the plurality of sensors and the alarm module are fixed on the substrate and are electrically connected through the substrate,

8. The apparatus of claim 1, wherein each of the through-silicon vias has a diameter of 20 μm to 50 μm and an aspect ratio of 5:1 to 10:1.

9. The apparatus of claim 3, wherein the device comprises a plurality of sensors,

the shape of the heating electrode comprises a malleable shape, and the malleable shape comprises any one of a snake shape and an S shape; and/or

10. A method of manufacturing a through-silicon via based MEMS sensor integrated device according to any one of claims 1-9, the method comprising: a sensor manufacturing step and a sensor stacking step,