CN105845615B - Method for manufacturing semiconductor device and electronic device - Google Patents
Method for manufacturing semiconductor device and electronic device Download PDFInfo
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- CN105845615B CN105845615B CN201510019317.4A CN201510019317A CN105845615B CN 105845615 B CN105845615 B CN 105845615B CN 201510019317 A CN201510019317 A CN 201510019317A CN 105845615 B CN105845615 B CN 105845615B
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Abstract
The invention provides a manufacturing method of a semiconductor device and an electronic device, and relates to the technical field of semiconductors. The method comprises the following steps: providing a first substrate; forming a source electrode, a drain electrode and a grid electrode of a transistor on one side of the first surface of the first substrate, and forming a first dielectric cap layer covering the first surface and an interconnection structure positioned on the first dielectric cap layer; providing a carrier substrate, and bonding one side of the first substrate, on which the first dielectric cap layer is formed, with the carrier substrate; and thinning the first substrate from a second surface of the first substrate opposite to the first surface to a second depth. The method comprises the steps of bonding the carrier substrate on the first substrate and thinning the first substrate, so that a common bulk silicon substrate can be used as the first substrate instead of a thin film silicon-on-insulator substrate, and the cost can be reduced. The electronic device of the present invention, including the semiconductor device manufactured by the method, also has the advantages described above.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor device and an electronic device.
Background
In the field of semiconductor technology, it is often necessary to use thin film silicon-on-insulator (TF SOI) substrates to complete the fabrication of certain semiconductor devices, such as radio frequency front end devices and modules.
However, the relatively high cost of thin-film silicon-on-insulator substrates directly limits their use in the semiconductor industry. Accordingly, semiconductor devices (e.g., rf front end devices) that use thin film silicon-on-insulator substrates tend to be relatively costly.
Therefore, it is necessary to provide a method for manufacturing a semiconductor device to complete the manufacturing of the semiconductor device without using a thin-film silicon-on-insulator substrate, thereby reducing the cost of the semiconductor device.
Disclosure of Invention
The invention provides a manufacturing method of a semiconductor device and an electronic device, which can adopt a bulk silicon substrate to replace a silicon substrate on a thin film insulator to finish the manufacturing of the semiconductor device, thereby reducing the cost.
An embodiment of the present invention provides a method of manufacturing a semiconductor device, including:
step S101: providing a first substrate, and forming shallow trench isolation with a first depth in the first substrate from a first surface of the first substrate, wherein the first depth is the distance from the bottom of the shallow trench isolation to the first surface;
step S102: forming a source electrode, a drain electrode and a grid electrode of a transistor on one side of the first surface of the first substrate, and forming a first dielectric cap layer covering the first surface and an interconnection structure positioned on the first dielectric cap layer;
step S103: providing a carrier substrate, and bonding one side of the first substrate, on which the first dielectric cap layer is formed, with the carrier substrate;
step S104: thinning the first substrate from a second surface opposite to the first surface to a second depth, wherein the second depth is the distance from the second surface to the first surface after thinning;
step S105: and forming a second dielectric capping layer on the second surface of the first substrate, and forming at least one silicon through hole which penetrates through the second dielectric capping layer, the shallow trench isolation and the first dielectric capping layer and is connected with the interconnection structure.
In one example, in the step S102, the transistor is a double-gate transistor; further, between the step S104 and the step S105, a step S1015 is further included:
and forming a second grid electrode, a second source electrode and a second drain electrode of the double-grid transistor on one side of the second surface of the first substrate, wherein the second grid electrode and the grid electrode are oppositely arranged, the second source electrode is connected with the source electrode, and the second drain electrode is connected with the drain electrode.
In one example, after the step S105, the method further includes a step S106:
and forming a contact hole positioned above the second grid electrode and a conductive plug positioned in the contact hole in the dielectric capping layer.
In one example, in the step S102, the source and the drain are located below the first surface, and the gate is located above the first surface.
In one example, in the step S102, the second source and the second drain are located below the second surface, and the second gate is located above the second surface.
In one example, in the step S101, the first substrate includes a doped epitaxial layer having a third depth, wherein the third depth is a distance from the doped epitaxial layer to the first surface, and the third depth is greater than or equal to the first depth.
In one example, in step S101, before forming the shallow trench isolation, ion implantation is performed on the first substrate from the first surface to form a first implanted doped layer having a fourth depth in the first substrate, where the fourth depth is a distance from the first implanted doped layer to the first surface, and the fourth depth is greater than or equal to the first depth.
In one example, between the step S101 and the step S102 includes a step S1012:
and carrying out ion implantation on the first substrate from the first surface to form an etching stop layer with a fifth depth below a region where the transistor is to be formed, wherein the fifth depth is the distance from the etching stop layer to the first surface.
Illustratively, the second depth is equal to the first depth.
Illustratively, the second depth is equal to the third depth.
Illustratively, the second depth is equal to the fourth depth.
Illustratively, the second depth is equal to the fifth depth.
In one example, in the step S104, the thinning process includes:
step S1041: carrying out back grinding treatment on the first substrate;
step S1042: performing CMP on the first substrate and stopping the CMP at the bottom of the shallow trench isolation;
step S1043: and carrying out wet etching on the first substrate to the second depth.
In an example, a step of performing wet etching on the first substrate is further included between the step S1041 and the step S1042.
In one example, the first substrate comprises a bulk silicon substrate.
Another embodiment of the present invention provides an electronic apparatus including an electronic component and a semiconductor device connected to the electronic component, wherein a method of manufacturing the semiconductor device includes:
step S101: providing a first substrate, and forming shallow trench isolation with a first depth in the first substrate from a first surface of the first substrate, wherein the first depth is the distance from the bottom of the shallow trench isolation to the first surface;
step S102: forming a source electrode, a drain electrode and a grid electrode of a transistor on one side of the first surface of the first substrate, and forming a first dielectric cap layer covering the first surface and an interconnection structure positioned on the first dielectric cap layer;
step S103: providing a carrier substrate, and bonding one side of the first substrate, on which the first dielectric cap layer is formed, with the carrier substrate;
step S104: thinning the first substrate from a second surface of the first substrate opposite to the first surface to a second depth, wherein the second depth is the distance from the second surface to the first surface after thinning;
step S105: and forming a second dielectric capping layer on the second surface of the first substrate, and forming at least one silicon through hole which penetrates through the second dielectric capping layer, the shallow trench isolation and the first dielectric capping layer and is connected with the interconnection structure.
The manufacturing method of the semiconductor device of the invention can use the common bulk silicon substrate instead of the thin film silicon-on-insulator substrate as the first substrate by bonding the carrier substrate on the first substrate and thinning the first substrate, thereby reducing the cost. The electronic device of the present invention, including the semiconductor device manufactured by the method, also has the advantages described above.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIG. 1A, FIG. 1B, FIG. 1C, FIG. 1D, FIG. 1E, FIG. 1F, FIG. 1G and FIG. 1H are cross-sectional views of structures formed at steps associated with a method of fabricating a semiconductor device in accordance with one embodiment of the present invention;
fig. 2 is a schematic flow chart of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, an implanted region formed by implantation may result in some implantation in the region between the implanted region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
Next, a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described with reference to fig. 1A to 1H and fig. 2. Fig. 1A to 1H are cross-sectional views of structures formed in the relevant steps of a method of manufacturing a semiconductor device according to an embodiment of the present invention; fig. 2 is a schematic flow chart of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Illustratively, the method for manufacturing a semiconductor device according to an embodiment of the present invention includes the steps of:
step A1: providing a first substrate 100, wherein the first substrate 100 comprises a doped epitaxial layer 101 having a third depth D3; performing ion implantation from a first surface (also referred to as an upper surface) 1001 of the first substrate 100 to form a first implant doping layer 102 having a fourth depth D4 within the first substrate 100, wherein the first implant doping layer 102 serves as an etch stop layer; then, Shallow Trench Isolation (STI)103 having a first depth D1 is formed in the first substrate 100 from the first surface 1001 of the first substrate 100, as shown in fig. 1A.
Among them, a surface opposite to a first surface (also referred to as an upper surface) 1001 of the first substrate 100 is referred to as a second surface (also referred to as a lower surface) 1002, as shown in fig. 1A.
In the present embodiment, the term "depth" (e.g., the third depth D3) refers to a distance from the corresponding component (e.g., the doped epitaxial layer 101) to the first surface 1001 of the first substrate 100, unless otherwise specified.
Wherein the doping concentration of the doped epitaxial layer 101 is different from other regions of the first substrate 100.
Illustratively, the shallow trench isolation 103 includes a pad layer 1031 and a body structure layer 1032. Wherein the pad layer 1031 may serve as a stop layer for a subsequent CMP process. Illustratively, the material of pad layer 1031 is silicon oxide, and the material of body structure layer 1032 is silicon nitride.
The first substrate 100 may be a bulk silicon (bulk Si) substrate or any other suitable substrate. Without using a thin-film silicon-on-insulator substrate (TF SOI) or a high-resistance substrate (high-resistance substrate) as in the prior art.
Illustratively, D3 is equal to or greater than D4 and D4 is equal to or greater than D1.
The first substrate 100 may not include the doped epitaxial layer 101 having the third depth D3. In this step, the step of performing ion implantation from the first surface (also referred to as the upper surface) 1001 of the first substrate 100 to form the first impurity implantation layer 102 having the fourth depth D4 in the first substrate 100 may be omitted.
Step A2: forming a well region (not shown in the figure), forming an etch stop layer 104 having a fifth depth D5 below a region where a transistor is to be formed by ion implantation into the first substrate from the first surface 1001; forming a transistor 105 including a source 1051, a drain 1052, and a gate 1053; a dielectric capping layer (dielectric capping film)106 is formed overlying the first surface of the first substrate 100, and an interconnect structure 107 is formed within and at the surface of the dielectric capping layer 106, as shown in fig. 1B.
Wherein the fifth depth D5 is less than the first depth D1. Wherein the interconnect structure 107 is used to connect at least one of the source 1051, the drain 1052, and the gate 1053. The method of forming the gate 1053 may be a gate-first process or a gate-last process.
Wherein the number of transistors 105 is at least one. Illustratively, the source 1051 and the drain 1052 are located below the first surface 1001, and the gate 1053 is located above the first surface 1001. At this time, the transistor 105 is a normal transistor. In the subsequent process steps, a second gate electrode may be formed on the second surface 1002 of the first substrate 100, and the second gate electrode and the source electrode 1051, the drain electrode 1052, and the gate electrode 1053 (the first gate electrode) may form a double gate transistor.
Meanwhile, when the transistor 105 is formed, other devices such as a diode, a resistor, a capacitor, and the like may be formed, which is not limited herein.
The method of the embodiment of the invention directly forms devices such as a transistor on a bulk silicon substrate instead of a silicon substrate on a thin film insulator. The process of forming transistors and the like is done the same as forming CMOS devices on bulk silicon substrates.
Step A3: a carrier substrate 200 is provided and the side of the first substrate 100 on which the dielectric capping layer 106 is formed is bonded to the carrier substrate 200, as shown in fig. 1C.
In one example, before the side of the first substrate 100 on which the dielectric capping layer 106 is formed is bonded to the carrier substrate 200, a bonding capping layer 300 is formed on a surface of the side of the first substrate 100 on which the dielectric capping layer 106 is formed and on a corresponding surface of the carrier substrate 200, respectively, as shown in fig. 1C. Illustratively, the material of the bonding cap layer 300 may be silicon oxide or other suitable material.
For example, the method of bonding the first substrate 100 and the carrier substrate 200 may be fusion bonding (fusion bonding) or other suitable methods.
The carrier substrate 200 may be a silicon substrate or other suitable substrate. In one example, the carrier substrate 200 has the same shape and size as the first substrate 100.
The carrier substrate 200 may provide support for the first substrate 100 during a subsequent thinning process for the first substrate 100.
Step A4: the first substrate 100 is subjected to a thinning process from a second surface 1002 opposite to the first surface 1001, the thinning process including: the first substrate 100 is subjected to back grinding (backside grinding) to a sixth depth D6 (not shown), and then the first substrate 100 is subjected to wet etching to a second depth D2, as shown in fig. 1D.
Wherein the sixth depth D6 is greater than the second depth D2.
The back grinding method may be CMP (chemical mechanical polishing) or other suitable process. The wet etching may use various available etching solutions, such as TMAH, and the like, and is not limited herein.
In this step, after the wet etching is performed on the first substrate 100 to the second depth D2, a step of performing low temperature annealing on the first substrate 100 (including the carrier substrate 200) may be further included.
Step a5, continuing the thinning process of the first substrate 100 from the second surface 1002 opposite to the first surface 1001, comprises: the first substrate 100 is subjected to CMP and the CMP is stopped at the bottom of the shallow trench isolation 103 (illustratively, the pad layer 1031 acts as a stop layer for the CMP), and then the first substrate 100 is subjected to wet etching to a fifth depth D5. Through this step, the resulting structure is shown in FIG. 1E.
The CMP may employ various available CMP processes, among others. The wet etching may use various feasible etching solutions, such as TMAH, etc.
In this step, the pad layer 1031 of the shallow trench isolation 103 may be used as a stop layer for the CMP.
The step a4 and the step a5 collectively implement a process of thinning the first substrate 100 from the second surface 1002.
In the method of the embodiment of the present invention, since the method includes the steps of bonding the carrier substrate to the first substrate and thinning the first substrate, the first substrate 100 may use a common bulk silicon (bulk Si) substrate as a basic device layer substrate, and does not need to use a thin-film silicon-on-insulator (TF SOI) substrate or a high-resistance substrate (high-resistance substrate), so that the cost can be reduced.
Moreover, the method of this embodiment can perform the thinning process to the desired thickness accurately and ensure the desired uniformity by performing the thinning process by using the back grinding, CMP, wet etching, and the like (matching through a plurality of stop layers).
In addition, as the bonding process between the silicon substrates is more and more mature, the method of the embodiment can reduce the cost and ensure the yield of the manufactured semiconductor device.
Step A6: a second gate electrode 2053 corresponding to the gate electrode 1053 (first gate electrode) is formed on the second surface 1002 of the first substrate 100, and a second source electrode 2051 corresponding to the source electrode 1051 and a second drain electrode 2052 corresponding to the drain electrode 1052 are formed from the second surface 1002 side, in which the second source electrode 2051 is connected to the source electrode 1051 (first source electrode) and the second drain electrode 2051 is connected to the drain electrode 1051 (second drain electrode), as shown in fig. 1F.
The gate 1053 (first gate), the second gate 2053, the second source 2051, the source 1051 (first source), the second drain 2051, and the drain 1051 (second drain) together form a dual-gate transistor 105', as shown in fig. 1F.
Namely, the preparation of the double-gate transistor can be realized on the bulk silicon substrate by the method of the embodiment of the invention.
Step A7: forming a dielectric capping layer 108 on the second surface 1002 of the first substrate 100, and forming at least one through-silicon via (TSV)109 penetrating the dielectric capping layer 108, the shallow trench isolation 103, and the dielectric capping layer 106 and connected to the interconnect structure 107 on the surface of the dielectric capping layer 106, as shown in fig. 1G.
Illustratively, the method of forming the Through Silicon Via (TSV)109 includes: etching to form a via hole penetrating through the dielectric cap layer 108, the shallow trench isolation 103 and the dielectric cap layer 106;
filling a conductive material in the via hole;
excess conductive material is removed by CMP to form the through-silicon via 109.
The conductive material 109 may be a metal or other suitable material.
That is, the method of the embodiment of the invention can replace a thin film silicon-on-insulator substrate with a first substrate (for example, a bulk silicon substrate), realize the preparation of the double-gate transistor on the first substrate, and realize the interconnection of devices positioned on the upper and lower surfaces of the first substrate through a silicon through hole.
Step A8: forming a contact hole (CT)1101 located above the second gate electrode 2053 and a conductive plug 110 located in the contact hole 1101 in the dielectric capping layer 108; then, an interconnect structure 111 connected to the through-silicon via 109 and the conductive plug 110 is formed on the dielectric capping layer 108, as shown in fig. 1H.
The material of the conductive plug 110 may be copper, tungsten, or other suitable materials. Generally, the conductive plug 110 is connected to the second gate 2053.
Illustratively, the method of forming the contact hole 1101 and the conductive plug 110 includes:
a contact hole 1101 over the second gate 2053 is formed in the dielectric capping layer 108 by etching, which may be dry etching, wet etching or other suitable method.
Filling a conductive material in the contact hole 1101;
excess conductive material is removed by CMP to form conductive plug 110 located within contact hole 1101.
Wherein, before the step of etching to form the contact hole 1101, a step of depositing a dielectric layer above the dielectric cap layer 108 may be further included. When the step of depositing the dielectric layer is included, in the step of etching to form the contact hole, the newly deposited dielectric layer and the existing dielectric cap layer 108 are etched together, and the formed contact hole 1101 is located in the newly deposited dielectric layer and the dielectric cap layer 108.
The material of the interconnect structure 111 may be a conductive metal (e.g., copper) or other suitable material. The method for forming the interconnect structure 111 may adopt various available methods, and is not limited herein.
Thus, the description of the key steps of the method of manufacturing a semiconductor device of the embodiment of the present invention is completed. It will be understood by those skilled in the art that, in addition to the above steps a1 to A8, other steps may be included between adjacent steps and after step A8, and the steps are not limited herein.
According to the manufacturing method of the semiconductor device, the carrying substrate is jointed on the first substrate and the first substrate is thinned, so that a common bulk silicon substrate instead of a thin film silicon-on-insulator substrate can be used as the first substrate, and therefore cost can be reduced.
Fig. 2 shows a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, which is used to briefly show an exemplary flow of the above method. The method specifically comprises the following steps:
in step S101, providing a first substrate, and forming a shallow trench isolation having a first depth in the first substrate from a first surface of the first substrate, wherein the first depth is a distance from a bottom of the shallow trench isolation to the first surface;
in step S102, forming a source, a drain and a gate of a transistor on a first surface side of the first substrate, and forming a first dielectric capping layer covering the first surface and an interconnect structure on the first dielectric capping layer;
in step S103, providing a carrier substrate, and bonding the side of the first substrate on which the first dielectric cap layer is formed with the carrier substrate;
in step S104, thinning the first substrate from a second surface of the first substrate opposite to the first surface to a second depth, where the second depth is a distance from the second surface to the first surface after the thinning;
in step S105, a second dielectric capping layer is formed on the second surface of the first substrate, and at least one through-silicon via penetrating through the second dielectric capping layer, the shallow trench isolation, and the first dielectric capping layer and connected to the interconnect structure is formed.
Another embodiment of the present invention provides an electronic device including an electronic component and a semiconductor device connected to the electronic component. Wherein the semiconductor device is a semiconductor device manufactured according to the manufacturing method of the semiconductor device as described above. The electronic component may be any suitable component.
Illustratively, the method of manufacturing the semiconductor device includes:
step S101: providing a first substrate, and forming shallow trench isolation with a first depth in the first substrate from a first surface of the first substrate, wherein the first depth is the distance from the bottom of the shallow trench isolation to the first surface;
step S102: forming a source electrode, a drain electrode and a grid electrode of a transistor on one side of the first surface of the first substrate, and forming a first dielectric cap layer covering the first surface and an interconnection structure positioned on the first dielectric cap layer;
step S103: providing a carrier substrate, and bonding one side of the first substrate, on which the first dielectric cap layer is formed, with the carrier substrate;
step S104: thinning the first substrate from a second surface of the first substrate opposite to the first surface to a second depth, wherein the second depth is the distance from the second surface to the first surface after thinning;
step S105: and forming a second dielectric capping layer on the second surface of the first substrate, and forming at least one silicon through hole which penetrates through the second dielectric capping layer, the shallow trench isolation and the first dielectric capping layer and is connected with the interconnection structure.
The electronic device of this embodiment may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a voice pen, an MP3, an MP4, and a PSP, and may also be any intermediate product including the semiconductor device.
The electronic device of the embodiment of the invention has the advantages as well as the advantages due to the use of the semiconductor device manufactured according to the method.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (13)
1. A method of manufacturing a semiconductor device, the method comprising:
step S101: providing a first substrate (100), wherein the first substrate (100) is a bulk silicon substrate, the semiconductor device is formed on the bulk silicon substrate, shallow trench isolation (103) with a first depth is formed in the first substrate from a first surface (1001) of the first substrate, wherein the first depth is the distance from the bottom of the shallow trench isolation to the first surface, after the shallow trench isolation is formed and before a transistor is formed, ion implantation is carried out on the first substrate from the first surface to form an etching stop layer (104) with a fifth depth below a region where the transistor is to be formed, wherein the fifth depth is the distance from the etching stop layer to the first surface, and the fifth depth is smaller than the first depth;
step S102: after forming an etching stop layer (104), forming a source electrode (1051), a drain electrode (1052) and a grid electrode (1053) of a transistor on one side of the first surface of the first substrate, and forming a first dielectric capping layer (106) covering the first surface and an interconnection structure (107) positioned on the first dielectric capping layer;
step S103: providing a carrier substrate (200), and bonding the side of the first substrate, on which the first dielectric cap layer is formed, with the carrier substrate;
step S104: thinning the first substrate from a second surface opposite to the first surface to a second depth, wherein the second depth is the distance from the second surface to the first surface after thinning;
step S105: forming a second dielectric capping layer (108) on the second surface of the first substrate, forming at least one through-silicon-via (109) penetrating the second dielectric capping layer, the shallow trench isolation and the first dielectric capping layer and connected to the interconnect structure; wherein, the step S104 further includes:
step S1041: carrying out back grinding treatment on the first substrate;
step S1042: performing wet etching on the first substrate to stop at the second depth;
step S1043: performing CMP on the first substrate and stopping the CMP at the bottom of the shallow trench isolation, wherein the shallow trench isolation comprises a liner layer and a body structure layer, and the liner layer is used as a stop layer of the CMP;
step S1044: and carrying out wet etching on the first substrate to the fifth depth.
2. The method for manufacturing a semiconductor device according to claim 1, wherein in the step S102, the transistor is a double-gate transistor; further, between the step S104 and the step S105, a step S1015 is further included:
and forming a second grid electrode (2053), a second source electrode (2051) and a second drain electrode (2052) of the double-grid transistor on one side of the second surface of the first substrate, wherein the second grid electrode and the grid electrode are oppositely arranged, the second source electrode is connected with the source electrode, and the second drain electrode is connected with the drain electrode.
3. The method for manufacturing a semiconductor device according to claim 2, further comprising, after the step S105, a step S106 of:
forming a contact hole (1101) above the second gate and a conductive plug (110) in the contact hole in the dielectric capping layer.
4. The method for manufacturing a semiconductor device according to claim 1, wherein in the step S102, the source electrode and the drain electrode are located below the first surface, and the gate electrode is located above the first surface.
5. The method for manufacturing the semiconductor device according to claim 2, wherein in the step S102, the second source electrode and the second drain electrode are located below the second surface, and the second gate electrode is located above the second surface.
6. The method of manufacturing a semiconductor device according to claim 1, wherein in the step S101, the first substrate comprises a doped epitaxial layer (101) having a third depth, wherein the third depth is a distance from the doped epitaxial layer to the first surface, and the third depth is greater than or equal to the first depth.
7. The method of manufacturing a semiconductor device according to claim 1, wherein in the step S101, before forming the shallow trench isolation, the first substrate is ion-implanted from the first surface to form a first implanted doped layer (102) having a fourth depth in the first substrate, wherein the fourth depth is a distance from the first implanted doped layer to the first surface, and the fourth depth is greater than or equal to the first depth.
8. The method for manufacturing a semiconductor device according to claim 1, wherein the second depth is equal to the first depth.
9. The method for manufacturing a semiconductor device according to claim 6, wherein the second depth is equal to the third depth.
10. The method for manufacturing a semiconductor device according to claim 7, wherein the second depth is equal to the fourth depth.
11. The method for manufacturing a semiconductor device according to claim 1, wherein the second depth is equal to the fifth depth.
12. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of wet etching the first substrate between the step S1041 and the step S1042.
13. An electronic device comprising an electronic component and a semiconductor device connected to the electronic component, wherein the semiconductor device is manufactured by a method comprising:
step S101: providing a first substrate, wherein the first substrate (100) is a bulk silicon substrate, the semiconductor device is formed on the bulk silicon substrate, shallow trench isolation with a first depth is formed in the first substrate from a first surface of the first substrate, wherein the first depth is the distance from the bottom of the shallow trench isolation to the first surface, and ion implantation is carried out on the first substrate from the first surface to form an etching stop layer (104) with a fifth depth below a region where a transistor is to be formed, wherein the fifth depth is the distance from the etching stop layer to the first surface, and the fifth depth is smaller than the first depth;
step S102: after an etching stop layer (104) is formed, forming a source electrode, a drain electrode and a grid electrode of a transistor on one side of the first surface of the first substrate, and forming a first dielectric cap layer covering the first surface and an interconnection structure positioned on the first dielectric cap layer;
step S103: providing a carrier substrate, and bonding one side of the first substrate, on which the first dielectric cap layer is formed, with the carrier substrate;
step S104: thinning the first substrate from a second surface of the first substrate opposite to the first surface to a second depth, wherein the second depth is the distance from the second surface to the first surface after thinning;
step S105: forming a second dielectric capping layer on the second surface of the first substrate, and forming at least one through-silicon-via penetrating through the second dielectric capping layer, the shallow trench isolation and the first dielectric capping layer and connected to the interconnection structure;
wherein, the step S104 further includes: step S1041: carrying out back grinding treatment on the first substrate; step S1042: performing wet etching on the first substrate to stop at the second depth; step S1043: performing CMP on the first substrate and stopping the CMP at the bottom of the shallow trench isolation; step S1044: and carrying out wet etching on the first substrate to the fifth depth.
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