CN117766588B - Super junction dual SOI-LDMOS device with extended drain structure and manufacturing method - Google Patents

Abstract

The invention provides a super junction double SOI-LDMOS device with an extended drain structure and a manufacturing method thereof, wherein the device comprises the following components: a second SOI layer on the second buried oxide layer, comprising a semiconductor region and a semiconductor extension drain contact region; the first SOI layer is positioned on the first buried oxide layer and comprises a body contact region, a source region, a drain region and a drift region; a drain metal, wherein a first portion of the drain metal is in contact with the first buried oxide layer parallel to a side surface of the device in a longitudinal direction, and a lower surface thereof is in contact with an upper surface of the semiconductor extension drain contact region; a second portion of the drain metal is in contact with an upper surface of the semiconductor drain region. When the device is conducted, the first semiconductor region, the second semiconductor region and the extended drain structure which are alternately arranged in the second SOI layer are utilized, so that majority carriers are induced on the surface of the drift region of the first SOI layer, and the specific on-resistance is reduced; the potential field distribution of the drift region is also improved when the device is turned off, thereby increasing the breakdown voltage.

Description

Super junction dual SOI-LDMOS device with extended drain structure and manufacturing method

Technical Field

The present invention belongs to the field of semiconductor devices, and in particular relates to a super junction dual SOI-LDMOS device with an extended drain structure and a manufacturing method thereof.

Background technique

The dual SOI device has an additional SOI layer, an intermediate silicon layer below the traditional buried oxide layer. It can act as an independent electrode to apply both positive and negative bias in the circuit, which broadens the flexibility of integrated circuit design. In addition, this electrode can further optimize speed, power consumption, threshold voltage drift and leakage current. Due to its unique structure, the dual SOI device is very promising in 3D fin waveguide fabrication, high-resolution detectors and even in-situ sensing applications.

In the long-term development process of power devices, the demand for power dual SOI structures has been developing in the direction of high withstand voltage and low specific on-resistance. At the same time, due to the "silicon limit" relationship, that is, the specific on-resistance of the device is proportional to the 2.5th power of the breakdown voltage, and the increase in breakdown voltage will also lead to an increase in specific on-resistance. The contradictory relationship between reducing specific on-resistance and increasing breakdown voltage has limited the development of devices.

Summary of the invention

The object of the present invention is to provide a super junction dual SOI-LDMOS device with an extended drain structure and a manufacturing method thereof. When the device is turned on, the first semiconductor region and the second semiconductor region alternately arranged in the second SOI layer and the extended drain structure (i.e., the drain metal 13) are used to induce majority carriers on the surface of the drift region of the first SOI layer, thereby reducing the specific on-resistance; when the device is turned off, the potential field distribution of the drift region is improved, thereby increasing the breakdown voltage, so that a larger FOM value (square of the breakdown voltage/specific on-resistance) can be obtained.

A super junction dual SOI-LDMOS device with an extended drain structure, comprising:

Substrate 1;

A second buried oxide layer 2, located on the substrate 1;

The second SOI layer is located on the second buried oxide layer 2 and includes:

The semiconductor region comprises a first semiconductor region 4 and a second semiconductor region 5 which are arranged in parallel and have different doping types; the first semiconductor region 4 is parallel to a lateral side of the device and contacts a lateral side of the second semiconductor region 5 which is parallel to the lateral side of the device;

A semiconductor extended drain contact region 3, one side of which is parallel to the longitudinal direction of the device and contacts with one side of the semiconductor region parallel to the longitudinal direction of the device;

A first buried oxide layer 6, located on the second SOI layer;

The first SOI layer is located on the first buried oxide layer 6, and includes a semiconductor body contact region 7, a semiconductor source region 8, a semiconductor drain region 9, and a drift region between the semiconductor body contact region 7 and the semiconductor drain region 9;

The semiconductor drain region 9 is arranged close to the semiconductor body contact region 7; a side surface of the semiconductor source region 8 parallel to the longitudinal direction of the device is in contact with the semiconductor body contact region 7;

The drift region includes a third semiconductor region 15 and a fourth semiconductor region 16 arranged in parallel;

The third semiconductor region 15 is parallel to a lateral side of the device and contacts a lateral side of the fourth semiconductor region 16 which is parallel to the lateral side of the device.

The third semiconductor region 15 has the same doping type as the first semiconductor region 4 ; the fourth semiconductor region 16 has the same doping type as the second semiconductor region 5 ;

A drain metal 13, wherein a first portion of the drain metal 13 is in contact with the first buried oxide layer 6 on a side surface parallel to the longitudinal direction of the device, and a lower surface thereof is in contact with an upper surface of the semiconductor extended drain contact region 3; and a second portion of the drain metal 13 is in contact with an upper surface of the semiconductor drain region 9;

The insulating dielectric layer 14 is disposed between the first portion and the second portion of the drain metal 13 and is in contact with the semiconductor drain region 9;

A source metal 10 in contact with the upper surface of the semiconductor source region 8;

The gate metal 11 forms a gap with the source metal 10 and is disposed on the gate oxide layer 12. The gate oxide layer 12 is in contact with the semiconductor body contact region 7, the semiconductor source region 8 and the upper surface of the drift region.

Preferably, the first semiconductor region 4 is placed directly below the fourth semiconductor region 16 ; and the second semiconductor region 5 is placed directly below the third semiconductor region 15 .

Preferably, the doping type of the first semiconductor region 4 is P type or N type.

Preferably, the doping concentration C1 of the first semiconductor region 4 is lower than the doping concentration C3 of the third semiconductor region 15;

The doping concentration C2 of the second semiconductor region 5 is lower than the doping concentration C4 of the fourth semiconductor region 16 .

A method for manufacturing a super junction dual SOI-LDMOS device with an extended drain structure, the super junction dual SOI-LDMOS device with an extended drain structure comprising the following steps:

Step 1, growing an oxide layer on a substrate 1 to form a second buried oxide layer 2;

Step 2, ion implantation is performed on the second buried oxide layer 2 to form a semiconductor region and a semiconductor extended drain contact region 3;

Step 3, growing an oxide layer on the second SOI layer to form a first buried oxide layer 6;

Step 4: depositing oxide to form an insulating dielectric layer 14;

Step 5, etching oxide at a preset position;

Step 6, ion implantation is performed on the first buried oxide layer 6 to form a semiconductor source region 8, a semiconductor body contact region 7, a drift region, and a semiconductor drain region 9 respectively;

Step 7, growing an oxide layer in the semiconductor body contact region 7, the semiconductor source region 8 and the drift region to form a gate oxide layer 12;

Step 8, disposing gate metal 11 on gate oxide layer 12, disposing source metal 10 on semiconductor source region 8, disposing the second part of drain metal 13 on semiconductor drain region 9, and disposing the first part of drain metal 13 on semiconductor extended drain contact region 3.

Compared with the prior art, the advantages of the present invention are:

1. When the device is turned on, the first semiconductor region and the second semiconductor region and the extended drain structure arranged alternately in the second SOI layer are used to induce majority carriers on the surface of the drift region of the first SOI layer, thereby reducing the specific on-resistance.

2. When the device is turned off, the electric field and potential distribution in the drift region are improved, the breakdown voltage is increased, and a larger FOM value can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a three-dimensional diagram of a super junction dual SOI-LDMOS device with an extended drain structure;

FIG2 is a two-dimensional potential distribution diagram of a super junction dual SOI-LDMOS device with an extended drain structure;

FIG3 is a two-dimensional potential distribution diagram of a conventional double SOI structure;

FIG4 is a graph showing the impact ionization rate distribution of a super junction dual SOI-LDMOS device with an extended drain structure;

FIG5 is a diagram showing the impact ionization rate distribution of a conventional double SOI structure;

FIG6 is a three-dimensional electric field distribution diagram of a super junction dual SOI-LDMOS device with an extended drain structure;

FIG7 is a three-dimensional electric field distribution diagram of a conventional SOI structure;

FIG8 is a graph showing the breakdown voltage variation trend of a super junction dual SOI-LDMOS device with an extended drain structure and a conventional dual SOI structure with drift region concentration when the drift region length is 4 μm;

9 is a graph showing the breakdown voltage and specific on-resistance of a super junction dual SOI-LDMOS device with an extended drain structure and a conventional dual SOI structure as a function of the length of the drift region;

FIG. 10 is a cross-sectional view of FIG. 1 .

Among them, 1-substrate, 2-second buried oxide layer, 3-semiconductor extended drain contact region, 4-first semiconductor region, 5-second semiconductor region, 6-first buried oxide layer, 7-semiconductor body contact region, 8-semiconductor source region, 9-semiconductor drain region, 10-source metal, 11-gate metal, 12-gate oxide layer, 13-drain metal, 14-insulating dielectric layer, 15-third semiconductor region, 16-fourth semiconductor region.

Detailed ways

The following will be described in more detail with reference to the schematic diagram of the super junction dual SOI-LDMOS device with extended drain structure and the manufacturing method of the present invention, wherein the preferred embodiment of the present invention is shown, and it should be understood that the present invention described herein can be modified by those skilled in the art, while still achieving the advantageous effects of the present invention. Therefore, the following description should be understood as being widely known to those skilled in the art, and not as a limitation of the present invention.

As shown in FIG. 1 and FIG. 10 , a super junction dual SOI-LDMOS device with an extended drain structure includes:

Substrate 1;

A second buried oxide layer 2, located on the substrate 1;

The second SOI layer is located on the second buried oxide layer 2 and includes:

The semiconductor region comprises a first semiconductor region 4 and a second semiconductor region 5 which are arranged in parallel and have different doping types; the first semiconductor region 4 is parallel to a lateral side of the device and contacts a lateral side of the second semiconductor region 5 which is parallel to the lateral side of the device;

A semiconductor extended drain contact region 3, one side of which is parallel to the longitudinal direction of the device and contacts with one side of the semiconductor region parallel to the longitudinal direction of the device;

A first buried oxide layer 6, located on the second SOI layer;

The first SOI layer is located on the first buried oxide layer 6, and includes a semiconductor body contact region 7, a semiconductor source region 8, a semiconductor drain region 9, and a drift region between the semiconductor body contact region 7 and the semiconductor drain region 9;

The semiconductor drain region 9 is arranged close to the semiconductor body contact region 7 relative to the semiconductor source region 8; a side surface of the semiconductor source region 8 parallel to the longitudinal direction of the device is in contact with the semiconductor body contact region 7;

The drift region includes a third semiconductor region 15 and a fourth semiconductor region 16 arranged in parallel;

The third semiconductor region 15 is parallel to a lateral side of the device and contacts a lateral side of the fourth semiconductor region 16 which is parallel to the lateral side of the device.

The third semiconductor region 15 has the same doping type as the first semiconductor region 4 ; the fourth semiconductor region 16 has the same doping type as the second semiconductor region 5 ;

Drain metal 13 (corresponding voltage is V _d ), the first part of the drain metal 13 is in contact with the first buried oxide layer 6 on a side surface parallel to the longitudinal direction of the device, and the lower surface thereof is in contact with the upper surface of the semiconductor extended drain contact region 3; the second part of the drain metal 13 is in contact with the upper surface of the semiconductor drain region 9;

The first portion and the second portion of the drain metal 13 are wire-connected.

The insulating dielectric layer 14 is disposed between the first portion and the second portion of the drain metal 13 and is in contact with the semiconductor drain region 9;

A source metal 10 in contact with the upper surface of the semiconductor source region 8;

A gap is formed between the gate metal 11 (corresponding voltage is V _g ) and the source metal 10 , which is placed on the gate oxide layer 12 , and the gate oxide layer 12 is in contact with the semiconductor body contact region 7 , the semiconductor source region 8 and the upper surface of the drift region.

The first semiconductor region 4 is placed directly below the fourth semiconductor region 16 ; the second semiconductor region 5 is placed directly below the third semiconductor region 15 .

The doping type of the first semiconductor region 4 is P type or N type. That is, when the doping type of the first semiconductor region 4 is P type, the third semiconductor region 15 is P type, the second semiconductor region 5 is N type, and the fourth semiconductor region 16 is N type.

The doping concentration C1 of the first semiconductor region 4 is lower than the doping concentration C3 of the third semiconductor region 15;

The doping concentration C2 of the second semiconductor region 5 is lower than the doping concentration C4 of the fourth semiconductor region 16 .

In dual SOI LDMOS devices, in order to achieve better electrical performance, a concentration gradient, i.e., concentration difference, needs to be formed between the p-type semiconductor and the n-type semiconductor. This concentration difference can make it easier for electrons and holes to diffuse in the device, thereby improving the efficiency and performance of the device. At the same time, the concentration difference can also reduce carrier recombination in the device, thereby reducing reverse leakage current. Therefore, the concentration difference is one of the important factors that enable dual SOI-LDMOS devices to achieve high breakdown voltage.

A method for manufacturing a super junction dual SOI-LDMOS device with an extended drain structure comprises the following steps:

Step 1, growing an oxide layer on a substrate 1 to form a second buried oxide layer 2;

Step 2, ion implantation is performed on the second buried oxide layer 2 to form a semiconductor region and a semiconductor extended drain contact region 3;

Step 3, growing an oxide layer on the second SOI layer to form a first buried oxide layer 6;

Step 4: depositing oxide to form an insulating dielectric layer 14;

Step 5, etching oxide at a preset position;

Step 6: Ion implantation is performed on the first buried oxide layer 6 to form a semiconductor source region 8, a semiconductor body contact region 7, a drift region, and a semiconductor drain region 9, respectively.

Step 7: growing an oxide layer in the semiconductor body contact region 7, the semiconductor source region 8 and the drift region to form a gate oxide layer 12.

Step 8, disposing gate metal 11 on gate oxide layer 12, disposing source metal 10 on semiconductor source region 8, disposing the second part of drain metal 13 on semiconductor drain region 9, and disposing the first part of drain metal 13 on semiconductor extended drain contact region 3.

In order to verify the beneficial effects of the embodiments of the present invention, FIGS. 2 to 7 analyze the structures of the present invention and the traditional structures in terms of potential, collision ionization rate and electric field.

The view in FIG. 2 is a front view of the device.

Figures 2 and 3 show the two-dimensional potential distribution diagrams of the super junction dual SOI-LDMOS device with extended drain structure and the traditional dual SOI structure, respectively. It can be seen from the figure that the potential lines of the traditional dual SOI structure are concentrated at the drain of the device, and the ability to bear voltage is limited, while the potential lines of the drift region of the structure of the present invention are evenly distributed inside the drift region, and the entire drift region can evenly bear the applied voltage, so the breakdown voltage is higher.

Figures 4 and 5 are the impact ionization rate distribution diagrams of the super junction dual SOI-LDMOS device with extended drain structure and the traditional dual SOI structure, respectively. It can be seen from the figure that the highest point (i.e., the maximum value) of the impact ionization rate of the traditional structure is much higher than that of the structure of the present invention, and it is easier to break down, so the structure of the present invention has a stronger withstand voltage capability.

Figures 6 and 7 show the three-dimensional electric field distribution diagrams of the super junction dual SOI-LDMOS device with extended drain structure and the traditional dual SOI structure, respectively. It can be seen from the figure that the electric field peak of the traditional structure is at the highest point of the device collision ionization rate, that is, the drain end of the device (drain metal 13), and the electric field is not uniformly distributed, while the electric field of the structure of the present invention is uniformly distributed. Therefore, the device of the present invention can withstand higher voltages. Among them, in Figures 6 and 7, E is the electric field intensity.

In order to verify the beneficial effects of the embodiments of the present invention, FIG8-FIG9 compares the structure of the present invention with the traditional structure.

FIG8 is a graph showing the breakdown voltage variation trend of the super junction dual SOI-LDMOS device with an extended drain structure and the traditional dual SOI structure with the drift region concentration when the drift region length (i.e., the dimension parallel to the lateral direction of the device) is 4 μm. It can be seen from the graph that the breakdown voltage of the structure of the present invention is higher than that of the traditional structure because the potential field distribution of the drift region is improved when the device is turned off, and reaches a maximum value of 72 V when the drift region concentration is 10 ¹⁸ cm ^-3 .

FIG. 9 is a graph showing the breakdown voltage and specific on-resistance of a super junction dual SOI-LDMOS device with an extended drain structure and a traditional dual SOI structure as a function of the drift region length.

It can be seen from the left coordinate axis of FIG. 9 that the breakdown voltage of the structure of the present invention is higher than that of the conventional structure because the potential field distribution in the drift region is improved when the device is turned off, and reaches a maximum value of 72V when the drift region length is 4μm, and then remains unchanged. The conventional structure reaches a maximum value of 33V when the drift region length is 2μm, and then remains unchanged.

It can be seen from the right coordinate axis in Figure 9 that the specific on-resistance of the structure of the present invention is lower than that of the traditional structure because when the device is turned on, the first semiconductor region and the second semiconductor region and the extended drain structure are alternately arranged in the second SOI layer, so that majority carriers are induced on the surface of the drift region of the first SOI layer. Therefore, its specific on-resistance is lower than that of the traditional structure.

Table 1 shows the variation of FOM values of the super junction dual SOI-LDMOS device with extended drain structure and the traditional dual SOI structure with the drift region length. It can be seen intuitively from Table 1 that the FOM value of the structure of the present invention reaches a maximum of 23.23 MW•cm ^-2 when the drift region length is 3μm, and the traditional structure reaches a maximum of 5.3 MW•cm ^-2 when the drift region length is 1μm, and decreases with the increase of the drift region length. It can be seen from the table that the FOM value of the structure of the present invention is improved by 338% compared with the traditional dual SOI structure.

Table 1

Drift region length/μm FOM value of the structure of the present invention/MW•cm ^-2 Traditional structure FOM value/MW•cm ^-2 1 7.4 5.3 2 18.51 4.94 3 23.23 3.42 4 22.17 2.71 5 18.83 2.27 6 16.2 1.95

The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims (5)

1. A superjunction double-SOI-LDMOS device having an extended drain structure, comprising:

a substrate (1);

The second oxygen-buried layer (2) is positioned on the substrate (1);

a second SOI layer on the second buried oxide layer (2), comprising:

A semiconductor region comprising a first semiconductor region (4) and a second semiconductor region (5) arranged in parallel and having different doping types; the first semiconductor region (4) is parallel to one lateral surface of the device and is contacted with one lateral surface of the second semiconductor region (5) parallel to the device lateral direction;

A semiconductor extended drain contact region (3) parallel to one side of the device longitudinal direction and in contact with one side of the semiconductor region parallel to the device longitudinal direction;

A first buried oxide layer (6) on the second SOI layer;

The first SOI layer is positioned on the first oxygen-buried layer (6) and comprises a semiconductor body contact region (7), a semiconductor source region (8), a semiconductor drain region (9) and a drift region between the semiconductor body contact region (7) and the semiconductor drain region (9);

the semiconductor drain region (9) is arranged close to the semiconductor body contact region (7); a side surface of the semiconductor source region (8) parallel to the longitudinal direction of the device is contacted with the semiconductor body contact region (7);

the drift region comprises a third semiconductor region (15) and a fourth semiconductor region (16) arranged in parallel;

Wherein the third semiconductor region (15) is parallel to one lateral surface of the device transverse direction and is contacted with one lateral surface of the fourth semiconductor region (16) parallel to the device transverse direction;

the doping type of the third semiconductor region (15) is the same as that of the first semiconductor region (4); the doping type of the fourth semiconductor region (16) is the same as that of the second semiconductor region (5);

A drain metal (13), wherein a first part of the drain metal (13) is parallel to one side surface of the longitudinal direction of the device and is in contact with the first oxygen-buried layer (6), and the lower surface of the first part of the drain metal is in contact with the upper surface of the semiconductor extension drain contact region (3); a second portion of the drain metal (13) is in contact with the upper surface of the semiconductor drain region (9);

an insulating dielectric layer (14) interposed between the first portion and the second portion of the drain metal (13) and in contact with the semiconductor drain region (9);

A source metal (10) in contact with the upper surface of the semiconductor source region (8);

And a gate metal (11) forming a gap with the source metal (10), which is disposed on the gate oxide layer (12), the gate oxide layer (12) being simultaneously in contact with the upper surfaces of the semiconductor body contact region (7), the semiconductor source region (8) and the drift region.

2. The super-junction double-SOI-LDMOS device with extended drain structure of claim 1, wherein the first semiconductor region (4) is placed directly under a fourth semiconductor region (16); the second semiconductor region (5) is disposed directly below the third semiconductor region (15).

3. The super-junction double-SOI-LDMOS device with extended drain structure according to claim 1, wherein the doping type of the first semiconductor region (4) is P-type or N-type.

4. The super-junction double-SOI-LDMOS device with extended drain structure according to claim 1, wherein the doping concentration C1 of the first semiconductor region (4) is lower than the doping concentration C3 of the third semiconductor region (15);

the doping concentration C2 of the second semiconductor region (5) is lower than the doping concentration C4 of the fourth semiconductor region (16).

5. A method for manufacturing a super-junction double-SOI-LDMOS device with an extended drain structure according to any of claims 1 to 4, characterized in that it comprises the steps of:

Step 1, growing an oxide layer on a substrate (1) to form a second buried oxide layer (2);

step 2, forming a semiconductor region and a semiconductor extension drain contact region (3) on the second oxygen-buried layer (2) by ion implantation;

step 3, growing an oxide layer on the second SOI layer to form a first buried oxide layer (6);

Step 4, depositing oxide to form an insulating medium layer (14);

Step 5, etching oxide at a preset position;

Step 6, ion implantation is performed on the first oxygen-buried layer (6) to form a semiconductor source region (8), a semiconductor body contact region (7), a drift region and a semiconductor drain region (9) respectively;

step 7, growing an oxide layer on the semiconductor body contact region (7), the semiconductor source region (8) and the drift region to form a gate oxide layer (12);

Step 8, disposing a gate metal (11) on the gate oxide layer (12), disposing a source metal (10) on the semiconductor source region (8), disposing a second portion of a drain metal (13) on the semiconductor drain region (9), and disposing a first portion of the drain metal (13) on the semiconductor extended drain contact region (3).