CN104979382A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN104979382A CN104979382A CN201410131272.5A CN201410131272A CN104979382A CN 104979382 A CN104979382 A CN 104979382A CN 201410131272 A CN201410131272 A CN 201410131272A CN 104979382 A CN104979382 A CN 104979382A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 299
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 239000002131 composite material Substances 0.000 claims abstract description 23
- 238000002347 injection Methods 0.000 claims description 43
- 239000007924 injection Substances 0.000 claims description 43
- 238000000034 method Methods 0.000 claims description 36
- 230000004888 barrier function Effects 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 11
- 238000009792 diffusion process Methods 0.000 claims description 9
- 238000000407 epitaxy Methods 0.000 claims 2
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 230000002459 sustained effect Effects 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000005669 field effect Effects 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 238000002955 isolation Methods 0.000 description 5
- 229910044991 metal oxide Inorganic materials 0.000 description 5
- 150000004706 metal oxides Chemical class 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000005496 tempering Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
The invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises the components of a plurality of stacked semiconductor layers; a plurality of composite doped regions which are parallelly and separately arranged in partial area of the plurality of semiconductor layers; a gate structure which is arranged on partial areas of the plurality of semiconductor layers in a second direction, wherein the gate structure covers partial areas of the plurality of composite doped regions; a first doped region which is arranged on a topmost layer in the plurality of semiconductor layers at a first side that is adjacent with the gate structure; and a second doped region which is arranged in the topmost layer in the plurality of semiconductor layers at the second side relative to the first side of the gate structure in a second direction and is adjacent with the plurality of composite doped regions. According to the semiconductor device and the manufacturing method provided by the invention, component performances of the semiconductor device such as driving current, on resistance and breakdown voltage can be sustained on condition that the size of the semiconductor device is reduced.
Description
Technical field
The invention relates to integrated circuit (IC) apparatus, and particularly there is about one semiconductor device and the manufacture method thereof of super-junction structures (Super junctionstructure).
Background technology
In recent years, along with the increase in demand of the such as high voltage device (Highvoltage device) of power semiconductor arrangement (Power semiconductor device), the research for the high voltage MOS field-effect transistor used in high voltage device (High voltage MOSFETs) technology also increases gradually.
The high voltage MOS field-effect transistor used in conventional power semiconductors device adopts a super-junction structures (Super junction structure) usually, to reach as reduced conducting resistance (On-resistance) and maintaining the effects such as high breakdown voltage (High breakdown voltage).
But, along with the micro trend of semiconductor fabrication, the component size of the high voltage MOS field-effect transistor in manufactured power semiconductor arrangement also phases down, and therefore just needs to consider how maintain along with the size micro of power semiconductor arrangement and improve showing as elements such as drive current, conducting resistance, breakdown voltages of high voltage MOS field-effect transistor in it.
Summary of the invention
In view of this, the invention provides a kind of semiconductor device and manufacture method thereof, with still can maintain under its size micro semiconductor device as the performance of the element such as drive current, conducting resistance, breakdown voltage.
According to an embodiment, the invention provides a kind of semiconductor device, comprising: mutually stacking multiple semiconductor layers, wherein said multiple semiconductor layer has one first conduction type; Multiple composite mixed district, parallel and be arranged in a part of region of described multiple semiconductor layer separatedly along a first direction, wherein said multiple composite mixed district has one second conduction type in contrast to this first conduction type; One grid structure, is arranged on a part of region of described multiple semiconductor layer along a second direction, and wherein this grid structure covers a part of region in described multiple composite mixed district; One first doped region, be arranged at the superiors in described multiple semiconductor layer along this second direction and one first side of this grid structure contiguous, wherein this first doped region has this second conduction type; And one second doped region, be arranged at along this second direction relative in the superiors in described multiple semiconductor layer of one second side of this grid structure first side and contiguous described multiple composite mixed district, wherein this second doped region has this second conduction type.
According to another embodiment, the invention provides a kind of manufacture method of semiconductor device, comprise the following steps: (a). provide on an insulating barrier and cover semiconductor substrate, comprise a bulk semiconductor layer, be positioned at one on this bulk semiconductor layer and bury insulating barrier underground and be positioned at this and bury 1 on insulating barrier first semiconductor layer underground, this first semiconductor layer has one first conduction type; (b). form parallel in this first semiconductor layer of multiple first injection region respectively and in the several parts separated, wherein said multiple first injection region has one second conduction type in contrast to this first conduction type along a first direction; (c). form one second semiconductor layer on this first semiconductor layer; And (d). along this first direction to form parallel in this second semiconductor layer of multiple second injection region respectively and in the several parts separated, wherein said multiple second injection region to lay respectively on one of described multiple first injection region and has this second conduction type; (e). implement a thermal diffusion process, respectively described multiple first injection region in this first semiconductor layer and described multiple second injection regions in this second semiconductor layer are diffused into one first doped region and one second doped region respectively; And (f): formed a grid structure on a part of region of this second semiconductor layer, one the 3rd doped region in a part of region of this second semiconductor layer of one first side of this grid structure and one the 4th doped region in a part of region of this second semiconductor layer of one second side of this first side relative to this grid structure, wherein this grid structure extends on this second semiconductor layer along a second direction, and the 3rd doped region and the 4th doped region have this second conduction type.
A kind of semiconductor device provided by the invention and manufacture method thereof, still can maintain under its size micro semiconductor device as the performance of the element such as drive current, conducting resistance, breakdown voltage, and, by the setting of a deep trench isolation element, external noise can be reduced for the interference of semiconductor device and can avoid the generation of locking (Latch-up) effect of semiconductor device.
Accompanying drawing explanation
Fig. 1 is a schematic perspective view, shows the semiconductor device according to one embodiment of the invention;
Fig. 2 is a generalized section, shows the section situation along line segment A-A in Fig. 1;
Fig. 3,5,8,11,14,18 is a series of schematic top plan view, shows the manufacture method of the semiconductor device according to one embodiment of the invention;
Fig. 4 is a generalized section, is respectively the making situation of the semiconductor device along the line segment B-B in Fig. 3;
Fig. 6 is a generalized section, is respectively the making situation of the semiconductor device along the line segment C-C in Fig. 5;
Fig. 7 is a generalized section, is respectively the making situation of the semiconductor device along the line segment D-D in Fig. 5;
Fig. 9 is a generalized section, is respectively the making situation of the semiconductor device along the line segment E-E in Fig. 8;
Figure 10 is a generalized section, is respectively the making situation of the semiconductor device along the line segment F-F in Fig. 8;
Figure 12 is a generalized section, is respectively the making situation of the semiconductor device along the line segment J-J in Figure 11;
Figure 13 is a generalized section, is respectively the making situation of the semiconductor device along the line segment K-K in Figure 11;
Figure 15 is a generalized section, is respectively the making situation of the semiconductor device along the line segment L-L in Figure 14;
Figure 16 is a generalized section, is respectively the making situation of the semiconductor device along the line segment M-M in Figure 14;
Figure 17 is a generalized section, is respectively the making situation of the semiconductor device along the line segment N-N in Figure 14;
Figure 19 is a generalized section, is respectively the making situation of the semiconductor device along the line segment O-O in Figure 18;
Figure 20 is a generalized section, is respectively the making situation of the semiconductor device along the line segment P-P in Figure 18;
Figure 21 is a schematic perspective view, shows the semiconductor device according to another embodiment of the present invention.
Symbol description:
10 ~ semiconductor device
12 ~ insulating barrier covers semiconductor substrate
14 ~ bulk semiconductor layer
16 ~ bury insulating barrier underground
18 ~ semiconductor layer
20 ~ super-junction structures
22 ~ doped region
24 ~ doped region
26 ~ grid structure
28 ~ doped region
30 ~ doped region
32 ~ well region
34 ~ doped region
102 ~ semiconductor substrate
104 ~ bulk semiconductor layer
106 ~ bury insulating barrier underground
108 ~ bury insulating barrier underground
110 ~ patterned mask layer
112 ~ opening
114 ~ ion implantation technology
115 ~ admixture
116 ~ injection region
118 ~ semiconductor layer
120 ~ patterned mask layer
122 ~ opening
124 ~ ion implantation technology
125 ~ admixture
126 ~ injection region
128 ~ semiconductor layer
129 ~ admixture
130 ~ injection region
132 ~ thermal diffusion process
134,136,138 ~ doped region
140 ~ gate dielectric
142 ~ grid electrode layer
144,146,148 ~ doped region
300 ~ semiconductor device
310 ~ composite mixed district
320 ~ composite mixed district
330 ~ super-junction structures
H1, H2, H3 ~ degree of depth
G ~ grid structure
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and coordinate appended by graphic, be described in detail below.
Please refer to Fig. 1, the one showing foundation one embodiment of the invention has a schematic perspective view of the semiconductor device 10 of lateral super junction structure (Lateralsuper junction structure).
At this, the semiconductor device that semiconductor device 10 is known for inventor and as the use of a comparative example, it illustrates is a metal oxide semiconductcor field effect transistor (MOSFET), to illustrate that semiconductor device 10 that inventor finds reduces problem along with the drive current met with during its size micro, and the enforcement situation of semiconductor device 10 is herein not intended to limit category of the present invention.
As shown in Figure 1, semiconductor device 10 comprises on an insulating barrier and covers semiconductor (Semiconductor on insulator, SOI) substrate 12, it comprises a bulk semiconductor layer (Bulk semiconductor layer) 14 and is sequentially formed at one on bulk semiconductor layer 14 buries insulating barrier (Buried insulating layer) 16 and semi-conductor layer (Semiconductor layer) 18 underground.Bulk semiconductor layer 14 and semiconductor layer 18 can comprise the semi-conducting material as silicon, bury insulating barrier 16 underground and can comprise insulating material as silicon dioxide, then can comprise the admixture of the first conduction type as P-type conduction type in semiconductor layer 18.In semiconductor device 10, be formed with a super-junction structures (Super junction structure) 20 in a part of region of semiconductor layer 18, it comprises adjacent and several doped regions 22 and 24 be laterally crisscross arranged.These doped regions 24 are a part of region of semiconductor layer 18, thus there is the first conductive characteristic being same as semiconductor layer 18, these doped regions 22 are then the doped region that the admixture of the second conduction type (being such as N-type conduction type) comprising the first conduction type in contrast to semiconductor layer 18 is formed, and it can adopt as ion implantation mode and be formed in several parts of semiconductor layer 18.These doped regions 22 are as the use of the drift region (Drift-region) of semiconductor device 10.In addition, on a part of region of semiconductor layer 18, be formed with a grid structure (Gate structure) 26, and in a part of region of the semiconductor layer 18 of the opposite side of grid structure 26, be then formed with two adjacent doped region 28 and 34 and doped regions 30 respectively.Doped region 34 is for being included in a doped region of the first conduction type being same as semiconductor layer 18, and doped region 28 and 30 is the doped region of the second conduction type of the first conduction type comprised in contrast to semiconductor layer 18, using the use as one source pole district/drain region.Grid structure 26 extends semiconductor layer 18 a part of region along Y-direction on Fig. 1 partly covers these doped regions 22 and 24 of super-junction structures 20.In a part of region that doped region 30 is arranged at doped region 22 and 24 and for doped region 22 and 24 institute to be then arranged within a well region 32 around, doped region 28 and 34 and for well region 32 around.This well region 32 is a part of region of the semiconductor layer 18 of contiguous doped region 28 and 34 and it is grid structure 26 part covers.Well region 32 has the admixture of the first conduction type being same as semiconductor layer 18, and contacts the top burying insulating barrier 16 underground bottom it, be arranged at doped region 28 and 34 in well region 32 then for well region 32 institute around.
Please refer to Fig. 2, show the generalized section along line segment A-A in Fig. 1.As shown in Figure 2, based on the use comprising the super-junction structures 20 that several doped regions 22 and 24 of being crisscross arranged are formed, the high voltage operation that this semiconductor device 10 is applicable to as power semiconductor arrangement is applied.
But, due to these doped regions 22 for the several parts of the semiconductor layer 18 of region implement as the technique such as ion implantation and thermal diffusion process formed.Therefore, along with the size micro of semiconductor device 10, the component size as surface area of semiconductor device 10 also micro thereupon, the region therefore for the formation of these doped regions 22 also will micro thereupon.Drive current due to semiconductor device 10 is proportional to the summation of the sectional area of these doped regions 22 being positioned at semiconductor layer 18, and therefore the micro in the region of these doped regions 22 probably will reduce the drive current of semiconductor device 10 and increase the conducting resistance of semiconductor device 10.Therefore, if for maintaining or promote the drive current of semiconductor device 10 and the conducting resistance of maintenance or minimizing semiconductor device 10, then need the surface area increasing region shared by these doped regions 22, this demand is then inconsistent with the size micro situation of semiconductor device 10.
Therefore, the invention provides a kind of semiconductor device and manufacture method thereof, comprise a super-junction structures in it, and this semiconductor device can maintain or improve the drive current of semiconductor device and the conducting resistance of maintenance or reduction semiconductor device along with component size micro.
Please refer to a series of schematic diagrames of Fig. 3-20, to show the manufacture method of the semiconductor device according to one embodiment of the invention, wherein Fig. 3,5,8,11,14,18 is a schematic top plan view, Fig. 4, Fig. 6-7, Fig. 9-10, Figure 12-13, Figure 19-20 etc. then respectively illustrate the generalized section along line segment specific in Fig. 3, Fig. 5, Fig. 8, Figure 11, Figure 14, Figure 18, so as to being shown in the making situation in an interstage of the manufacture method of semiconductor device.
Please refer to Fig. 3-4, first provide semiconductor substrate 102, and Fig. 3 shows the schematic top plan view of this semiconductor substrate 102, Fig. 4 then shows the generalized section along the line segment B-B in Fig. 1.
As shown in Figure 4, semiconductor substrate 102 is such as that an insulating barrier covers semiconductor (Semiconductor oninsulator, SOI) substrate, it comprises a bulk semiconductor layer 104 and is sequentially formed at one on bulk semiconductor layer 104 buries insulating barrier (Buried insulating layer) 106 and semi-conductor layer 108 underground.Bulk semiconductor layer 104 and semiconductor layer 108 can comprise the semi-conducting material as silicon, bury insulating barrier 106 underground and can comprise insulating material as silicon dioxide, in semiconductor layer 108, then can comprise the admixture of the first conduction type as P-type conduction type or N-type conduction type.
Please refer to Fig. 5-7, in semiconductor layer 108, then form several injection regions 116 that are parallel and that separate.Fig. 5 shows a schematic top plan view of the semiconductor substrate 102 being formed with several injection region 116, and Fig. 6-7 then respectively illustrates the generalized section along the line segment C-C in Fig. 5 and line segment D-D.
As seen in figs. 5-6, first a patterned mask layer 110 is formed on semiconductor layer 108, and in this patterned mask layer 110, being formed with several openings 112 that are parallel and that separate, these openings 112 extend along the X-direction on Fig. 5 and expose a part of region of semiconductor layer 108 respectively.Patterned mask layer 110 can comprise the mask material as resist, therefore these openings 112 are by the such as technique (not shown) such as micro-shadow and etching and the use of a suitable light shield (not shown) of arranging in pairs or groups and being formed within patterned mask layer 110.Then, patterned mask layer 110 is adopted to inject mask to implement an ion implantation technology 114 as one, with in the admixture 115 injecting second conduction type with the first conduction type in contrast to semiconductor layer 108 a part of region of semiconductor layer 108 that most these openings 112 expose, such as, it is depth H 1 part shown in Fig. 6.This depth H 1 is such as 1/2 part of semiconductor layer 108 thickness, and can adjust according to institute's implementing process, but not is limited with above-mentioned enforcement situation.In addition; as shown in Figure 7; then carrying on as before and be subject to the protection of patterned mask layer 110 in a part of region being adjacent to the semiconductor layer 108 of injection region 116, thus can not be subject to the injection of the admixture 115 of the second conduction type in ion implantation technology 114, thus still have the first original conduction type.
Please refer to Fig. 8-10, on semiconductor layer 108, then form semi-conductor layer 118 and in this semiconductor layer 118, form several injection regions 126 that are parallel and that separate.Fig. 8 shows a schematic top plan view of the semiconductor layer 118 being formed with several injection region 126, and Fig. 9-10 then respectively illustrates the generalized section along line segment E-E in Fig. 8 and line segment F-F.
As Figure 8-9, after removing in Fig. 5-7 patterned mask layer 110 be formed on semiconductor layer 108, then adopt if a method of epitaxial growth is to form semi-conductor layer 118 on the semiconductor layer 108 of semiconductor substrate 102.At this, the conduction type of the thickness of semiconductor layer 118, material and institute's dopant-bearing can be same as the conduction type of the thickness of semiconductor layer 108, material and institute's dopant-bearing, such as, be silicon material and the first conduction type.Then on semiconductor layer 118, form a patterned mask layer 120, and be formed with several openings 122 that are parallel and that separate in this patterned mask layer 120, these openings 122 extend along the X-direction of Fig. 8 and expose a part of region of semiconductor layer 118 respectively.Patterned mask layer 120 can comprise the mask material as resist, therefore these openings 122 are by the such as technique (not shown) such as micro-shadow and etching and the use of a suitable light shield (not shown) of arranging in pairs or groups and being formed.In addition, light shield for the formation of opening 112 also can be adopted to form these openings 122, aim at it on the injection region 116 that a part of region of the semiconductor layer 118 that each opening 122 like this exposes is positioned at semiconductor layer 108 substantially.Then, adopt patterned mask layer 120 to inject mask as one and implement an ion implantation technology 124, in a part of region of the semiconductor layer 118 exposed with the most each opening 122 of admixture 125 of the second conduction type injecting the first conduction type had in contrast to semiconductor layer 118, such as, it is depth H 2 part shown in Fig. 9.This depth H 2 is such as 1/2 part of semiconductor layer 118 thickness, and slightly can adjust according to institute's implementing process, but not is limited with above-mentioned enforcement situation.In addition; as shown in Figure 10; then carrying on as before and be subject to the protection of patterned mask layer 120 in a part of region being adjacent to the semiconductor layer 108 of injection region 126, thus can not be subject to the injection of the admixture 125 of the second conduction type in ion implantation technology 124, thus still have the first original conduction type.
Please refer to Figure 11-13, after removal patterned mask layer 120, on semiconductor layer 118, then form semi-conductor layer 128 and in this semiconductor layer 128, form several injection regions 130 that are parallel and that separate.Figure 11 shows a schematic top plan view of the semiconductor layer 128 being formed with several injection region 130, and Figure 12-13 then respectively illustrates the generalized section along the line segment J-J in Figure 10 and line segment K-K.
As depicted in figs. 11-12, can adopt and be same as if the formation method of the semiconductor layer 118 in Fig. 8-10 and injection region 126 is to form this semiconductor layer 128 and to form the several injection regions 130 including admixture 129 in it, therefore again not describe it in this and make situation.And the enforcement situation of the semiconductor layer 128 formed and several injection region 130 is also same as the enforcement situation of semiconductor layer 118 and injection region 126.As shown in figure 12, injection region 130 is positioned on injection region 126 substantially also to be aimed at it, and the admixture 129 being formed at the second conduction type of the first conduction type in semiconductor layer 128 is positioned at depth H 3 part in a part of region of the semiconductor layer 128 of injection region 130.This depth H 3 is such as 1/2 part of semiconductor layer 128 thickness, and slightly can adjust according to institute's implementing process, but not is limited with above-mentioned enforcement situation.As shown in figure 13, then injection region 130 is not formed with in the several parts being adjacent to the semiconductor layer 128 of injection region 130.
Then, a thermal diffusion process 132 is implemented for structure as figs 11-13, a such as tempering process, a doped region 134,136 and 138 is become, situation as shown in figures 14-17 to be spread respectively by the admixture 115,125 and 129 in the injection region 116,126,130 in semiconductor layer 108,118 and 128 respectively.
Please refer to Figure 14-17, after thermal diffusion process 132 is implemented, the admixture 115,125 and 129 being originally positioned at the injection region 116,126,130 of semiconductor layer 108,118 and 128 just spreads respectively and becomes a doped region 134,136 and 138, and it has the second conduction type of the first conduction type in contrast to semiconductor layer 108,118 and 128.
As shown in figure 14, show semiconductor layer 128 and form a schematic top plan view of several doped regions 138 in the inner, Figure 15-17 then respectively illustrates the generalized section along the line segment L-L in Figure 14, line segment M-M and line segment N-N.
As shown in figure 14, from overlooking sight, doped region 138,136,134 is a region of the cardinal principle strip (Strip-like) extended along the X-direction of Figure 14.In addition, as shown in Figure 15,17, the doped region 134,136 and 138 laid respectively in semiconductor layer 108,118 and 128 is stacked in from lower to upper bury underground on insulating barrier 106 and have a profile of substantially class ellipse (Oval-like) respectively, and insulating barrier 106 is buried in doped region 134 contact underground, doped region 136 contact diffusion zone 134 and 138, and contact doping district, doped region 138 136.As shown in figure 16, the semiconductor layer in the region between adjacent doped region 134,136,138 108,118 and 128 is not formed with these doped regions 134,136 and 138.
Please refer to Figure 18-20, then upper formation one grid structure G in semiconductor layer 128, and form a doped region 146 and 148 respectively in a part of region of semiconductor layer 128 in the side of grid structure G, and form a doped region 144 in a part of region of semiconductor layer 128 in the opposite side of grid structure G.Figure 18 is a schematic top plan view, and Figure 19-20 then respectively illustrates the generalized section along the line segment O-O in Figure 18 and line segment P-P.
As shown in figure 18, grid structure G and doped region 144,146 and 148 be formed at respectively perpendicular to the Y-direction of X-direction extends on Figure 18 on semiconductor layer 128 with within.Grid structure G part covers a part of region of these doped regions 138 and contiguous semiconductor layer 128 thereof, and doped region 146 and 148 is arranged in a part of region of the semiconductor layer 128 of the side of adjacent gate structures G, and doped region 144 is formed in a part of region of the semiconductor layer 128 of the opposite side of grid structure G, and be arranged in a part of region of doped region 138, as shown in figure 19.In addition, as shown in Figure 19-20, grid structure G then comprises and is sequentially arranged at gate dielectric on semiconductor layer 128 140 and grid electrode layer 142.
At this, grid structure G inner grid dielectric layer 140 as shown in Figure 18-20 and grid electrode layer 142 and doped region 144, the making of 146 and 148 can adopt conventional high voltage metal-oxide semiconductor (MOS) (High voltage MOS) technique to be formed, and gate dielectric 140 and grid electrode layer 142 can adopt the material of conventional high voltage metal oxide semiconductcor field effect transistor (MOSFET), therefore at this in detail its making and application material thereof are not described in detail, and doped region 144, the admixture of the second conduction type of the first conduction type in contrast to semiconductor layer 128 can be comprised in 146 and can be used as the use of source/drain region, doped region 148 then can comprise the admixture of the first conduction type being same as semiconductor layer 128.
So far, just substantially complete the making of the semiconductor device 300 according to one embodiment of the invention, it is the metal oxide semiconductor transistor (MOS transistor) comprising a super-junction structures 330 to technique.The composite mixed district 310 that this super-junction structures 330 includes the second conduction type of the separation combined by several doped region 138,136,134 and the composite mixed district 320 of several first conduction types combined by a part of region of its contiguous semiconductor layer 128,118,108.And these composite mixed districts 310 of the second conduction type of the several separations combined by several doped region 138,136,134 can be used as the use of a drift region (Shift region) of semiconductor device 300, semiconductor device 300 is thus made to have the electrical performance can bearing high breakdown voltage.
In an embodiment, when the semiconductor layer 108,118,128 in semiconductor device 300 shown in 18-21 figure has the first conduction type as P type, the admixture of the second then included in relevant doped region conduction type is N-type admixture, and therefore formed semiconductor device 300 is a P-type mos transistor (PMOS).On the contrary, in another embodiment, when the semiconductor layer 108,118,128 shown in 18-21 figure has the first conduction type as N-type, the admixture of the second then included in relevant doped region conduction type is P type admixture, and therefore formed MOS device 300 is a N-type metal oxide semiconductor transistor (NMOS).
Compared to the semiconductor device 10 shown in Fig. 1-2, in semiconductor device 300 as shown in figs. 18-21, then can according to the drive current of semiconductor device 300, conducting resistance, the element design demands such as breakdown voltage and moderate reduction or increase the setting that one or more is same as the middle semiconductor layer as semiconductor layer 118, and the enforcement situation of the semiconductor layer (not shown) of setting up and interior doped region thereof can be identical with the relevant enforcement situation of semiconductor layer 118, and the enforcement being same as the relative production situation about semiconductor layer 118 and interior doped region 126 thereof shown in Fig. 8-10 and the thermal diffusion process 132 shown in Figure 11-13 can be adopted to be formed.So, by semiconductor layer 118 and form setting up of doped region 136 in the inner, under the surface area prerequisite in the composite mixed district 310 of several second conduction types just can separated mutually in the super-junction structures 310 do not increased in semiconductor device 300, by increasing the rete of overall semiconductor floor in it and extra increase the doped region 136 that formed and increase this sectional area of composite mixed district 310 in overall semiconductor floor, thus the drive current of semiconductor device 300 can be increased and reduce the conducting resistance of semiconductor device 300.In addition, also the deep trench isolation element (Deep trench isolation does not show) around this semiconductor device 300 can be provided with in a part of region of the semiconductor layer (being such as semiconductor layer 108,118 and 128) in the outside of semiconductor device 300.This deep trench isolation element is by arranging and penetrating a part of region of semiconductor layer 128,118,108 and the insulating material that insulating barrier 106 is buried in contact underground formed, such as, be the insulating material of silicon dioxide.By the setting of this deep trench isolation element (not shown), external noise can be reduced for the interference of semiconductor device 300 and can avoid the generation of locking (Latch-up) effect of semiconductor device 300.
Although the present invention discloses as above with preferred embodiment; so itself and be not used to limit the present invention, anyly have the knack of this those skilled in the art, without departing from the spirit and scope of the present invention; when doing to change and retouching, therefore protection scope of the present invention is when being as the criterion of defining depending on claims.
Claims (22)
1. a semiconductor device, is characterized in that, described semiconductor device comprises:
Mutually stacking multiple semiconductor layers, wherein said multiple semiconductor layer has one first conduction type;
Multiple composite mixed district, parallel and be arranged in a part of region of described multiple semiconductor layer separatedly along a first direction, wherein said multiple composite mixed district has one second conduction type in contrast to this first conduction type;
One grid structure, is arranged on a part of region of described multiple semiconductor layer along a second direction, and wherein this grid structure covers a part of region in described multiple composite mixed district;
One first doped region, be arranged at the superiors in described multiple semiconductor layer along this second direction and one first side of this grid structure contiguous, wherein this first doped region has this second conduction type; And
One second doped region, be arranged at along this second direction relative in the superiors in described multiple semiconductor layer of one second side of this grid structure first side and contiguous described multiple composite mixed district, wherein this second doped region has this second conduction type.
2. semiconductor device as claimed in claim 1, it is characterized in that, described semiconductor device also comprises:
One bulk semiconductor layer; And
One buries insulating barrier underground, is positioned on this bulk semiconductor layer, and wherein mutually stacking described multiple semiconductor layer is arranged at this to bury underground on insulating barrier.
3. semiconductor device as claimed in claim 1, it is characterized in that, this first conduction type is P type and this second conduction type is N-type.
4. semiconductor device as claimed in claim 1, it is characterized in that, this first conduction type is N-type and this second conduction type is P type.
5. semiconductor device as claimed in claim 1, it is characterized in that, described multiple composite mixed district comprises a doped region that is stacking and that be arranged in one of described multiple semiconductor layer respectively from top to bottom.
6. semiconductor device as claimed in claim 5, it is characterized in that, this doped region has a section profile of general oval.
7. semiconductor device as claimed in claim 1, it is characterized in that, described multiple semiconductor layer is an epitaxial semiconductor layer.
8. semiconductor device as claimed in claim 1, it is characterized in that, this first direction is perpendicular to this second direction.
9. semiconductor device as claimed in claim 1, it is characterized in that, a part of region of described multiple semiconductor layer that described multiple composite mixed district is adjacent defines a super-junction structures.
10. a manufacture method for semiconductor device, is characterized in that, described manufacture method comprises the following steps:
(a). provide on an insulating barrier and cover semiconductor substrate, comprise a bulk semiconductor layer, be positioned at one on this bulk semiconductor layer and bury insulating barrier underground and be positioned at this and bury 1 on insulating barrier first semiconductor layer underground, this first semiconductor layer has one first conduction type;
(b). form parallel in this first semiconductor layer of multiple first injection region respectively and in the several parts separated, wherein said multiple first injection region has one second conduction type in contrast to this first conduction type along a first direction;
(c). form one second semiconductor layer on this first semiconductor layer; And
(d). along this first direction to form parallel in this second semiconductor layer of multiple second injection region respectively and in the several parts separated, wherein said multiple second injection region to lay respectively on one of described multiple first injection region and has this second conduction type;
(e). implement a thermal diffusion process, respectively described multiple first injection region in this first semiconductor layer and described multiple second injection regions in this second semiconductor layer are diffused into one first doped region and one second doped region respectively; And
(f). formed a grid structure on a part of region of this second semiconductor layer, one the 3rd doped region in a part of region of this second semiconductor layer of one first side of this grid structure and one the 4th doped region in a part of region of this second semiconductor layer of one second side of this first side relative to this grid structure, wherein this grid structure extends on this second semiconductor layer along a second direction, and the 3rd doped region and the 4th doped region have this second conduction type.
The manufacture method of 11. semiconductor devices as claimed in claim 10, it is characterized in that, this first conduction type is P type and this second conduction type is N-type.
The manufacture method of 12. semiconductor devices as claimed in claim 10, it is characterized in that, this first conduction type is N-type and this second conduction type is P type.
The manufacture method of 13. semiconductor devices as claimed in claim 10, it is characterized in that, be formed at this first doped region with parallel in this second semiconductor layer and in the several parts separated of this first semiconductor layer and this second doped region defines multiple composite mixed district that is stacking from the bottom to top and that be arranged in this first semiconductor layer and this second semiconductor layer.
The manufacture method of 14. semiconductor devices as claimed in claim 13, is characterized in that, a part of region of this first semiconductor layer that described multiple composite mixed district is adjacent and this second semiconductor layer defines a super-junction structures.
The manufacture method of 15. semiconductor devices as claimed in claim 10, is characterized in that, this doped region in this first semiconductor layer and this second semiconductor layer has a section profile of general oval.
The manufacture method of 16. semiconductor devices as claimed in claim 10, it is characterized in that, this second semiconductor layer formed by epitaxy method.
The manufacture method of 17. semiconductor devices as claimed in claim 10, it is characterized in that, this first direction is perpendicular to this second direction.
The manufacture method of 18. semiconductor devices as claimed in claim 10, before this step (e) is implemented, is characterized in that, also comprise execution the following step:
(g). form one the 3rd semiconductor layer on this second semiconductor layer; And
(h). along this first direction to form parallel in the 3rd semiconductor of multiple 3rd injection region respectively and in the several parts separated.
The manufacture method of 19. semiconductor devices as claimed in claim 18, this step (e) and (f) comprising:
(e). implement a thermal diffusion process, respectively described multiple 3rd injection regions in described multiple first injection regions in this first semiconductor layer, described multiple second injection region in this second semiconductor layer and the 3rd semiconductor layer are diffused into one first doped region, one second doped region and one the 3rd doped region;
(f). formed a grid structure on a part of region of the 3rd semiconductor layer, one the 4th doped region in a part of region of the 3rd semiconductor layer of one first side of this grid structure and one the 5th doped region in a part of region of the 3rd semiconductor layer of one second side of this first side relative to this grid structure, wherein this grid structure extends on the 3rd semiconductor layer along a second direction, and the 4th doped region and the 5th doped region have this second conduction type.
The manufacture method of 20. semiconductor devices as claimed in claim 19, it is characterized in that, be formed at parallel in this first semiconductor layer, this second semiconductor layer and the 3rd semiconductor layer and this first doped region in the several parts separated, this second doped region and the 3rd doped region define multiple composite mixed district that is stacking from the bottom to top and that be arranged in this first semiconductor layer and this second semiconductor layer.
The manufacture method of 21. semiconductor devices as claimed in claim 18, it is characterized in that, the 3rd semiconductor layer formed by epitaxy method.
The manufacture method of 22. semiconductor devices as claimed in claim 18, it is characterized in that, this first doped region in this first semiconductor layer, this second semiconductor layer and the 3rd semiconductor layer, this second doped region and the 3rd doped region have a section profile of general oval.
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