CN201570500U - P-type super-junction lateral double-diffused semiconductor metal oxide transistor - Google Patents
P-type super-junction lateral double-diffused semiconductor metal oxide transistor Download PDFInfo
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- CN201570500U CN201570500U CN2009202834623U CN200920283462U CN201570500U CN 201570500 U CN201570500 U CN 201570500U CN 2009202834623 U CN2009202834623 U CN 2009202834623U CN 200920283462 U CN200920283462 U CN 200920283462U CN 201570500 U CN201570500 U CN 201570500U
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Abstract
The utility model relates to a P-type super-junction lateral double-diffused semiconductor metal oxide transistor which comprises a N-type substrate that is provided with a super-junction structure and a N-type body area; the super-junction structure is formed by a P-type area and an N-type area which are distributed at intervals along the directions of connecting source drain regions; a P-type source area, an N-type body contact area and a gate oxide are arranged above the N-type body area; a P-type drain region is arranged above the super-junction structure; a first type field oxide is arranged above the super-junction structure and positioned at the area outside the P-type drain region; polysilicon gate is arranged above the gate oxide; a second type field oxide is arranged above the P-type source area, the N-type body contact area, the P-type drain region, the polysilicon gate and the first type field oxide; the P-type source area, the P-type drain region, the N-type body contact area and the polysilicon gate are connected with metal leads passing through the second type field oxide; and the P-type super-junction lateral double-diffused semiconductor metal oxide transistor is characterized in that the N-type substrate is internally provided with a P-type buffer area which is positioned under the N-type area in the super-junction structure and connected with the bottom of the N-type area in the super-junction structure.
Description
Technical field
The utility model relates to the power semiconductor field, is the structure that is applicable to the super-junction laterally double diffused metal oxide semiconductor of high-voltage applications about a kind of.
Background technology
Along with energy-conservation demand strengthens day by day, the performance of power integrated circuit product more and more receives publicity, and wherein the power loss of circuit is undoubtedly one of main performance index.The factor of decision power integrated circuit power loss size except the circuit structure of power integrated circuit own, design, the manufacturing process that circuit adopted, the power device performance that is adopted is the key of power integrated circuit power loss size.
At present, the manufacturing process according to power integrated circuit mainly is divided into based on body silicon, extension and silicon-on-insulator (SOI).Wherein, bulk silicon technological is because there is more defective in silicon face layer, so the large scale integrated circuit mainly adopts this technology in early days; Silicon-on-insulator (SOI) technology is owing to exist insulating barrier that surface silicon and substrate silicon layer are isolated, insulating barrier is generally silica in addition, vertical puncture voltage of the device of this technology of employing is higher like this, simultaneously substrate current there is good restraining, help reducing the power consumption of device, yet, cause the heat dissipation problem of power integrated circuit more serious, and the disk cost of silicon-on-insulator process is higher because the heat-sinking capability of silicon oxide layer is 1/100 of a silicon layer; Epitaxy technique has solved the blemish problem that bulk silicon technological exists well, has heat dispersion preferably simultaneously, so still wide based on the power integrated circuit prospect of epitaxy technique.
Integrated power device mainly contains landscape insulation bar double-pole-type transistor and laterally double diffused metal oxide semiconductor in the power integrated circuit.Although the current driving ability of landscape insulation bar double-pole-type transistor is more intense, yet be restricted, so still selection relatively preferably of laterally double diffused metal oxide semiconductor in the power integrated circuit of upper frequency because the existence of shutoff hangover electric current makes the power integrated circuit speed of using landscape insulation bar double-pole-type transistor improve.
In laterally double diffused metal oxide semiconductor optimization in Properties process, the puncture voltage that improves device is the problem of a pair of contradiction with the conducting resistance that reduces device all the time.Depend on the lower and long drift region of doping content because the puncture voltage of device improves, and try one's best height and length of the drift region doping content that lowers the requirement of conducting resistance is short as far as possible.So in actual design process, often adopt trading off of the two to reach the optimization of device performance.The laterally double diffused metal oxide semiconductor of super-junction structure has been proposed for this reason recently, the proposition of this structure mainly is the drift region of adopting super-junction structure, be implemented in the puncture voltage that does not reduce device when improving the drift region doping content, even the raising device electric breakdown strength, thereby reach optimization in Properties.Yet, present super-junction laterally double diffused metal oxide semiconductor is owing to exist the influence of substrate-assisted depletion factor, performance also has the leeway of improving, and the utility model is exactly the improvement structure super-junction laterally double diffused metal oxide semiconductor that proposes at this problem.
Summary of the invention
The utility model provides a kind of puncture voltage that can effectively improve the laterally double diffused metal oxide semiconductor device, and can reduce the P type super-junction laterally double diffused metal oxide semiconductor of laterally double diffused metal oxide semiconductor break-over of device resistance.
The utility model adopts following technical scheme:
A kind of P type super-junction laterally double diffused metal oxide semiconductor, comprise: N type substrate, on N type substrate, be provided with super-junction structure and N type tagma, super-junction structure is made of p type island region and the N type district that connection source-drain area direction distributes alternately, above N type tagma, be provided with P type source region, N type body contact zone and gate oxide, above super-junction structure, be provided with P type drain region, above super-junction structure, and the zone that is positioned at beyond the P type drain region is provided with the first type field oxide, above gate oxide, be provided with polysilicon gate, in P type source region, N type body contact zone, P type drain region, polysilicon gate and first type field oxide top are provided with the second type field oxide, P type source region, P type drain region, N type body contact zone and polysilicon gate all are connected to the metal lead wire of the break-through second type field oxide, it is characterized in that in N type substrate, being provided with P type buffering area, P type buffering area is arranged in the below in super-junction structure N type district, and with super-junction structure in N type district bottom connection.
Compared with prior art, the utlity model has following advantage:
(1) the P type super-junction laterally double diffused metal oxide semiconductor in the utility model has adopted new construction, that is: in super-junction structure, added P type buffering area 15 below the N type district 12 and between the N type substrate 1, can effectively eliminate the adverse effect that the substrate-assisted depletion effect between the p type island region 11 brings in 1 pair of super-junction structure of N type substrate of conventional P type super-junction laterally double diffused metal oxide semiconductor with respect to conventional P type super-junction laterally double diffused metal oxide semiconductor (Fig. 4), thereby can further improve device electric breakdown strength, reduce break-over of device resistance, finally reach the raising device performance.
(2) the P type super-junction laterally double diffused metal oxide semiconductor in the utility model adopts the P type buffering area 15 that separates, adopt whole P type buffering area 16 with respect to other P type super-junction laterally double diffused metal oxide semiconductors (Fig. 5), whole P type buffering area 16 can only realize that p type island region 11 is isolated in N type substrate 1 and the super-junction structure, on certain Cheng Du, reduced substrate-assisted depletion effect, yet introduced the assisted depletion effect in N type district 12 and whole P type buffering area 16 (Fig. 5) in the super-junction structure, this is that we are undesirable.The utility model structure has realized, the space of three directions except super knot superficial layer exhausts, that is: in the surperficial super-junction structure in N type district 12 and the super-junction structure two sides between the p type island region 11 exhaust, exhausting between 12 bottoms, N type district and its P type buffering area 15 tops, below in the super-junction structure, exhausting between p type island region 11 bottoms and N type substrate 1 top in the super-junction structure, the both sides of P type buffering area 15 and bottom all exhaust with N type substrate 1, like this exhaust the adverse effect that structure has effectively been eliminated assisted depletion effect entirely, make full use of super-junction structure, be of value to the raising device electric breakdown strength, simultaneously under the prerequisite of same breakdown voltage, be of value to the conducting resistance that reduces device, reduce chip area.
Description of drawings
Fig. 1 is the 3 D stereo profile, illustrates the three-dimensional cross-section structure of the utility model P type super-junction laterally double diffused metal oxide semiconductor embodiment.
Fig. 2 is a profile, illustrates the device profile structure of AA section in the utility model P type super-junction laterally double diffused metal oxide semiconductor 3 D stereo profile 1.
Fig. 3 is a profile, illustrates the device profile structure of BB section in the utility model P type super-junction laterally double diffused metal oxide semiconductor 3 D stereo profile 1.
Fig. 4 is the 3 D stereo profile, illustrates the three-dimensional cross-section structure of conventional P type super-junction laterally double diffused metal oxide semiconductor embodiment.
Fig. 5 is the 3 D stereo profile, illustrates to have the three-dimensional cross-section structure of integral body towards the P type super-junction laterally double diffused metal oxide semiconductor embodiment of plot structure.
Fig. 6 is the device analog simulation result, illustrates the ON state current ability size of three kinds of structure P type super-junction laterally double diffused metal oxide semiconductors, and more the low current driving force is stronger for visible the utility model break-over of device resistance.
Fig. 7 is the device analog simulation result, illustrates the OFF state puncture voltage size of three kinds of structure P type super-junction laterally double diffused metal oxide semiconductors, and the puncture voltage of visible the utility model structure is higher.
Embodiment
Below in conjunction with accompanying drawing 1, the utility model is elaborated, a kind of P type super-junction laterally double diffused metal oxide semiconductor, comprise: N type substrate 1, on N type substrate 1, be provided with super-junction structure and N type tagma 2, super-junction structure is made of p type island region 11 and the N type district 12 that connection source-drain area direction distributes alternately, above N type tagma 2, be provided with P type source region 4, N type body contact zone 5 and gate oxide 3, above super-junction structure, be provided with P type drain region 14, above super-junction structure, and the zone that is positioned at beyond the P type drain region 14 is provided with the first type field oxide 10, above gate oxide 3, be provided with polysilicon gate 6, in P type source region 4, N type body contact zone 5, P type drain region 14, polysilicon gate 6 and the first type field oxide, 10 tops are provided with the second type field oxide 8, P type source region 4, P type drain region 14, N type body contact zone 5 and polysilicon gate 6 all are connected to the metal lead wire of the break-through second type field oxide 8, it is characterized in that in N type substrate 1, being provided with P type buffering area 15, P type buffering area 15 is arranged in the below in super-junction structure N type district 12, and with super-junction structure in N type district 12 bottom connections.
The width in N type district 12 equates with the width of corresponding P type buffering area 15 in the described super-junction structure, also can be not exclusively equal.
Described P type buffering area 15 can form by the mode that energetic ion injects with buried layer.
Described P type buffering area 15 can inject by ion, and the mode of carrying out surperficial extension then forms.
Described P type buffering area 15 bottoms not necessarily will be positioned at same horizontal plane with 2 bottoms, N type tagma, need and decide according to actual design.
In the described super-junction structure in p type island region 11 and the super-junction structure N type district 12 doping contents suitable, need and decide according to actual design.
In the described super-junction structure in p type island region 11 and the super-junction structure N type district 12 width suitable, need and decide according to actual design.
Described polysilicon gate 6 can extend to the first type field oxide, 10 tops, forms the crystal silicon field plate, further reduces surface field, improves device electric breakdown strength.
Described drain terminal metal electrode 13 can extend to the first type field oxide, 10 tops, forms drain terminal metal field plate, further reduces surface field, improves device electric breakdown strength.
The utility model adopts following method to prepare:
The first step, get N type substrate, it is carried out prerinse, preparation P type buffering area on N type substrate, growing P-type epitaxial loayer then, logical ion injects and elevated temperature heat diffuses to form N type tagma, on P type epitaxial loayer, make N type district in the width super-junction structure suitable directly over the P type buffering area, form p type island region in the super-junction structure simultaneously, then carry out the growth of the first type field oxide again with P type buffering area, carrying out an oxygen then injects, the adjustment channel threshold voltage is injected, growth of gate oxide layer, and the deposit etch polysilicon forms polysilicon gate and polysilicon field plate, the source is leaked to inject and is formed P type source region, P type drain region and N type body contact zone, the deposit second type field oxide then.
Second step: the etching second type oxide layer, form the metal electrode fairlead of P type source region, P type drain region, N type body contact zone and polysilicon gate, deposited metal, etching sheet metal forms the P type source region of P type super-junction laterally double diffused metal oxide semiconductor and extraction electrode, P type drain region extraction electrode and the polysilicon gate extraction electrode of N type body contact zone, carries out Passivation Treatment at last.
Claims (2)
1. P type super-junction laterally double diffused metal oxide semiconductor, comprise: N type substrate (1), on N type substrate (1), be provided with super-junction structure and N type tagma (2), super-junction structure is by connecting p type island region (11) and N type district (12) formation that the source-drain area direction distributes alternately, be provided with P type source region (4) in top, N type tagma (2), N type body contact zone (5) and gate oxide (3), above super-junction structure, be provided with P type drain region (14), above super-junction structure, and be positioned at zone in addition, P type drain region (14) and be provided with the first type field oxide (10), be provided with polysilicon gate (6) in gate oxide (3) top, in P type source region (4), N type body contact zone (5), P type drain region (14), polysilicon gate (6) and the first type field oxide (10) top are provided with the second type field oxide (8), P type source region (4), P type drain region (14), N type body contact zone (5) and polysilicon gate (6) all are connected to the metal lead wire of the break-through second type field oxide (8), it is characterized in that in N type substrate (1), being provided with P type buffering area (15), P type buffering area (15) is arranged in the below in super-junction structure N type district (12), and with super-junction structure in N type district (12) bottom connection.
2. P type super-junction laterally double diffused metal oxide semiconductor according to claim 1, the width that it is characterized in that N type district (12) in the super-junction structure equates with the width of corresponding P type buffering area (15).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009202834623U CN201570500U (en) | 2009-12-18 | 2009-12-18 | P-type super-junction lateral double-diffused semiconductor metal oxide transistor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2009202834623U CN201570500U (en) | 2009-12-18 | 2009-12-18 | P-type super-junction lateral double-diffused semiconductor metal oxide transistor |
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| CN201570500U true CN201570500U (en) | 2010-09-01 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103515443A (en) * | 2013-09-16 | 2014-01-15 | 电子科技大学 | Super-junction power device and manufacturing method thereof |
| CN105633153A (en) * | 2014-11-06 | 2016-06-01 | 比亚迪股份有限公司 | Super junction semiconductor device and formation method thereof |
-
2009
- 2009-12-18 CN CN2009202834623U patent/CN201570500U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103515443A (en) * | 2013-09-16 | 2014-01-15 | 电子科技大学 | Super-junction power device and manufacturing method thereof |
| CN103515443B (en) * | 2013-09-16 | 2016-03-02 | 电子科技大学 | A kind of super junction power device and manufacture method thereof |
| CN105633153A (en) * | 2014-11-06 | 2016-06-01 | 比亚迪股份有限公司 | Super junction semiconductor device and formation method thereof |
| CN105633153B (en) * | 2014-11-06 | 2019-01-11 | 比亚迪股份有限公司 | Super junction-semiconductor device and forming method thereof |
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| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20100901 Effective date of abandoning: 20091218 |