CN103515443A - Super-junction power device and manufacturing method thereof - Google Patents
Super-junction power device and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 150
- 238000005516 engineering process Methods 0.000 claims abstract description 12
- 230000003647 oxidation Effects 0.000 claims abstract description 7
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 19
- 238000002513 implantation Methods 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 16
- 239000012535 impurity Substances 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 238000001259 photo etching Methods 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000001459 lithography Methods 0.000 claims description 3
- 238000009825 accumulation Methods 0.000 abstract description 4
- 210000000746 body region Anatomy 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 5
- 229910052698 phosphorus Inorganic materials 0.000 description 5
- 239000011574 phosphorus Substances 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- 238000002347 injection Methods 0.000 description 3
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- 230000009286 beneficial effect Effects 0.000 description 2
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- 230000004308 accommodation Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
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- 230000000903 blocking effect Effects 0.000 description 1
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- 239000013078 crystal Substances 0.000 description 1
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Abstract
The invention relates to technologies of power semiconductor devices, in particular to a transverse power device of a super junction structure and a manufacturing method of the transverse power device. The super-junction power device is characterized in that a second conductive type semiconductor drift region 4 and a first conductive type semiconductor body region 9 are provided with grooves, a thick oxidation layer 12 is arranged on the upper surface of the second conductive type semiconductor drift region 4 in a covering mode, a thin gate oxidation layer 13 is arranged on the upper surface of the first conductive type semiconductor body region 9 in a covering mode, and a gate electrode 2 is arranged on the upper surface of the thick oxidation layer 12 and the upper surface of the thin gate oxidation layer 13 in a covering mode. The super-junction power device has the advantages that the area of a channel of an accumulation layer of the surface of the drift region 4 is increased so that lower forward on-resistance can be achieved. The super-junction power device is particularly suitable for transverse power devices of the super junction structure.
Description
Technical field
The present invention relates to power semiconductor technology, relate to specifically lateral power and the manufacture method thereof of a kind of super knot (Super Junction) structure.
Background technology
Power semiconductor is widely used in the fields such as DC-DC converter, DC-AC converter, relay, motor driving.Power metal-oxide-semiconductor field effect transistor (MOSFET) is compared with bipolar transistor, there is the advantages such as switching speed is fast, loss is little, input impedance is high, driving power is little, especially power MOSFET has negative temperature coefficient under large electric current, the second breakdown problem that there is no bipolar transistor, safety operation area is large, therefore range of application is wider.
But conventional power MOSFET also has its born shortcoming, conducting resistance is with withstand voltage growth (R
on∝ BV
2.5) cause the sharply increase of power consumption.This " silicon limit (silicon limit) " broken in the appearance that surpasses the charge balance class device that knot (Superjunction) VDMOS is representative of take, improved conducting resistance and withstand voltage between restricting relation (R
on∝ BV
1.3), can realize low on-state power consumption and high blocking voltage simultaneously, therefore in various high energy efficiency occasions, obtain application rapidly, market prospects are very extensive.Basic super-junction structure is p post and n post alternately, and the effective prerequisite of this structure is that p, n post strictly meet charge balance.At device during in off state, under reverse biased, interaction due to transverse electric field and longitudinal electric field, p post district and n post district will exhaust completely, in depletion region, longitudinal electric field distributes and to be tending towards evenly, thereby puncture voltage only depends on the thickness of Withstand voltage layer in theory, irrelevant with doping content, Withstand voltage layer doping content can improve an order of magnitude nearly, thereby has effectively reduced the conducting resistance of device.
In power integrated circuit, in order to realize the integrated of power MOSFET and low-voltage circuit, MOSFET often adopts horizontal double diffusion structure, i.e. LDMOS(lateral double-diffused MOS) structure.For the conducting resistance of LDMOS, people introduce super-junction structure the drift region of LDMOS.But the conductive region of LDMOS is positioned at the surface of device, is subject to the restriction of surface area, the overall width of its conductive channel is limited, and this becomes a restriction of the conduction resistance of the super junction type LDMOS of further reduction.
Summary of the invention
Technical problem to be solved by this invention, is exactly for the problems referred to above, proposes a kind of super knot power device and manufacture method thereof.
The present invention solves the problems of the technologies described above adopted technical scheme: a kind of super knot power device, its structure cell comprises the first conductive type semiconductor substrate 7, the second conductive type semiconductor assisted depletion layer 14, the second conductive type semiconductor drift region 4, the first conductive type semiconductor drift region 11, the first conductive type semiconductor tagma 9, the second conductive type semiconductor source region 10, the first conductive type semiconductor contact zone 8, source class metallic electrode 1, drain metal polarizing electrode 5, the second conductive type semiconductor material drain region 6, thin grid oxide layer 13, gate electrode 2, thick oxide layer 12 and extension gate electrode 3, described the second conductive type semiconductor assisted depletion layer 14 is arranged on the upper surface of the first conductive type semiconductor substrate 7, described the second conductive type semiconductor drift region 4, the first conductive type semiconductor drift region 11 and the first conductive type semiconductor tagma 9 are in contact with one another and are all arranged on the upper surface of the second conductive type semiconductor assisted depletion layer 14, the second conductive type semiconductor drift region 4 parts are arranged on the upper surface of the first conductive type semiconductor drift region 11, described the second conductive type semiconductor source region 10 and the first conductive type semiconductor contact zone 8 are separate to be arranged in the first conductive type semiconductor tagma 9, described source class metallic electrode 1 is arranged on the upper surface in the first conductive type semiconductor contact zone 8 and part the second conductive type semiconductor source region 10, described the second conductive type semiconductor material drain region 6 is arranged in the second conductive type semiconductor drift region 4 one end away from the first conductive type semiconductor tagma 9, described drain metal polarizing electrode 5 is arranged on the upper surface in the second conductive type semiconductor material drain region 6, described thin grid oxide layer 13 is arranged on the part upper surface in the first conductive type semiconductor tagma 9, described gate electrode 2 is arranged on the upper surface of thin grid oxide layer 13, described thick oxide layer 12 is arranged on the upper surface of the second conductive type semiconductor drift region 4, described extension gate electrode 3 is arranged on the upper surface of thick oxide layer 12 and is connected with gate electrode 2, it is characterized in that, on described the second conductive type semiconductor drift region 4 and the first conductive type semiconductor tagma 9, be provided with groove, described thick oxide layer 12 covers the upper surface that is arranged on the second conductive type semiconductor drift region 4, described thin gate oxide 13 covers the upper surface that is arranged on the first conductive type semiconductor tagma 9, and described gate electrode 2 covers the upper surface that is arranged on thick oxide layer 12 and thin gate oxide 13.
Concrete, the total impurities of described the first conductive type semiconductor drift region 11 equates with the total impurities of the second conductive type semiconductor assisted depletion layer 14.
A manufacture method for super knot power device, is characterized in that, comprises the following steps:
The first step: the second low-doped conductive type epitaxial layer of extension on the first conductive type semiconductor substrate 7, forms substrate-assisted depletion layer 14;
Second step: utilize boron Implantation and diffusion technology to make the first conductive type semiconductor tagma 9 and the first conductive type semiconductor drift region 11 on the second conductive type epitaxial layer;
The 3rd step: utilize photoetching and body silicon etching to form groove structure on the first conductive type semiconductor tagma 9 and the first conductive type semiconductor drift region 11, be etched in arrival the second conductive type semiconductor assisted depletion layer 14 upper surface and stop before;
The 4th step: utilize Implantation to inject the impurity of the second conduction type at the first conductive type semiconductor drift region 11 upper surfaces, described Implantation should adopt inclination angle ion implantation, and the second conductive type impurity that makes trenched side-wall and bottom all inject same concentrations forms the second conductive type semiconductor drift region 4;
The 5th step: utilize the thermal oxidation technology thin grid oxide layer 13 of growing at the first conductive type semiconductor tagma 9 upper surfaces;
The 6th step: at the first conductive type semiconductor drift region 11 upper surface deposit thick oxide layers 12;
The 7th step: depositing polysilicon, polysilicon doping and photoetching form polysilicon gate electrode 2, described gate electrode 2 is as covered thick oxide layer 12 upper surfaces;
The 8th step: complete the subsequent technique of conventional LDMOS device, comprise the photoetching in source region and Implantation, the Implantation of contact zone, tagma, the photoetching in drain region and Implantation, dielectric layer deposited, annealing is fine and close and lithography fair lead, depositing metal, anti-carves metal, surface passivation.
Beneficial effect of the present invention is, by the structure of multiaspect grid, channel region surrounded, and increased greatly the width of channel region, thereby reduced the resistance of channel region; By introduce super-junction structure and extension gate electrode 3 in drift region, can reach lower forward conduction resistance.
Accompanying drawing explanation
Fig. 1 is a kind of laterally structural representation of super knot power device of the present invention;
Fig. 2 is along the cutaway view of AA ' direction in Fig. 1;
Fig. 3 is along the cutaway view of BB ' direction in Fig. 1;
Fig. 4 is along the cutaway view of CC ' direction in Fig. 1;
Fig. 5 is extension N-epitaxial loayer schematic diagram on the P+ substrate in the processing step of the laterally manufacture method of super knot power device of embodiment 1;
Fig. 6 utilizes boron Implantation and diffusion technology to make P-body district and p type island region schematic diagram on the N-epitaxial loayer in the processing step of the laterally manufacture method of super knot power device of embodiment 1;
Fig. 7 is the formation groove structure schematic diagram in the processing step of the laterally manufacture method of super knot power device of embodiment 1;
Fig. 8 is the surperficial phosphorus impurities schematic diagram that injects in processing step Zhong drift region of the laterally manufacture method of super knot power device of embodiment 1;
Fig. 9 is the growth thin gate oxide schematic diagram in the processing step of the laterally manufacture method of super knot power device of embodiment 1;
Figure 10 is the laterally processing step Zhong drift region deposit thick oxide layer schematic diagram of the manufacture method of super knot power device of embodiment 1;
Figure 11 is the formation polysilicon gate electrode schematic diagram in the processing step of the laterally manufacture method of super knot power device of embodiment 1;
Figure 12 is that the gate electrode in the processing step of the laterally manufacture method of super knot power device of embodiment 1 will cover channel region and drift region schematic diagram.
Embodiment
Below in conjunction with drawings and Examples, describe technical scheme of the present invention in detail:
As Figure 1-Figure 4, a kind of super knot power device of the present invention, its structure cell comprises the first conductive type semiconductor substrate 7, the second conductive type semiconductor assisted depletion layer 14, the second conductive type semiconductor drift region 4, the first conductive type semiconductor drift region 11, the first conductive type semiconductor tagma 9, the second conductive type semiconductor source region 10, the first conductive type semiconductor contact zone 8, source class metallic electrode 1, drain metal polarizing electrode 5, the second conductive type semiconductor material drain region 6, thin grid oxide layer 13, gate electrode 2, thick oxide layer 12 and extension gate electrode 3, described the second conductive type semiconductor assisted depletion layer 14 is arranged on the upper surface of the first conductive type semiconductor substrate 7, described the second conductive type semiconductor drift region 4, the first conductive type semiconductor drift region 11 and the first conductive type semiconductor tagma 9 are in contact with one another and are all arranged on the upper surface of the second conductive type semiconductor assisted depletion layer 14, the second conductive type semiconductor drift region 4 parts are arranged on the upper surface of the first conductive type semiconductor drift region 11, described the second conductive type semiconductor source region 10 and the first conductive type semiconductor contact zone 8 are separate to be arranged in the first conductive type semiconductor tagma 9, described source class metallic electrode 1 is arranged on the upper surface in the first conductive type semiconductor contact zone 8 and part the second conductive type semiconductor source region 10, described the second conductive type semiconductor material drain region 6 is arranged in the second conductive type semiconductor drift region 4 one end away from the first conductive type semiconductor tagma 9, described drain metal polarizing electrode 5 is arranged on the upper surface in the second conductive type semiconductor material drain region 6, described thin grid oxide layer 13 is arranged on the part upper surface in the first conductive type semiconductor tagma 9, described gate electrode 2 is arranged on the upper surface of thin grid oxide layer 13, described thick oxide layer 12 is arranged on the upper surface of the second conductive type semiconductor drift region 4, described extension gate electrode 3 is arranged on the upper surface of thick oxide layer 12 and is connected with gate electrode 2, it is characterized in that, on described the second conductive type semiconductor drift region 4 and the first conductive type semiconductor tagma 9, be provided with groove, described thick oxide layer 12 covers the upper surface that is arranged on the second conductive type semiconductor drift region 4, described thin gate oxide 13 covers the upper surface that is arranged on the first conductive type semiconductor tagma 9, and described gate electrode 2 covers the upper surface that is arranged on thick oxide layer 12 and thin gate oxide 13.
Operation principle of the present invention is:
Take the first conductive type semiconductor material as P type semiconductor material is example, operation principle of the present invention and beneficial effect be described:
In described structure, the foreign ion sum approximately equal of the foreign ion sum providing in the second conductive type semiconductor 4 and the opposite types in the first conductive type semiconductor drift region 11, meets charge balance conditions, forms super-junction structure.
Described structure oppositely withstand voltage: when grid 2 and source class metallic electrode 1 add zero potential, when drain metal polarizing electrode 5 adds positive voltage, the first conductive type semiconductor material sections 11 and 4 Zhong holes, the second drift region, conductive type semiconductor material sections and electrons exhaust rapidly, it is zero that whole region free carrier number is close to, make electric field in drift region 4 close to distributed rectangular, can obtain higher device withstand voltage.In theory, the doping content of the relevant ，Er Yu of the length of the big or small Zhi Yu drift region 4 of device withstand voltage drift region 4 is irrelevant.And the second conductive type semiconductor material assisted depletion layer 14 can shield the withstand voltage reduction that the substrate-assisted depletion effect that brings due to the first conductive type semiconductor material substrate 7 causes.
The forward conduction of described structure: add positive voltage on grid 2, source class metallic electrode adds 1 zero potential, when drain metal polarizing electrode 5 adds positive voltage, the first conductive type semiconductor material tagma 9 under gate electrode 2 is by transoid, form the raceway groove that connects the second conductive type semiconductor material source region 10 and the second drift region, conductive type semiconductor material sections 4, break-over of device.Because channel region is folding stereo structure, three faces are covering grid electrode 2 all, and channel region area is increased greatly, can effectively reduce channel region resistance.The first conductive type semiconductor material sections 11 and the second conductive type semiconductor material drift region 4 have formed the super-junction structure of charge balance, the doping content of drift region 4 can not affect the oppositely withstand voltage of device in theory, so drift region 4 can adopt higher doping content.Meanwhile, owing to having thick oxide layer 12 on drift region 4 and extending gate electrode 3, the surface induction that extends gate electrode 3 Hui drift regions 4 goes out a majority carrier accumulation layer, and this accumulation layer can provide a low-resistance channel to electric current, reduces drift zone resistance.Because drift region 4 has equally also adopted the stereochemical structure of folded form, increased the accumulation layer aisle spare on 4 surfaces, drift region, can reach lower forward conduction resistance.
Embodiment 1:
As of the present invention, with better embodiment, the invention discloses a kind of laterally preparation method of super knot power device of extremely low conduction resistance, it comprises the steps:
(1) monocrystalline silicon is prepared, and adopts P type heavily doped region substrate 1, and foreign atom is arsenic, and concentration is 1.5 * 10<sup TranNum="118">19</sup>cm<sup TranNum="119">-3</sup>，Qi crystal orientation is<100>;
(2) extension N-epitaxial loayer on P+ substrate, as shown in Figure 5, as substrate-assisted depletion layer, foreign atom is phosphorus, epitaxial thickness is adjusted according to device electrical parameter index request;
(3) on low-resistance N-epitaxial loayer, utilize boron Implantation and diffusion technology to make P-body district and p type island region, as shown in Figure 6;
(4) photoetching, recycling body silicon etching forms groove structure in channel region and drift region, and as shown in Figure 7, body silicon etching can adopt reactive ion etching;
(5) utilize Implantation to inject phosphorus impurities on surface, drift region, Implantation should adopt inclination angle ion implantation, by suitably choosing of implant angle, make trenched side-wall and bottom all inject the phosphorus impurities of same concentrations, the phosphorus impurities injecting should guarantee that after impurity compensation the total impurities in YuP+ district, N+ district meets charge balance, as shown in Figure 8;
(6) in channel region, utilize thermal oxidation technology growth thin gate oxide, as shown in Figure 9;
(7) at drift region deposit thick oxide layer, as shown in figure 10;
(8) depositing polysilicon, polysilicon doping and photoetching form polysilicon gate electrode, and as shown in figure 11, this gate electrode will cover channel region and drift region, as shown in figure 12;
(9) complete the subsequent technique of conventional LDMOS device, technological process and conventional LDMOS device are similar, comprise the photoetching in N+ source region and the photoetching in the injection ,N+ drain region of injection ,P+ contact zone and injection, dielectric layer deposited, annealing fine and close also lithography fair lead, depositing metal, anti-carve the steps such as metal, passivation, photoetching passivation hole.
Can be as the case may be in implementation process, in the situation that basic structure is constant, carry out certain accommodation design, for example: after the making in P-body district can be placed on step (8) polysilicon electrode and forms in step (3), by self-registered technology, form.
This example is on the basis of embodiment 1, its first conductivity regions 11 also be can be to the situation shown in Fig. 5, between the second conductive type semiconductor assisted depletion floor 14 and the second conductive type semiconductor district 4 of groove, the district 11 of reserve part the first conduction type.
The concrete methods of realizing embodiment 1 of embodiment 2 is similar, just, in the 5th step of the processing step of embodiment 1, reduces the etching depth to the first conductivity regions 11, retains the first conductivity regions 11 of suitable thickness in ditch groove.
Claims (3)
1. one kind surpasses knot power device, its structure cell comprises the first conductive type semiconductor substrate (7), the second conductive type semiconductor assisted depletion layer (14), the second conductive type semiconductor drift region (4), the first conductive type semiconductor drift region (11), the first conductive type semiconductor tagma (9), the second conductive type semiconductor source region (10), the first conductive type semiconductor contact zone (8), source class metallic electrode (1), drain metal polarizing electrode (5), the second conductive type semiconductor material drain region (6), thin grid oxide layer (13), gate electrode (2), thick oxide layer (12) and extension gate electrode (3), described the second conductive type semiconductor assisted depletion layer (14) is arranged on the upper surface of the first conductive type semiconductor substrate (7), described the second conductive type semiconductor drift region (4), the first conductive type semiconductor drift region (11) and the first conductive type semiconductor tagma (9) are in contact with one another and are all arranged on the upper surface of the second conductive type semiconductor assisted depletion layer (14), the second conductive type semiconductor drift region (4) part is arranged on the upper surface of the first conductive type semiconductor drift region (11), described the second conductive type semiconductor source region (10) and the first conductive type semiconductor contact zone (8) are separate to be arranged in the first conductive type semiconductor tagma (9), described source class metallic electrode (1) is arranged on the upper surface in the first conductive type semiconductor contact zone (8) and part the second conductive type semiconductor source region (10), described the second conductive type semiconductor material drain region (6) is arranged in the second conductive type semiconductor drift region (4) one end away from the first conductive type semiconductor tagma (9), described drain metal polarizing electrode (5) is arranged on the upper surface in the second conductive type semiconductor material drain region (6), described thin grid oxide layer (13) is arranged on the part upper surface in the first conductive type semiconductor tagma (9), described gate electrode (2) is arranged on the upper surface of thin grid oxide layer (13), described thick oxide layer (12) is arranged on the upper surface of the second conductive type semiconductor drift region (4), described extension gate electrode (3) is arranged on the upper surface of thick oxide layer (12) and is connected with gate electrode (2), it is characterized in that, on described the second conductive type semiconductor drift region (4) and the first conductive type semiconductor tagma (9), be provided with groove, described thick oxide layer (12) covers the upper surface that is arranged on the second conductive type semiconductor drift region (4), described thin gate oxide (13) covers the upper surface that is arranged on the first conductive type semiconductor tagma (9), and described gate electrode (2) covers the upper surface that is arranged on thick oxide layer (12) and thin gate oxide (13).
2. a kind of super knot power device according to claim 1, is characterized in that, the total impurities of described the first conductive type semiconductor drift region (11) equates with the total impurities of the second conductive type semiconductor assisted depletion layer (14).
3. a manufacture method for super knot power device, is characterized in that, comprises the following steps:
The first step: at upper the second low-doped conductive type epitaxial layer of extension of the first conductive type semiconductor substrate (7), form substrate-assisted depletion layer (14);
Second step: utilize boron Implantation and diffusion technology to make the first conductive type semiconductor tagma (9) and the first conductive type semiconductor drift region (11) on the second conductive type epitaxial layer, the first conductive type semiconductor drift region (11) and the first conductive type semiconductor tagma (9) are in contact with one another and are all arranged on the upper surface of the second conductive type semiconductor assisted depletion layer (14);
The 3rd step: utilize photoetching and body silicon etching at the upper groove structure that forms in the first conductive type semiconductor tagma (9) and the first conductive type semiconductor drift region (11), be etched in arrival the second conductive type semiconductor assisted depletion layer (14) upper surface and stop before;
The 4th step: utilize Implantation to inject the impurity of the second conduction type at the first conductive type semiconductor drift region (11) upper surface, described Implantation should adopt inclination angle ion implantation, the second conductive type impurity that makes trenched side-wall and bottom all inject same concentrations forms the second conductive type semiconductor drift region (4), described the second conductive type semiconductor drift region (4), the first conductive type semiconductor drift region (11) and the first conductive type semiconductor tagma (9) are in contact with one another and are all arranged on the upper surface of the second conductive type semiconductor assisted depletion layer (14), the second conductive type semiconductor drift region (4) part is arranged on the upper surface of the first conductive type semiconductor drift region (11),
The 5th step: utilize the thermal oxidation technology thin grid oxide layer (13) of growing at the first conductive type semiconductor tagma (9) upper surface;
The 6th step: at the first conductive type semiconductor drift region (11) upper surface deposit thick oxide layer (12), thick oxide layer (12) covers the upper surface that is arranged on the second conductive type semiconductor drift region (4);
The 7th step: depositing polysilicon, polysilicon doping and photoetching form polysilicon gate electrode (2), and described gate electrode (2) covers thick oxide layer (12) upper surface;
The 8th step: complete the subsequent technique of conventional LDMOS device, comprise the photoetching in source region and Implantation, the Implantation of contact zone, tagma, the photoetching in drain region and Implantation, dielectric layer deposited, annealing is fine and close and lithography fair lead, depositing metal, anti-carves metal, surface passivation.
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