CN103996715A - Transverse double-diffusion metal oxide semiconductor field-effect tube - Google Patents
Transverse double-diffusion metal oxide semiconductor field-effect tube Download PDFInfo
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- CN103996715A CN103996715A CN201410235457.0A CN201410235457A CN103996715A CN 103996715 A CN103996715 A CN 103996715A CN 201410235457 A CN201410235457 A CN 201410235457A CN 103996715 A CN103996715 A CN 103996715A
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- drift region
- metal oxide
- oxide semiconductor
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000009792 diffusion process Methods 0.000 title claims abstract description 11
- 230000005669 field effect Effects 0.000 title claims abstract description 11
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 11
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 11
- 238000009413 insulation Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 239000011810 insulating material Substances 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 6
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 239000002800 charge carrier Substances 0.000 abstract 2
- 238000009825 accumulation Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a novel semiconductor device with a concave and convex surface structure in order to realize the purpose that lowest on-resistance is obtained on the condition that certain breakdown voltage is achieved. According to the transverse double-diffusion metal oxide semiconductor field-effect tube, the concave and convex surface structure is formed from a source region to a drain region through etching, inversion layers are accumulated in a channel of the lateral wall of an etched groove, a plurality of charge carriers are formed in a shift region of the lateral wall of the etched groove, and therefore resistance of the channel region and resistance of the shift region are reduced. Moreover, a grid electrode is expanded to the drain end, the shift region is completely covered with the grid electrode, therefore, the charge carriers are accumulated on the surface of the shift region when the device is in an on state and the on-resistance is effectively reduced.
Description
Technical field
The present invention relates to field of semiconductor devices, particularly relate to a kind of lateral double diffusion metal oxide semiconductor field effect transistor.
Background technology
At PIC (power integrated circuit) field low pressure lateral power, be subject to extensive concern in recent years.Lateral power is for compatible better in technique with low-voltage circuit, design has thin epitaxy layer and can meet certain withstand voltage novel LDMOS, and thereby the lower conducting resistance of acquisition reduces power consumption, be an important development direction of current power semiconductor technologies, and the subject matter that LDMOS class device exists is breakdown voltage (BV) and ON state conducting resistance (R
on) between contradiction.So meeting under the condition of certain puncture voltage, obtaining alap conducting resistance just becomes the focus of domestic and international research to reduce conduction loss.
Summary of the invention
The present invention proposes a kind of semiconductor device with ups and downs surface texture, to realize under the condition that meets certain puncture voltage, obtain alap conducting resistance.
Technical scheme of the present invention is as follows:
This lateral double diffusion metal oxide semiconductor field effect transistor, comprising:
The substrate of semi-conducting material;
Be positioned at the drift region of extension on described substrate;
Lay respectively at base and the drain region at two ends on drift region;
Be positioned at the source region of described base region surface;
At the gate insulation layer between source region and drain region, on the integral surface of base and drift region;
Be positioned at the grid of gate electrode insulation surface;
It is characterized in that:
On surface, drift region, from source region, to drain region integral body, be etched into the ups and downs surface texture (being strip groove parallel arrangement alternate with bar shaped boss) of strip.
Based on above-mentioned basic scheme, the present invention also further does following optimization and limits and improve:
In the ups and downs surface texture of above-mentioned strip, the degree of depth of all strip grooves is all identical, and width is all identical.
In the ups and downs surface texture of above-mentioned strip, establish upper surface and the Wei Yi district, side of bar shaped boss, the Wei Er district, bottom surface of strip groove, the doping type in He Er district, drift region Yi district is identical.
The doping content in Yi district, above-mentioned drift region is greater than the doping content in Er district, drift region.
In the ups and downs surface texture of above-mentioned strip, bar shaped boss has two or more.
Above-mentioned grid and gate insulation layer completely (expansion) cover surface, drift region.
The beneficial effect of technical solution of the present invention is as follows:
Structure of the present invention, due to the ups and downs surface texture forming by etching from source region to drain region, has also formed majority carrier (or channel inversion layer) accumulation in the side of etching groove, reduced the resistance of channel region and the resistance of drift region.Because the grid of expanding covers son completely above drift region, while making device ON state, surface, drift region forms the accumulation of majority carrier-electronics, and the electronic shell of accumulation provides low conductive channel.Longitudinally, with horizontal Electric Field Modulated effect (the charge compensation effect of enhancing), the drift region concentration of bearing certain puncture voltage when device is turn-offed increases.
Accompanying drawing explanation
Fig. 1 is the structure front view (not comprising ups and downs surface texture) of LDMOS in the embodiment of the present invention;
Fig. 2 is the three-dimensional structure schematic diagram of LDMOS in the embodiment of the present invention;
Fig. 3 is the schematic side view of LDMOS in the embodiment of the present invention.
Drawing reference numeral explanation:
1-source region; 2-grid; 3-expansion covers the grid above drift region; 4-drift region; 5-drain region; 6-substrate; 7-base; One district, 41-drift region (upper surface, side); 2nd district, 42-drift region; The degree of depth of 8-strip groove; 9-bar shaped boss width; The width of 10-strip groove.
Embodiment
Below in conjunction with drawings and Examples, the present invention is done to the explanation of detailed example, this embodiment be not to technical solution of the present invention the restriction of definite scope.
As shown in Figure 1, Figure 2 and Figure 3, LDMOS of the present invention comprises:
Semiconductive material substrate 6;
Be positioned at the drift region 4 of epitaxial surface on substrate;
Lay respectively at base 7 and the drain region 5 at two ends on drift region;
Be positioned at the source region 1 of base region surface;
Between source region and drift region, be conducting channel, be positioned at gate electrode 2 under;
Between conducting channel and 2 gate electrodes, it is gate oxide;
Gate electrode is expanded the electrode that covers top, drift region;
From source region, to drain region integral body, be etched into the ups and downs surface texture of strip.
In Fig. 3,8,9 and 10 represent respectively the width of the degree of depth, bar shaped boss width and the strip groove of ups and downs silicon face etching.
Due to from source region 1 to drain region 5 ups and downs surface texture, in the side of etching groove, also formed majority carrier (or channel inversion layer) accumulation, this has further reduced the resistance of channel region and the resistance of drift region.
The width of optimizing the degree of depth, bar shaped boss width and strip groove that drift region 4 ups and downs surface texture silicon face etching is set, further reduces conducting resistance.
By extended grid 3, while making device ON state, 4 surfaces, drift region form the accumulation of majority carrier-electronics, and the electronic shell of accumulation provides low conductive channel.Longitudinally, with horizontal Electric Field Modulated effect (the charge compensation effect of enhancing), the drift region concentration of bearing certain puncture voltage when device is turn-offed increases.
The present invention (also having comprised gate insulation layer) is etched into the conductive layer from source region to drain region the ups and downs surface texture of strip, the upper surface that formation protrudes and sidewall, sunk bottom surface, can establish upper surface and the Wei Yi district, side of bar shaped boss, the Wei Er district, bottom surface of strip groove, accordingly, channel region also just can be divided into one district, channel region, 2nd district, channel region, drift region also just can be divided into one district, drift region, 2nd district, drift region, thereby with respect to the device of the conventional planar of same width, increase the width of equivalent raceway groove and equivalent drift region.And, the grid with concavo-convex contoured surface structure is expanded to drain region on thinner field oxide always.The Electric Field Modulated effect of extended grid, in drift region, one district 41,42 surfaces, 2nd district, drift region all form majority carrier accumulation, and the majority carrier of accumulation greatly reduces the conducting resistance of drift region.And in raceway groove one district, the concentration of the raceway groove two equivalent inversion layers in districts surfaces increases than the concentration of planar channeling surface inversion layer, thereby also greatly reduce the conducting resistance of raceway groove.This ups and downs surface texture, than conventional planar structure, can obtain low-down conducting resistance, thereby has reduced significantly the power consumption of device.
Specifically can form LDMOS of the present invention by following steps:
1) the N-type drift region of the Grown of semi-conducting material (comprising Si, SiC and GaAs etc.) doping.
2) on drift region, one end forms P type base, and on base, forms the source region of N-type.
3) at the drift region other end, form P type heavy doping drain region.
4) by reactive ion etching technology, the ups and downs surface texture forming from source region to drain region.
5) corresponding, on ups and downs raceway groove, form gate oxide.
6) also form the grid of expansion.
Certainly, the LDMOS in the present invention can be also P raceway groove, and its structure is identical with N raceway groove LDMOS, does not repeat them here.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, do not departing under the prerequisite of the technology of the present invention principle; can also make some improvement and replacement, these improvement and replacement also should be considered as protection scope of the present invention.
Claims (6)
1. a lateral double diffusion metal oxide semiconductor field effect transistor, comprising:
The substrate of semi insulating material;
Be positioned at the drift region of extension on described substrate;
Lay respectively at base and the drain region at two ends on drift region;
Be positioned at the source region of described base region surface;
At the gate insulation layer between source region and drain region, on the integral surface of base and drift region;
Be positioned at the grid of gate electrode insulation surface;
It is characterized in that:
On surface, drift region, from source region, to drain region integral body, be etched into the ups and downs surface texture of strip.
2. lateral double diffusion metal oxide semiconductor field effect transistor according to claim 1, is characterized in that: in the ups and downs surface texture of described strip, the degree of depth of all strip grooves is all identical, and width is all identical.
3. lateral double diffusion metal oxide semiconductor field effect transistor according to claim 1, it is characterized in that: in the ups and downs surface texture of described strip, if the upper surface of bar shaped boss and Wei Yi district, side, the Wei Er district, bottom surface of strip groove, the doping type in He Er district, drift region Yi district is identical.
4. lateral double diffusion metal oxide semiconductor field effect transistor according to claim 3, is characterized in that: the doping content in Yi district, drift region is greater than the doping content in Er district, drift region.
5. according to the arbitrary described lateral double diffusion metal oxide semiconductor field effect transistor of claim 1-4, it is characterized in that: in the ups and downs surface texture of described strip, bar shaped boss has two or more.
6. according to the arbitrary described lateral double diffusion metal oxide semiconductor field effect transistor of claim 1-4, it is characterized in that: described grid and gate insulation layer cover surface, drift region completely.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410235457.0A CN103996715A (en) | 2014-05-29 | 2014-05-29 | Transverse double-diffusion metal oxide semiconductor field-effect tube |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410235457.0A CN103996715A (en) | 2014-05-29 | 2014-05-29 | Transverse double-diffusion metal oxide semiconductor field-effect tube |
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| Publication Number | Publication Date |
|---|---|
| CN103996715A true CN103996715A (en) | 2014-08-20 |
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|---|---|---|---|
| CN201410235457.0A Pending CN103996715A (en) | 2014-05-29 | 2014-05-29 | Transverse double-diffusion metal oxide semiconductor field-effect tube |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107564957A (en) * | 2016-06-30 | 2018-01-09 | 英飞凌科技股份有限公司 | Power semiconductor with completely depleted channel region |
| CN110808287A (en) * | 2019-10-31 | 2020-02-18 | 东南大学 | High-quality-factor transverse double-diffusion metal oxide semiconductor device |
| US10950718B2 (en) | 2017-12-15 | 2021-03-16 | Infineon Technologies Dresden GmbH & Co. KG | IGBT with fully depletable n- and p-channel regions |
| US11171202B2 (en) | 2016-06-30 | 2021-11-09 | Infineon Technologies Ag | Power semiconductor device having fully depleted channel regions |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080296694A1 (en) * | 2005-12-22 | 2008-12-04 | Nxp B.V. | Semiconductor Device with Field Plate and Method |
| CN102709190A (en) * | 2012-05-24 | 2012-10-03 | 上海宏力半导体制造有限公司 | LDMOS (Laterally Diffused Metal Oxide Semiconductor) field effect transistor and manufacturing method thereof |
| CN103515443A (en) * | 2013-09-16 | 2014-01-15 | 电子科技大学 | Super-junction power device and manufacturing method thereof |
-
2014
- 2014-05-29 CN CN201410235457.0A patent/CN103996715A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080296694A1 (en) * | 2005-12-22 | 2008-12-04 | Nxp B.V. | Semiconductor Device with Field Plate and Method |
| CN102709190A (en) * | 2012-05-24 | 2012-10-03 | 上海宏力半导体制造有限公司 | LDMOS (Laterally Diffused Metal Oxide Semiconductor) field effect transistor and manufacturing method thereof |
| CN103515443A (en) * | 2013-09-16 | 2014-01-15 | 电子科技大学 | Super-junction power device and manufacturing method thereof |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107564957A (en) * | 2016-06-30 | 2018-01-09 | 英飞凌科技股份有限公司 | Power semiconductor with completely depleted channel region |
| US10672767B2 (en) | 2016-06-30 | 2020-06-02 | Infineon Technologies Ag | Power semiconductor device having different channel regions |
| CN107564957B (en) * | 2016-06-30 | 2020-12-29 | 英飞凌科技股份有限公司 | Power semiconductor device with fully depleted channel region |
| US11171202B2 (en) | 2016-06-30 | 2021-11-09 | Infineon Technologies Ag | Power semiconductor device having fully depleted channel regions |
| US10950718B2 (en) | 2017-12-15 | 2021-03-16 | Infineon Technologies Dresden GmbH & Co. KG | IGBT with fully depletable n- and p-channel regions |
| CN110808287A (en) * | 2019-10-31 | 2020-02-18 | 东南大学 | High-quality-factor transverse double-diffusion metal oxide semiconductor device |
| CN110808287B (en) * | 2019-10-31 | 2023-10-17 | 东南大学 | Superior quality factor transverse double-diffusion metal oxide semiconductor device |
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Application publication date: 20140820 |