CN109216431B - Completely isolated lateral diffusion metal oxide semiconductor structure and manufacturing method thereof - Google Patents
Completely isolated lateral diffusion metal oxide semiconductor structure and manufacturing method thereof Download PDFInfo
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- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 14
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 14
- 238000009792 diffusion process Methods 0.000 title claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims abstract description 18
- 239000012535 impurity Substances 0.000 claims description 37
- 238000002513 implantation Methods 0.000 claims description 32
- 238000002955 isolation Methods 0.000 claims description 27
- 239000002019 doping agent Substances 0.000 claims description 7
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 description 10
- 230000005684 electric field Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 6
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 239000011574 phosphorus Substances 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 210000000746 body region Anatomy 0.000 description 5
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The invention relates to a completely isolated lateral diffusion metal oxide semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate of a first doping type, a second doping type buried layer arranged in the substrate of the first doping type, a main structure formed on the second doping type buried layer and an isolating ring arranged around the main structure, wherein the main structure is isolated by the buried layer and the isolating ring. The manufacturing method is used for manufacturing the semiconductor structure. The semiconductor structure manufactured by the method can be applied to the high-voltage field.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an LDMOS (laterally diffused metal oxide semiconductor) with a high-voltage completely-isolated N-type channel.
Background
As shown in fig. 1, compared with a conventional NLDMOS, a Fully Isolated N-channel ldmos (NLDMOS) structure allows a difference between Drain (Drain) and isolation (BN-ISO) voltage biases, and under different isolation bias voltages, the stability of the electrical characteristics of the device can be ensured, and the device is more suitable for the application operation of a power supply integrated circuit, and the demand is increasing. However, Fully ISO NLDMOS is currently also loitering in low voltage applications, and is difficult to extend to high voltage applications. The reason for this is mainly that the voltage bias of the isolation terminal in the high voltage field is large, the P-type substrate (HVPWell) of the device is completely depleted by the bottom N-type buried layer (BN), the potential distribution of the drift region (N-drift) is influenced, and the fluctuation of the electrical characteristics of the device is large.
During manufacturing of the NLDMOS device, an N-type buried layer (BN) is formed on a P-type substrate (P-sub) through injection, then an epitaxial layer is epitaxially grown on the P-type substrate (P-sub) with the N-type buried layer (BN), and then a main body structure of the NLDMOS is formed through a fixed process so as to achieve functions of the NLDMOS device. Since the process is fixed (the equipment, materials, conditions, etc. used are fixed, and the process is mature and cannot be easily changed), the main structure formed on the epitaxial layer is also usually fixed, and the device parameters are also completely fixed. Most importantly, the thickness, concentration and the like of the high-voltage P-type substrate (HVPWell) in the epitaxial layer are also fixed, and the P-type substrate cannot be lifted in other ways so as not to be depleted. This therefore limits the extension of the Fully ISO NLDMOS device to high voltage applications.
One solution is to add P-type impurities at the bottom of a developed high-voltage Fully ISO NLDMOS device, improve the concentration of a P-type substrate (P-sub) and slow down the depletion of the impurities; however, as an isolation terminal, the concentration of the N-type buried layer (BN) may be high; in addition, the increase of the concentration of the P-type substrate (P-sub) can significantly reduce the junction breakdown voltage of the bottom P-type substrate (P-sub) and the N-type buried layer (BN), which becomes another restriction of expansion of the device to high-voltage application, so that the improvement space of the concentration of the bottom of the P-type substrate is limited, the improvement effect is limited, and the high-voltage application of 40-60V is difficult to realize.
Disclosure of Invention
In view of the above, there is a need for a fully isolated ldmos structure that can be applied in high voltage applications.
A completely isolated lateral diffusion metal oxide semiconductor structure comprises a first doping type substrate, a second doping type buried layer arranged in the first doping type substrate, a main structure formed on the second doping type buried layer and an isolation ring arranged around the main structure, wherein the buried layer and the isolation ring isolate the main structure together, an extension layer of the first doping type is formed in the second doping type buried layer, and the extension layer is close to one side of the main structure and is integrated with a well region in the main structure.
In one embodiment, the first doping type substrate is a P-type substrate, the second doping type buried layer is an N-type buried layer, and the extension layer of the first doping type is P-type doped.
In one embodiment, the doping impurity of the N-type buried layer is phosphorus, and the P-type doping impurity of the extension layer is boron.
In one embodiment, the implantation energy of the P-type impurity is 50-200 KeV, and the implantation dose is 5e 12-5 e13cm-2。
In one embodiment, the implantation peak value of the N-type buried layer is larger than the implantation peak value of the P-type impurity of the extension layer, and the implantation dosage range of the N-type impurity is 5e 12-5 e13cm-2。
A method for manufacturing a completely isolated lateral diffusion metal oxide semiconductor structure comprises the following steps:
providing a first doping type substrate;
forming a second doping type buried layer in the first doping type substrate in a mode of injecting second type impurities;
forming an extension layer in the second doping type buried layer by injecting first type impurities;
epitaxially growing an epitaxial layer on the first doping type substrate;
forming a main structure and an isolation ring on the epitaxial layer; the second doping type buried layer and the isolation ring together isolate the main structure.
In one embodiment, the first doping type substrate is a P-type substrate, the second doping type buried layer is an N-type buried layer, and the extension layer of the first doping type is P-type doped.
In one embodiment, the doping impurity of the N-type buried layer is phosphorus, and the P-type doping impurity of the extension layer is boron.
In one embodiment, the implantation energy of the P-type impurity is 50-200 KeV, and the implantation dose is 5e 12-5 e13cm-2。
In one embodiment, the implantation peak value of the N-type buried layer is larger than the implantation peak value of the P-type impurity of the extension layer, and the implantation dosage range of the N-type impurity is 5e 12-5 e13cm-2。
According to the structure and the method, the first-type impurities are doped in the second doping type buried layer, the extension layer with the same doping type as the body region of the main structure in the epitaxial layer is formed on the surface, which is in contact with the epitaxial layer, and the body region, which is used for forming the main structure of the device, in the epitaxial layer can be longitudinally expanded to increase the depth of the body region. When the isolation end is forward biased, the well region is not easy to be exhausted, so that the drift region is not influenced, and the electrical characteristics of the device are stable. The high-voltage application of the completely isolated lateral diffusion metal oxide semiconductor device is realized under the condition that the whole device process is fixed.
Drawings
FIG. 1 is a schematic structural diagram of a conventional LDMOS with a fully-isolated N-type channel;
FIG. 2 is a schematic diagram of a fully isolated LDMOS structure according to an embodiment;
FIG. 3 is a schematic diagram of a semiconductor structure of the embodiment of FIG. 2;
FIG. 4 is a graph of longitudinal doping concentration of FIG. 3 along section A-A;
FIG. 5a is a schematic diagram of the electric field distribution when the isolated terminal (ISO) bias voltage is 0V;
FIG. 5b is a schematic diagram of the electric field distribution when the isolated end (ISO) bias voltage is 50V;
FIG. 6a is a longitudinal voltage breakdown curve;
FIG. 6b is a working curve;
FIG. 7 is a flowchart of a manufacturing method according to an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Fig. 2 is a fully isolated ldmos structure according to an embodiment. The semiconductor structure includes a substrate 110 of a first doping type, a buried layer 120 of a second doping type disposed within the substrate 110 of the first doping type, a main structure 130 formed within an epitaxial layer on the buried layer 120 of the second doping type, and an isolation ring 140 disposed around the main structure 130. The second doping type buried layer 120 and the isolation ring 140 together isolate the main structure 130, an extension layer 150 of the first doping type is formed in the second doping type buried layer 120, and the extension layer 150 is close to one side of the main structure 130 and is integrated with a well region in the main structure 130.
The main structure 130 includes a channel region and a drift region, which are separated from each other and formed in a well region (in this embodiment, a first doping type hvw region). A source region is formed in the channel region and led out as a source electrode, a drain region is formed in the drift region and led out as a drain electrode, and the gate structure crosses the channel region and the drift region. Isolation is also performed where necessary, for example using shallow trench isolation.
In the above-described structure, the first-type impurity is doped into the second doping-type buried layer 120, and the extension layer 150 having the same doping type as the device body region in the epitaxial layer is formed on the surface in contact with the epitaxial layer, so that the well region (the first doping-type high-voltage well region in this embodiment) in the epitaxial layer for forming the main structure of the device can be longitudinally extended to increase the depth thereof. When the isolation end is forward biased, the well region is not easy to be exhausted, so that the drift region is not influenced, and the electrical characteristics of the device are stable. The high-voltage application of the completely isolated lateral diffusion metal oxide semiconductor device is realized under the condition that the whole device process is fixed.
In one embodiment, the first doping type substrate 110 is a P-type substrate, the second doping type buried layer 120 is an N-type buried layer, and the extension layer 150 of the first doping type is P-type doped. In the present embodiment, the doping described above realizes an N-channel fully isolated laterally diffused metal oxide semiconductor (NLDMOS) device structure. Fully ISONLDMOS is widely applied and has large demand, but cannot be easily extended to the high-voltage field (40V-60V). Through the structure, a depletion layer of a well region (in the embodiment, a high-voltage P-type well, HVPWell) can be increased, and meanwhile, the junction breakdown voltage can also be very high, so that the application of Fully ISO NLDMOS in the high-voltage field is realized.
In one embodiment, the doping impurity of the N-type buried layer is phosphorus (P), and the P-type doping impurity of the extension layer 150 is boron (B). The N-type buried layer and the P-type impurity extension layer 150 may be formed by high-energy implantation and then by well-driving through a ferroelectric tube. Since the well region (HVPWell) extends from the epitaxial layer to the P-type substrate (P-sub)110, the depletion region of HVPwell is effectively increased; in application, when the isolation end is under different high voltage biases, HVPwell depletion regions are far away from a drift region (N-drift) region of the surface, the potential and electric field distribution of a device are not influenced by the bottom bias, and the electrical characteristics of the device are constant. It is understood that other N-type and P-type doping may be used in other embodiments.
Specifically, the implantation peak of the N-type buried layer (BN)120 should be greater than the implantation peak depth of the extension layer 150; the implantation dosage is 5e 12-5 e13cm-2(ii) a The implantation dose of the extension layer 150 is 5e 12-5 e13cm-2(ii) a The specific implantation conditions should be determined by the device vertical isolation voltage requirements. .
Fig. 4 is a graph of the vertical dopant concentration of fig. 3 along the a-a section. In the figure, the solid points are the conventional doping concentration curves, and the hollow points are the doping concentration curves of the present embodiment. In the figure, NG represents the doping concentration profile of the drift region in the longitudinal section; HVPWell represents the doping concentration profile of the well region; BN _ B is the doping concentration profile of boron (B) in the extension layer 150; BN _ P is a doping concentration distribution of phosphorus (P) in the N-type buried layer 120; p-sub represents a doping concentration profile in a P-type substrate (P-sub).
The concentration of the N-type buried layer (BN)120 may be decreased compared to the doping concentration, implantation depth, location of the conventional structure, but the implantation depth is increased and a doped region of the extension layer 150 is additionally implanted with P-type impurities therein.
The NLDMOS structure has good high-voltage performance. Fig. 5a is a schematic diagram of electric field distribution when the isolated terminal (ISO) bias voltage is 0V, and fig. 5b is a schematic diagram of electric field distribution when the isolated terminal (ISO) bias voltage is 50V. It can be seen that the isolation terminal (ISO) voltage is biased by 50V, the well region (HVPwell) is not fully depleted and is far away from the drift region; compared with the voltage bias of 0V at an isolation end (ISO), the surface electric field and the potential distribution of the device are not different.
As shown in fig. 6a, the vertical breakdown voltage (Punch BV) of the bottom N-type buried layer (BN) to the surface Drain (Drain) is up to 75V. As shown in fig. 6b, when the isolated terminal (ISO) voltage bias is 0V or 50V, the breakdown Curve (BV cut) of the device remains unchanged, and the breakdown voltage BV is 65V.
Based on the same inventive concept, a method for manufacturing a fully-isolated laterally diffused metal oxide semiconductor structure is provided. As shown in fig. 7 in conjunction with fig. 2, the method includes the following steps S110 to S150.
Step S110: a first doping type substrate 110 is provided.
Step S120: a second doping-type buried layer 120 is formed by implanting second-type impurities in the first doping-type substrate 110.
Step S130: an extension layer 150 is formed by implanting first-type impurities within the second-type buried layer 120.
Step S140: an epitaxial layer (not shown) is epitaxially grown on the first doping type substrate 110.
Step S150: forming a main structure 130 and an isolation ring 140 on the epitaxial layer; the second doping type buried layer 120 and the isolation ring 140 together isolate the main structure 130. The main structure 130 is an LDMOS structure, and the forming method thereof is not described herein.
In the above method, by doping the first-type impurity into the second doping-type buried layer 120 and forming the extension layer 150 having the same doping type as the device body region in the epitaxial layer on the surface in contact with the epitaxial layer, the well region (in this embodiment, the first doping-type high-voltage well region) in the epitaxial layer for forming the main structure of the device can be longitudinally expanded to increase the depth thereof. When the isolation end is forward biased, the well region is not easy to be exhausted, so that the drift region is not influenced, and the electrical characteristics of the device are stable. The high-voltage application of the completely isolated lateral diffusion metal oxide semiconductor device is realized under the condition that the process condition of the whole device is fixed.
In one embodiment, as shown in fig. 3, the first doping type substrate 110 is a P-type substrate (P-sub), the second doping type buried layer 120 is an N-type buried layer (BN), and the extension layer 150 of the first doping type is P-type doped. In this embodiment, the doping realizes an N-channel Fully-isolated laterally diffused metal oxide semiconductor (Fully ISONLDMOS) device structure. Fully ISO NLDMOS is widely applied and has a large demand, but cannot be easily extended to the high-voltage field (40V-60V). Through the structure, a depletion layer of a well region (HVPWell) can be increased, and meanwhile, junction breakdown voltage can be high, so that the application of Fully ISO NLDMOS in the high-voltage field is realized.
In one embodiment, the doping impurity of the N-type buried layer is phosphorus (P), and the P-type doping impurity of the extension layer 150 is boron (B). The N-type buried layer and the P-type impurity extension layer 150 can be subjected to high-energy injection in sequence, and then are pushed together through the strong furnace tube to form a well region (HVPWell) which extends from the epitaxial layer to the P-type substrate (P-sub)110, so that the depletion region of the HVPwell is effectively increased; in application, when the isolation end is under different high voltage biases, HVPwell depletion regions are far away from a drift region (N-drift) region of the surface, the potential and electric field distribution of a device are not influenced by the bottom bias, and the electrical characteristics of the device are constant.
Specifically, the implantation depth of the N-type buried layer (BN)120 is greater than that of the extension layer 150; the implantation dosage of the N-type impurities is 5e 12-5 e13cm-2(ii) a The implantation dose of the extension layer 150 is 5e 12-5 e13cm-2(ii) a The specific implantation conditions should be determined by the device vertical isolation voltage requirements.
Fig. 4 is a graph of the vertical dopant concentration of fig. 3 along the a-a section. In the figure, the solid points are the conventional doping concentration curves, and the hollow points are the doping concentration curves of the present embodiment. In the figure, NG represents the doping concentration profile of the drift region in the longitudinal section; HVPWell represents the doping concentration profile of the well region; BN _ B is the doping concentration profile of boron (B) in the extension layer 150; BN _ P is a doping concentration distribution of phosphorus (P) in the N-type buried layer 120; p-sub represents a doping concentration profile in a P-type substrate (P-sub).
The concentration of the N-type buried layer (BN)120 may be decreased compared to the doping concentration, implantation depth, location of the conventional structure, but the implantation depth is increased and a doped region of the extension layer 150 is additionally implanted with P-type impurities therein.
The NLDMOS structure has good high-voltage performance. Fig. 5a is a schematic diagram of electric field distribution when the isolated terminal (ISO) bias voltage is 0V, and fig. 5b is a schematic diagram of electric field distribution when the isolated terminal (ISO) bias voltage is 50V. It can be seen that the isolation terminal (ISO) voltage is biased by 50V, the well region (HVPwell) is not fully depleted and is far away from the drift region; compared with the voltage bias of 0V at an isolation end (ISO), the surface electric field and the potential distribution of the device are not different.
As shown in fig. 6a, the vertical breakdown voltage (Punch BV) of the bottom N-type buried layer (BN) to the surface Drain (Drain) is up to 75V. As shown in fig. 6b, when the isolated terminal (ISO) voltage bias is 0V or 50V, the breakdown Curve (BV cut) of the device remains unchanged, and the breakdown voltage BV is 65V.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A completely isolated lateral diffusion metal oxide semiconductor structure comprises a first doping type substrate, a second doping type buried layer arranged in the first doping type substrate, a main structure formed on the second doping type buried layer and an isolating ring arranged around the main structure, wherein the buried layer and the isolating ring isolate the main structure together.
2. The fully isolated ldmos structure of claim 1, wherein the first doped type substrate is a P-type substrate, the second doped type buried layer is an N-type buried layer, and the extension layer of the first doped type is P-type doped.
3. The fully isolated LDMOS structure of claim 2, wherein the dopant impurity of the buried N-type layer is P and the dopant impurity of the extension layer is B.
4. The fully isolated LDMOS structure of claim 2, wherein the P-type impurity of the extension layer is implanted with an energy ranging from 50 KeV to 200KeV and an implantation dose ranging from 5e 12E to 5e13cm-2。
5. The fully isolated LDMOS structure of claim 4, wherein an implantation peak of the N-type buried layer is larger than an implantation peak of the P-type impurity of the extension layer, and an implantation dose of the N-type impurity is in a range of 5e 12-5 e13cm-2。
6. A method for manufacturing a completely isolated lateral diffusion metal oxide semiconductor structure comprises the following steps:
providing a first doping type substrate;
forming a second doping type buried layer in the first doping type substrate in a mode of injecting second type impurities;
forming an extension layer in the second doping type buried layer by injecting first type impurities, wherein the buried layer and the extension layer can be formed by high-energy injection in sequence and then driven and trapped together by a strong furnace tube;
epitaxially growing an epitaxial layer on the first doping type substrate;
forming a main structure and an isolation ring on the epitaxial layer; the second doping type buried layer and the isolation ring together isolate the main structure.
7. The method as claimed in claim 6, wherein the first doped type substrate is a P-type substrate, the second doped type buried layer is an N-type buried layer, and the extension layer of the first doped type is P-type doped.
8. The method as claimed in claim 7, wherein the dopant of the N-type buried layer is P, and the P-type dopant of the extension layer is B.
9. The method as claimed in claim 7, wherein the P-type dopant of the extension layer is implanted with an energy of 50-200 KeV and an implantation dose of 5e 12-5 e13cm-2。
10. The method as claimed in claim 9, wherein the peak implantation value of the N-type buried layer is greater than the peak implantation value of the P-type impurity of the extension layer, and the implantation dosage of the N-type impurity is in the range of 5e 12-5 e13cm-2。
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710533760.2A CN109216431B (en) | 2017-07-03 | 2017-07-03 | Completely isolated lateral diffusion metal oxide semiconductor structure and manufacturing method thereof |
| PCT/CN2018/094299 WO2019007331A1 (en) | 2017-07-03 | 2018-07-03 | Fully-isolated laterally-diffused metal oxide semiconductor structure and manufacturing method therefor |
Applications Claiming Priority (1)
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| CN103531631A (en) * | 2012-06-29 | 2014-01-22 | 飞思卡尔半导体公司 | Semiconductor device and driver circuit with a current carrying region and isolation structure interconnected through a resistor circuit, and method of manufacture thereof |
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| KR100859701B1 (en) * | 2002-02-23 | 2008-09-23 | 페어차일드코리아반도체 주식회사 | High voltage LDMOS transistor and method for fabricating the same |
| KR101196319B1 (en) * | 2011-01-24 | 2012-11-01 | 주식회사 동부하이텍 | Lateral double diffused metal oxide semiconductor and method for fabricating the same |
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| CN103531631A (en) * | 2012-06-29 | 2014-01-22 | 飞思卡尔半导体公司 | Semiconductor device and driver circuit with a current carrying region and isolation structure interconnected through a resistor circuit, and method of manufacture thereof |
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