CN102157560A - High-voltage LDMOS (landscape diffusion metal oxide semiconductor) device - Google Patents

High-voltage LDMOS (landscape diffusion metal oxide semiconductor) device Download PDF

Info

Publication number
CN102157560A
CN102157560A CN2011100502220A CN201110050222A CN102157560A CN 102157560 A CN102157560 A CN 102157560A CN 2011100502220 A CN2011100502220 A CN 2011100502220A CN 201110050222 A CN201110050222 A CN 201110050222A CN 102157560 A CN102157560 A CN 102157560A
Authority
CN
China
Prior art keywords
type semiconductor
district
ldmos device
region
drift region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2011100502220A
Other languages
Chinese (zh)
Other versions
CN102157560B (en
Inventor
方健
陈吕赟
管超
王泽华
吴琼乐
柏文斌
杨毓俊
黎俐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Electronic Science and Technology of China
Original Assignee
University of Electronic Science and Technology of China
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Electronic Science and Technology of China filed Critical University of Electronic Science and Technology of China
Priority to CN201110050222A priority Critical patent/CN102157560B/en
Publication of CN102157560A publication Critical patent/CN102157560A/en
Application granted granted Critical
Publication of CN102157560B publication Critical patent/CN102157560B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention relates to a high-voltage LDMOS (landscape diffusion metal oxide semiconductor) device which comprises a substrate, an epitaxial layer, a drift region, a drain region, a source region and at least one pair of n-type semiconductor regions and p-type semiconductor regions, wherein the epitaxial layer is positioned above the substrate; the drift region is positioned on one side, close to the drain region, of the epitaxial layer, and the lower surface of the drift region is coincided with the lower surface of the epitaxial layer; the drain region and the source region are positioned at two ends of the LDMOS device; at least one pair of the n-type semiconductor regions and the p-type semiconductor regions are arrayed alternatively, pass through the lower surface of the epitaxial layer on the border surface of the substrate and the epitaxial layer; the border surface of the n-type semiconductor regions and the p-type semiconductor regions is in parallel with the surface voltage drop direction of a power device in working; and the n-type semiconductor regions and the p-type semiconductor regions are arrayed closely, thus a PN junction is formed. The invention has the beneficial effects that the n-type semiconductor regions and the p-type semiconductor regions provided by the invention are named a bulk reduced surface field layer, and the contradiction of improving the reverse withstand voltage and reducing the positive conduction resistance of the existing LDMOS device is solved effectively by the LDMOS device with the bulk reduced surface field layer.

Description

A kind of high-voltage LDMOS device
Technical field
The present invention relates to the semiconductor high pressure low-resistance device in the electronic technology field, relate in particular to the high voltage power device of on body silicon, making.
Background technology
Fast development along with semicon industry, PIC (Power Integrated Circuit, power integrated circuit) constantly in a plurality of fields, uses, as Electric Machine Control, the flat panel display drive controlling, drive controlling of computer peripheral equipment or the like, in the PIC circuit in the employed power device, LDMOS (Lateral Double Diffused MOSFET, the lateral double diffusion metal oxide semiconductor field effect transistor) high tension apparatus has the operating voltage height, technology is simple, be easy to same low voltage CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductors (CMOS)) circuit characteristics such as compatibility and be subjected to extensive concern on technology.But for the semiconductor high voltage power device made from Si (silicon) material, the forward conduction resistance of LDMOS device is than VDMOS (Vertical Double Diffused MOSFET, the vertical DMOS field-effect transistor) big, and bigger forward conduction resistance has caused the increase of device size, thereby has increased manufacturing cost.Fig. 1 is the conventional LDMOS device architecture schematic diagram of N extension, and among the figure, the LDMOS device comprises substrate 1, epitaxial loayer 2, drift region 3, drain region 4, well region 5, source region 6, drain electrode 7, source electrode 8, grid 9, and substrate 1 is the p type, and epitaxial loayer 2 is the n type.When the LDMOS device was the n type, well region 5 was the p type, and drift region 3 is n -Type, drain region 4, source region 6 are n +Type, otherwise; When the LDMOS device was the p type, well region 5 was the n type, and drift region 3 is p -Type, drain region 4, source region 6 are p +Type.Fig. 2 is the conventional N raceway groove LDMOS device architecture schematic diagram of P extension, and among the figure, the LDMOS device comprises substrate 1, epitaxial loayer 2, drift region 3, drain region 4, source region 6, drain electrode 7, source electrode 8, grid 9, and substrate 1, epitaxial loayer 2 are the p type, and drift region 3 is n -Type, drain region 4, source region 6 are n +Type, drain electrode 7, source electrode 8, grid 9 are metal electrode.Fig. 3 is the conventional P raceway groove LDMOS device architecture schematic diagram of P extension, among the figure, the LDMOS device comprises substrate 1, epitaxial loayer 2, drift region 3, drain region 4, well region 5, source region 6, drain electrode 7, source electrode 8, grid 9, and substrate 1, epitaxial loayer 2 are the p type, well region 5 is the n type, and drift region 3 is p -Type, drain region 4, source region 6 are p +Type.Be used to bear withstand voltage drift region 3 needs low concentration dopings in the LDMOS device, but then, conducting resistance when reducing LDMOS device forward conduction requires to have high-dopant concentration as the drift region 3 of current channel again, and this has just formed puncture voltage BV and conducting resistance R OnBetween contradiction.With common MOS (Metal-Oxide-Semiconductor, Metal-oxide-semicondutor) device is example, and its physical relationship formula is as follows:
R on = L D qμ n N D = 5.39 × 10 - 9 ( BV ) 2.5 (for N type MOS)
R on = L D qμ p N D = 1.63 × 10 - 8 ( BV ) 2.5 (for P type MOS)
Wherein, L DBe drift region length, N DBe drift region concentration, μ nAnd μ pBe respectively the mobility in electronics and hole, q is an electron charge.This shows that the conducting resistance of MOS device is directly proportional with drift region length, be inversely proportional to its concentration.Length is short more, and concentration is high more, and then conducting resistance is more little, because the LDMOS device is a kind of in the MOS device, so the LDMOS device has the universal performance of MOS device.Therefore certain withstand voltage in order to guarantee, the length of the drift region 3 of LDMOS device can not be done too shortly; Its concentration can not be De Taigao, otherwise can puncture near the PN junction of 9 times well regions 5 of grid, makes the reverse withstand voltage reduction of LDMOS device.
Summary of the invention
The objective of the invention is to improve contradiction oppositely withstand voltage and reduction forward conduction resistance, a kind of high-voltage LDMOS device is provided in order to solve existing LDMOS device.
To achieve these goals, technical scheme of the present invention is a kind of high-voltage LDMOS device, comprise substrate, be positioned at the epitaxial loayer on the substrate, be positioned at the drift region of leaning on drain region one side and lower surface to overlap on the epitaxial loayer with the lower surface of epitaxial loayer, be positioned at the drain region and the source region at LDMOS device two ends, the lower surface that strides across epitaxial loayer on the interface of substrate and epitaxial loayer has at least one pair of the n N-type semiconductor N district and the p N-type semiconductor N district of alternately arranging, surface electrical pressure drop direction when the interface in n N-type semiconductor N district and p N-type semiconductor N district is worked with described power device is parallel, and be close to arrangement and form PN junction mutually in described n N-type semiconductor N district and p N-type semiconductor N district.
The invention has the beneficial effects as follows: n N-type semiconductor N district among the present invention and p N-type semiconductor N district also are collectively referred to as and reduce surface field (RESURF) floor in the body, this LDMOS device with the interior reduction of body surface field layer has effectively solved existing LDMOS device and has improved contradiction oppositely withstand voltage and reduction forward conduction resistance, thereby under identical oppositely withstand voltage situation, can effectively reduce forward conduction resistance, perhaps under the situation of identical forward conduction resistance, can effectively improve oppositely withstand voltage.
Description of drawings
Fig. 1 is the LDMOS device architecture schematic diagram of the routine of N extension.
Fig. 2 is the N raceway groove LDMOS device architecture schematic diagram of the routine of P extension.
Fig. 3 is the P raceway groove LDMOS device architecture schematic diagram of the routine of P extension.
Fig. 4 is the LDMOS device architecture schematic diagram of the embodiment of the invention one.
Fig. 5 is the LDMOS device architecture schematic diagram of the embodiment of the invention two.
Fig. 6 is the LDMOS device architecture schematic diagram of the embodiment of the invention three.
Fig. 7 is the LDMOS device architecture schematic diagram of the embodiment of the invention four.
Fig. 8 is the LDMOS device architecture schematic diagram of the embodiment of the invention five.
Fig. 9 is the LDMOS device architecture schematic diagram of the embodiment of the invention six.
Figure 10 is the LDMOS device architecture schematic diagram of the embodiment of the invention seven.
Figure 11 is the LDMOS device architecture schematic diagram of the embodiment of the invention eight.
Description of reference numerals: substrate 1, epitaxial loayer 2, drift region 3, drain region 4, well region 5, source region 6, drain electrode 7, source electrode 8, grid 9, n N-type semiconductor N district 10, p N-type semiconductor N district 11, top buried regions 12.
Embodiment
The present invention is described further below in conjunction with the drawings and specific embodiments.
Embodiment one: as shown in Figure 4, the LDMOS device comprises substrate 1, epitaxial loayer 2, drift region 3, drain region 4, source region 6, drain electrode 7, source electrode 8, grid 9, the LDMOS device is the N raceway groove LDMOS device of P extension in the present embodiment, so substrate 1, epitaxial loayer 2 are the p type, drift region 3 is n -Type, drain region 4, source region 6 are n +Type, epitaxial loayer 2 is positioned on the substrate 1, drift region 3 is positioned at epitaxial loayer 2 strides across epitaxial loayer 2 by drain region 4 one sides and lower surface lower surface, drain region 4 and source region 6 are positioned at LDMOS device two ends, the lower surface that strides across epitaxial loayer 2 on the interface of substrate 1 and epitaxial loayer 2 has the two pairs of n N-type semiconductor N districts 10 and the p N-type semiconductor N district 11 of alternately arranging, surface electrical pressure drop direction when the interface in n N-type semiconductor N district 10 and p N-type semiconductor N district 11 is worked with described power device is parallel, length is consistent with drift region 3 length, and be close to arrangement and form PN junction mutually in n N-type semiconductor N district 10 and p N-type semiconductor N district 11.
N N-type semiconductor N district 11 and p N-type semiconductor N district 12 can set logarithm, shape, width, length and doping content as required arbitrarily in the present embodiment, and the logarithm among the embodiment, shape, width, length can not be understood that limitation of the invention.
With the present embodiment is that example illustrates operation principle of the present invention:
At first, n N-type semiconductor N district 10 in the present embodiment and p N-type semiconductor N district 11 also are collectively referred to as and reduce surface field (RESURF) floor in the body.During LDMOS device forward conduction, the semiconductor region of the reduction surface field layer identical with drift region 3 doping characteristics constitutes an equivalent resistance in parallel with drift region 3, therefore can effectively reduce the conducting resistance of LDMOS device integral body, thereby reach the purpose that reduces conduction loss.As formula: R On=R Contact+ R Source+ R Channel+ R Drain+ R DriftR Resurf/ (R Drift+ R Resurf) shown in, in the formula, R OnBe conducting resistance, R ContactBe contact resistance, R SourceBe source resistance, R ChannelBe channel resistance, R Drift=ρ dL DriftBe drift zone resistance, R DrainBe drain region resistance, R ResurfBe the resistance that reduces the surface field layer, ρ dBe the epilayer resistance rate, L DriftBe drift region length.
The LDMOS device is reverse when withstand voltage, the transverse p/n junction that n N-type semiconductor N district 10 that doping characteristic is opposite in the reduction surface field floor and p N-type semiconductor N district 11 form exhausts in the horizontal mutually, and the longitudinal P N knot that semiconductor region opposite with drift region 3 doping characteristics and drift region 3 form exhausts mutually with drift region 3 in the vertical.Transversely, the smooth electric field of body interior reduction surface field layer can influence surface field makes it to become comparatively smooth, has improved the surface withstand voltage of LDMOS device.On vertical simultaneously, semiconductor region opposite with drift region 3 doping characteristics and drift region 3 form PN junctions, can influence the interior longitudinal electric field of body equally and make it to become smooth, thereby improve vertical puncture voltage.In conventional LDMOS device, vertical puncture voltage BV=E in the body C* t Epi, vertical puncture voltage BV is by vertical critical electric field E in the body C(between epitaxial loayer 2 and substrate 1) and epitaxial loayer 2 thickness t EpiDecision.After having increased reduction surface field layer, if will keep identical vertical puncture voltage, then epitaxy layer thickness t EpiCan reduce greatly.When reducing the realization of surface field layer, the doping content N of epitaxial loayer 2 EpiWith thickness t EpiSatisfy formula N Epi* t Epi=ε * E c/ q*sqrt (N Sub/ (N Epi+ N Sub)), ε is a dielectric constant in the formula, q is an electron charge, N SubDoping content for substrate 1.As vertical critical electric field E CWhen determining, N Epi* t EpiCan be considered constant, so when epitaxial loayer 2 thickness t EpiDuring reduction, epitaxial loayer 2 doping content N EpiWill improve.As seen, the structure that present embodiment provides can reduce forward conduction resistance significantly after introducing reduction surface field layer, the conduction loss of device is reduced, and improves the withstand voltage effect of LDMOS device under the situation of identical forward conduction resistance; And when assurance is withstand voltage, can reduce epitaxial loayer 2 thickness, increase drift region concentration, reduce the forward conduction resistance of drift region.
Embodiment two: as shown in Figure 5, on the basis of embodiment one, in order to prevent that PN junction that n N-type semiconductor N district 10 and p N-type semiconductor N district 11 forms from influencing the electric field in drain region 4, the length in n N-type semiconductor N district 10 and p N-type semiconductor N district 11 can foreshorten to the interface place of drain region 4 to center one side and drift region 3.
Embodiment three: as shown in Figure 6, on the basis of embodiment one or embodiment two, in order to prevent that the 11 pairs of source regions 6 in n N-type semiconductor N district 10 and p N-type semiconductor N district from impacting, can be the contraction in length in n N-type semiconductor N district 10 and p N-type semiconductor N district 11 to not linking to each other with the interface of epitaxial loayer 2 to source region 6 one sides with drift region 3.
Embodiment four: as shown in Figure 7, on the basis of embodiment one or embodiment two or embodiment three, in order to regulate the reverse charge balance of n N-type semiconductor N district 10 and p N-type semiconductor N district 11 and drift region 3 when withstand voltage of LDMOS device, it is reached fully as far as possible exhausts, 3 upper surface adds top buried regions (top) 12 in the drift region, and the doping characteristic of described top buried regions 12 is opposite with drift region 3.
Embodiment five: as shown in Figure 8, the LDMOS device comprises substrate 1, epitaxial loayer 2, drift region 3, drain region 4, well region 5, source region 6, drain electrode 7, source electrode 8, grid 9, and the LDMOS device is the N raceway groove LDMOS device of N extension in the present embodiment.Substrate 1, well region 5 are the p type, and epitaxial loayer 2 is the n type, and drift region 3 is n -Type, drain region 4, source region 6 are n +Type, epitaxial loayer 2 is positioned on the substrate 1, the lower surface that drift region 3 is positioned at close drain region 4 one sides of epitaxial loayer and drift region 3 overlaps with the interface of substrate 1 and epitaxial loayer 2, drain region 4 and source region 6 are positioned at LDMOS device two ends, the lower surface that strides across epitaxial loayer 2 on the interface of substrate 1 and epitaxial loayer 2 has the two pairs of n N-type semiconductor N districts 10 and the p N-type semiconductor N district 11 of alternately arranging, surface electrical pressure drop direction when the interface in n N-type semiconductor N district 10 and p N-type semiconductor N district 11 is worked with described power device is parallel, length extends to the drain terminal below from source end below always, and be close to arrangement and form PN junction mutually in n N-type semiconductor N district 10 and p N-type semiconductor N district 11.The operation principle of present embodiment is identical with embodiment one.
N N-type semiconductor N district 11 and p N-type semiconductor N district 12 also can set logarithm, shape, width, length and doping content arbitrarily as required in the present embodiment, and the logarithm among the embodiment, shape, width, length can not be understood that limitation of the invention.
Embodiment six: as shown in Figure 9, on the basis of embodiment five, in order to prevent that PN junction that n N-type semiconductor N district 10 and p N-type semiconductor N district 11 forms from influencing the electric field in drain region 4, the length in n N-type semiconductor N district 10 and p N-type semiconductor N district 11 can foreshorten to the interface of drain region 4 to center one side and drift region 3.
Embodiment seven: as shown in figure 10, impact in order to prevent the 11 pairs of source regions 6 in n N-type semiconductor N district 10 and p N-type semiconductor N district, can the contraction in length in n N-type semiconductor N district 10 and p N-type semiconductor N district 11 to the source region 6 interfaces to center one side and well region 5.
Embodiment eight: as shown in figure 11, on the basis of embodiment five or embodiment six or embodiment seven, in order to regulate the reverse charge balance of n N-type semiconductor N district 10 and p N-type semiconductor N district 11 and drift region 3 when withstand voltage of LDMOS device, it is reached fully as far as possible exhausts, 3 upper surface adds top buried regions (top) 12 in the drift region, and the doping characteristic of described top buried regions 12 is opposite with drift region 3.
Those of ordinary skill in the art will appreciate that embodiment described here is in order to help reader understanding's principle of the present invention, should to be understood that protection scope of the present invention is not limited to such special statement and embodiment.Those of ordinary skill in the art can make various other various concrete distortion and combinations that do not break away from essence of the present invention according to these technology enlightenments disclosed by the invention, and these distortion and combination are still in protection scope of the present invention.

Claims (9)

1. high-voltage LDMOS device, comprise substrate (1), be positioned at the epitaxial loayer (2) on the substrate (1), be positioned at the drift region (3) of leaning on drain region (4) one sides and lower surface to overlap on the epitaxial loayer (2) with the lower surface of epitaxial loayer (2), be positioned at drain region (4) and source region (6) at LDMOS device two ends, it is characterized in that, the lower surface that strides across epitaxial loayer (2) on the interface of substrate (1) and epitaxial loayer (2) has at least one pair of the n N-type semiconductor N district (10) and the p N-type semiconductor N district (11) of alternately arranging, surface electrical pressure drop direction when the interface in n N-type semiconductor N district (10) and p N-type semiconductor N district (11) is worked with described power device is parallel, and be close to arrangement and form PN junction mutually in described n N-type semiconductor N district (10) and p N-type semiconductor N district (11).
2. a kind of high-voltage LDMOS device according to claim 1 is characterized in that, described high-voltage LDMOS device is the N raceway groove LDMOS device of P extension.
3. a kind of high-voltage LDMOS device according to claim 2 is characterized in that, the length in described n N-type semiconductor N district (10) and p N-type semiconductor N district (11) can foreshorten to the interface place of drain region (4) to center one side and drift region (3).
4. a kind of high-voltage LDMOS device according to claim 2 is characterized in that, the contraction in length in described n N-type semiconductor N district (10) and p N-type semiconductor N district (11) is to not linking to each other with the interface of epitaxial loayer (2) to source region (6) one sides with drift region (3).
5. a kind of high-voltage LDMOS device according to claim 2 is characterized in that, the upper surface of (3) adds top buried regions (12) in the drift region, and the doping characteristic of described top buried regions (12) is opposite with drift region (3).
6. a kind of high-voltage LDMOS device according to claim 1 is characterized in that, described high-voltage LDMOS device is the N raceway groove LDMOS device of N extension.
7. a kind of high-voltage LDMOS device according to claim 6 is characterized in that, the length in described n N-type semiconductor N district (10) and p N-type semiconductor N district (11) can foreshorten to the interface place of drain region (4) to center one side and drift region (3).
8. a kind of high-voltage LDMOS device according to claim 6 is characterized in that, the contraction in length in described n N-type semiconductor N district (10) and p N-type semiconductor N district (11) to the source region (6) to the interface place of center one side and well region (5).
9. a kind of high-voltage LDMOS device according to claim 6 is characterized in that, the upper surface of (3) adds top buried regions (12) in the drift region, and the doping characteristic of described top buried regions (12) is opposite with drift region (3).
CN201110050222A 2011-03-02 2011-03-02 High-voltage LDMOS (landscape diffusion metal oxide semiconductor) device Expired - Fee Related CN102157560B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201110050222A CN102157560B (en) 2011-03-02 2011-03-02 High-voltage LDMOS (landscape diffusion metal oxide semiconductor) device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201110050222A CN102157560B (en) 2011-03-02 2011-03-02 High-voltage LDMOS (landscape diffusion metal oxide semiconductor) device

Publications (2)

Publication Number Publication Date
CN102157560A true CN102157560A (en) 2011-08-17
CN102157560B CN102157560B (en) 2012-09-12

Family

ID=44438892

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110050222A Expired - Fee Related CN102157560B (en) 2011-03-02 2011-03-02 High-voltage LDMOS (landscape diffusion metal oxide semiconductor) device

Country Status (1)

Country Link
CN (1) CN102157560B (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102427077A (en) * 2011-12-02 2012-04-25 日银Imp微电子有限公司 High-voltage isolation ring structure used in bridge type driving circuit
WO2012065514A1 (en) * 2010-11-19 2012-05-24 Csmc Technologies Fab1 Co., Ltd Ldmos device and method for fabricating the same
CN102709325A (en) * 2012-06-25 2012-10-03 电子科技大学 High-voltage lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS) device
CN102790092A (en) * 2012-08-24 2012-11-21 电子科技大学 Transverse high-voltage DMOS (double-diffusion metal oxide semiconductor) device
CN103066109A (en) * 2011-10-18 2013-04-24 旺宏电子股份有限公司 Semiconductor structure and formation method thereof
CN103091533A (en) * 2011-11-03 2013-05-08 上海华虹Nec电子有限公司 Current sampling circuit achieved by laterally diffused metal oxide semiconductor (LDMOS) devices
CN105762192A (en) * 2014-12-19 2016-07-13 北大方正集团有限公司 Lateral high-voltage semiconductor device
CN106252406A (en) * 2015-06-12 2016-12-21 旺宏电子股份有限公司 There is the semiconductor device of buried regions
CN106876464A (en) * 2016-12-29 2017-06-20 西安电子科技大学 A kind of lateral double diffusion metal oxide semiconductor FET
CN114220847A (en) * 2022-02-22 2022-03-22 北京芯可鉴科技有限公司 LDMOSFET, preparation method, chip and circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5347155A (en) * 1992-05-21 1994-09-13 U.S. Philips Corporation Semiconductor device having a lateral DMOST with breakdown voltage raising zones and provisions for exchanging charge with the back gate region
US6531355B2 (en) * 1999-01-25 2003-03-11 Texas Instruments Incorporated LDMOS device with self-aligned RESURF region and method of fabrication
US20080029814A1 (en) * 2006-08-02 2008-02-07 International Rectifier Corporation Multiple lateral RESURF LDMOST

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5347155A (en) * 1992-05-21 1994-09-13 U.S. Philips Corporation Semiconductor device having a lateral DMOST with breakdown voltage raising zones and provisions for exchanging charge with the back gate region
US6531355B2 (en) * 1999-01-25 2003-03-11 Texas Instruments Incorporated LDMOS device with self-aligned RESURF region and method of fabrication
US20080029814A1 (en) * 2006-08-02 2008-02-07 International Rectifier Corporation Multiple lateral RESURF LDMOST

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012065514A1 (en) * 2010-11-19 2012-05-24 Csmc Technologies Fab1 Co., Ltd Ldmos device and method for fabricating the same
CN103066109B (en) * 2011-10-18 2015-09-30 旺宏电子股份有限公司 Semiconductor structure and forming method thereof
CN103066109A (en) * 2011-10-18 2013-04-24 旺宏电子股份有限公司 Semiconductor structure and formation method thereof
CN103091533A (en) * 2011-11-03 2013-05-08 上海华虹Nec电子有限公司 Current sampling circuit achieved by laterally diffused metal oxide semiconductor (LDMOS) devices
CN103091533B (en) * 2011-11-03 2014-12-10 上海华虹宏力半导体制造有限公司 Current sampling circuit achieved by laterally diffused metal oxide semiconductor (LDMOS) devices
CN102427077A (en) * 2011-12-02 2012-04-25 日银Imp微电子有限公司 High-voltage isolation ring structure used in bridge type driving circuit
CN102427077B (en) * 2011-12-02 2013-11-27 日银Imp微电子有限公司 High-voltage isolation ring structure used in bridge type driving circuit
CN102709325A (en) * 2012-06-25 2012-10-03 电子科技大学 High-voltage lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS) device
CN102790092A (en) * 2012-08-24 2012-11-21 电子科技大学 Transverse high-voltage DMOS (double-diffusion metal oxide semiconductor) device
CN105762192A (en) * 2014-12-19 2016-07-13 北大方正集团有限公司 Lateral high-voltage semiconductor device
CN105762192B (en) * 2014-12-19 2019-01-29 北大方正集团有限公司 Lateral high-voltage semi-conductor device
CN106252406A (en) * 2015-06-12 2016-12-21 旺宏电子股份有限公司 There is the semiconductor device of buried regions
CN106252406B (en) * 2015-06-12 2019-03-15 旺宏电子股份有限公司 Semiconductor device with buried layer
CN106876464A (en) * 2016-12-29 2017-06-20 西安电子科技大学 A kind of lateral double diffusion metal oxide semiconductor FET
CN114220847A (en) * 2022-02-22 2022-03-22 北京芯可鉴科技有限公司 LDMOSFET, preparation method, chip and circuit

Also Published As

Publication number Publication date
CN102157560B (en) 2012-09-12

Similar Documents

Publication Publication Date Title
CN101969074B (en) High voltage lateral double diffused MOSFET element
CN102157560B (en) High-voltage LDMOS (landscape diffusion metal oxide semiconductor) device
US8890280B2 (en) Trench-type semiconductor power devices
CN104201206B (en) A kind of laterally SOI power LDMOS device
CN103715238B (en) A kind of lateral high-voltage device of Ultra-low Specific conducting resistance
CN102376762B (en) Super junction LDMOS(Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof
CN103915506B (en) A kind of double grid LDMOS device with longitudinal NPN structure
CN106816468B (en) Lateral diffusion metal oxide semiconductor field effect transistor with RESURF structure
KR101755718B1 (en) Lateral Double diffusion Metal-Oxide_Semiconductor device and method for manufacturing the same
CN102306659B (en) LDMOS (laterally double-diffused metal-oxide-semiconductor field effect transistor) device based on internal electric field modulation
CN107564965B (en) Transverse double-diffusion MOS device
CN102709325A (en) High-voltage lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS) device
CN107799580A (en) Diode, junction field effect transistor and semiconductor device
CN102263125B (en) Power MOS (metal oxide semiconductor) component for transversely diffusing metallic oxides
CN106571388A (en) Crosswise diffusion metal oxide semiconductor field effect tube possessing RESURF structure
CN107275388A (en) A kind of lateral high-voltage device
CN101980364B (en) Thin-layer SOI composite power device
CN107546274B (en) LDMOS device with step-shaped groove
CN102637744B (en) Signal operation instruction (SOI) transverse super junction power metal oxide semiconductor field effect transistor (MOSFET) device
CN101777584B (en) P-channel laterally double diffused metal oxide semiconductor device
CN107425052A (en) A kind of lateral high-voltage device
CN109192777B (en) Deep-groove semi-super-junction structure power device and manufacturing method
CN112186028A (en) Shielding grid MOSFET device integrated with NPN punch-through triode
CN103187443A (en) Lateral double-diffusion metal oxide semiconductor field effect transistor
WO2015145913A1 (en) Semiconductor device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20120912

Termination date: 20150302

EXPY Termination of patent right or utility model