CN114220847A - LDMOSFET, preparation method, chip and circuit - Google Patents
LDMOSFET, preparation method, chip and circuit Download PDFInfo
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- CN114220847A CN114220847A CN202210159453.3A CN202210159453A CN114220847A CN 114220847 A CN114220847 A CN 114220847A CN 202210159453 A CN202210159453 A CN 202210159453A CN 114220847 A CN114220847 A CN 114220847A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 7
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 73
- 239000010703 silicon Substances 0.000 claims abstract description 73
- 150000002500 ions Chemical class 0.000 claims abstract description 69
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 17
- 238000005468 ion implantation Methods 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 55
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 5
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 210000000746 body region Anatomy 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
The embodiment of the invention provides an LDMOSFET, a preparation method, a chip and a circuit, wherein the LDMOSFET comprises the following components: the device comprises a substrate, wherein an epitaxial layer is arranged on the substrate; a first heavily doped N + ion, P-type silicon, N-type silicon and a second heavily doped N + ion are sequentially arranged above the epitaxial layer; the P-type silicon is provided with lightly doped N-type ions, and the N-type silicon is provided with lightly doped P-type ions. The LDMOSFET does not need high-energy ion implantation, and has the characteristics of simple process and low cost.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to an LDMOSFET, a preparation method, a chip and a circuit.
Background
LDMOSFET devices are often used in various applications, such as automotive applications. The prior art often prevents breakdown from high voltage applied to the drain by reducing the surface electric field (RESURF) structure in LDMOSFET devices. Conventional LDMOSFET fabrication processes use HVNW, HVPW, NRF and P-Body implants to form high voltage PN junctions, especially HYNW and HVPW implants with high energy and require long high temperature well drive, which places high demands on lithography processes, ion implantation equipment and diffusion equipment.
Disclosure of Invention
The embodiment of the invention aims to provide an LDMOSFET, a preparation method, a chip and a circuit, wherein the LDMOSFET does not need high-energy ion implantation and has the characteristics of simple process and low cost.
In order to achieve the above object, an embodiment of the present invention provides an LDMOSFET including: the device comprises a substrate, wherein an epitaxial layer is arranged on the substrate; a first heavily doped N + ion, P-type silicon, N-type silicon and a second heavily doped N + ion are sequentially arranged above the epitaxial layer; the P-type silicon is provided with lightly doped N-type ions, and the N-type silicon is provided with lightly doped P-type ions.
Optionally, the lightly doped N-type ions and the lightly doped P-type ions are both distributed in a columnar shape.
Optionally, the P-type silicon and the N-type silicon are connected to form a PN junction.
Optionally, polysilicon is disposed above the LDMOSFET.
Optionally, a thick oxide layer is formed on the N-type silicon, and the thick oxide layer is SiO 2.
Optionally, the substrate is a P-type substrate.
In another aspect, the present invention provides a method for manufacturing an LDMOSFET, including: forming a substrate, wherein an epitaxial layer is formed on the substrate; forming first heavily doped N + ions, P-type silicon, N-type silicon and second heavily doped N + ions above the epitaxial layer in sequence; lightly doped N-type ions are formed in the P-type silicon, and lightly doped P-type ions are formed in the N-type silicon.
Optionally, a thick oxide layer is formed on the N-type silicon, and the thick oxide layer is SiO 2.
Optionally, the lightly doped N-type ions and the lightly doped P-type ions are both distributed in a columnar shape.
Optionally, the P-type silicon and the N-type silicon are connected to form a PN junction.
In another aspect, the invention provides a chip, which includes the LDMOSFET described above.
In another aspect, the present invention further provides a circuit, which includes the LDMOSFET described above.
The LDMOSFET provided by the invention comprises: the device comprises a substrate, wherein an epitaxial layer is arranged on the substrate; a first heavily doped N + ion, P-type silicon, N-type silicon and a second heavily doped N + ion are sequentially arranged above the epitaxial layer; the P-type silicon is provided with lightly doped N-type ions, and the N-type silicon is provided with lightly doped P-type ions. The LDMOSFET does not need high-energy ion implantation, and has the characteristics of simple process and low cost.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
fig. 1-5 are schematic diagrams of a method for fabricating an LDMOSFET according to the present invention.
Description of the reference numerals
100-a substrate;
101-an epitaxial layer;
102-P type silicon;
200-N type silicon;
301-lightly doping N-type ions;
302-lightly doped P-type ions;
400-silicon dioxide;
500-polysilicon.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating embodiments of the invention, are given by way of illustration and explanation only, not limitation.
The present invention provides an LDMOSFET, as shown in fig. 5, which includes: the substrate 100, the substrate 100 is preferably a P-type substrate, and an epitaxial layer 101 is arranged on the substrate 100; the epitaxial layer 101 is sequentially provided with first heavily doped N + ions, P-type silicon 102, N-type silicon 200 and second heavily doped N + ions, the first heavily doped N + ions and the second heavily doped N + ions are arranged on two sides of the P-type silicon 102 and the N-type silicon 200, the doping concentrations of the first heavily doped N + ions and the second heavily doped N + ions are the same, and the first heavily doped N + ions and the second heavily doped N + ions are used for increasing the width of a depletion layer. According to a preferred embodiment, the concentration of heavy doping is in the range of 5e 19-3 e20/cm 3.
The P-type silicon 102 is provided with lightly doped N-type ions 301, the N-type silicon 200 is provided with lightly doped P-type ions 302, preferably, the lightly doped N-type ions 301 and the lightly doped P-type ions 302 are both distributed in a columnar shape, the specific distribution density and ion concentration can be determined according to the breakdown voltage, according to a preferred embodiment, the distribution density is 1-1.5 um/1, the ion concentration of the lightly doped N-type ions 301 and the lightly doped P-type ions 302 is 1e 15-1 e16, and the breakdown voltage range is tens of volts to hundreds of volts.
The lightly doped N-type ions 301 and the P-type silicon 102 form a super PN junction, so that the conduction current and the breakdown voltage are reduced, and similarly, the lightly doped P-type ions 302 and the N-type silicon 200 form a super PN junction, so that the conduction current and the breakdown voltage are reduced. And the P-type silicon 102 and the N-type silicon 200 are connected to form a PN junction for reducing the breakdown voltage.
The LDMOSFET has no high-energy ion implantation such as high-energy HVPW (high-voltage N well region), HVNW (high-voltage P well region), NRF (N type drift region) and P-Body (N type Body region), does not need a photoetching technology, and does not need a long-time high-temperature drive well in the manufacturing process, so the LDMOSFET has the characteristics of simple and practical process, low production cost and the like.
The invention also provides a preparation method of the LDMOSFET, which comprises the following steps: forming a substrate 100, and forming an epitaxial layer 101 on the substrate 100; a first heavily doped N + ion, P-type silicon 102, N-type silicon 200 and a second heavily doped N + ion are sequentially formed above the epitaxial layer 101; lightly doped N-type ions 301 are formed in the P-type silicon 102, and lightly doped P-type ions 302 are formed in the N-type silicon 200. Photoresist is implanted in advance before the lightly doped N-type ions 301 are implanted into the P-type silicon 102 and before the lightly doped P-type ions 302 are implanted into the N-type silicon 200. Preferably, the lightly doped N-type ions 301 and the lightly doped P-type ions 302 are both distributed in a columnar shape. The P-type silicon 102 and the N-type silicon 200 are connected to form a PN junction.
Fig. 1-5 are schematic diagrams of a method for fabricating an LDMOSFET according to the present invention, specifically, as shown in fig. 1, a substrate 100 (SOI) with a desired thickness and concentration is customized, and an epitaxial layer 101 may be further grown on the substrate 100 to meet the thickness and concentration requirements, and a layer of P-type silicon 102 is grown on the epitaxial layer 101.
Next, a certain region is photoetched for the P-type silicon 102 in fig. 1, the region is implanted with N-type ions to form N-type silicon 200, and then photoetching is performed again to dry-etch away the region where silicon is not needed, so as to form the structure shown in fig. 2.
Then, lightly doped P-type ions 302 are implanted into the N-type silicon 200 by photolithography, and then lightly doped N-type ions 301 are implanted into the P-type silicon 102 by photolithography, so as to form the structure shown in fig. 3.
As shown in fig. 4, CVD SiO2 and photolithography are performed on the LDMOSFET in fig. 3, SiO2 is dry etched, and then diffused, so that N + doped source and drain regions are formed on the side surfaces of the P-type silicon 102 and the N-type silicon 200 for increasing the width of the depletion layer.
As shown in fig. 5, CVD SiO2 is partially removed next, the remaining CVD SiO2 is used for a thick oxide layer on N-type silicon 200 to increase isolation effect, then a Gate oxidation process is performed on P-type silicon 102 and a small portion of N-type silicon 200, and finally LPCVD Poly and doping, Gate oxide (Poly Gate) lithography and dry etching are performed to form the final LDMOSFET.
The LDMOSFET provided by the invention comprises: the structure comprises a substrate 100, wherein an epitaxial layer 101 is arranged on the substrate 100; a first heavily doped N + ion, P-type silicon 102, N-type silicon 200 and a second heavily doped N + ion are sequentially arranged above the epitaxial layer 101; the P-type silicon 102 is provided with lightly doped N-type ions 301, and the N-type silicon 200 is provided with lightly doped P-type ions 302. The lightly doped N-type ions 301 form a super PN junction with the P-type silicon 102, and the lightly doped P-type ions 302 form a super PN junction with the N-type silicon 200, both of which reduce the on-current and breakdown voltage. The LDMOSFET has no high-energy ion implantation such as high-energy HVPW (high-voltage N well region), HVNW (high-voltage P well region), NRF (N type drift region) and P-Body (N type Body region), does not need a photoetching technology, does not need a long-time high-temperature drive well in the manufacturing process, and has the characteristics of simple and practical process, low production cost and the like.
Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, the embodiments of the present invention are not limited to the details of the above embodiments, and various simple modifications can be made to the technical solutions of the embodiments of the present invention within the technical idea of the embodiments of the present invention, and the simple modifications all belong to the protection scope of the embodiments of the present invention.
It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, the embodiments of the present invention do not describe every possible combination.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.
The above are merely examples of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (12)
1. An LDMOSFET, comprising:
the device comprises a substrate, wherein an epitaxial layer is arranged on the substrate;
a first heavily doped N + ion, P-type silicon, N-type silicon and a second heavily doped N + ion are sequentially arranged above the epitaxial layer;
the P-type silicon is provided with lightly doped N-type ions, and the N-type silicon is provided with lightly doped P-type ions.
2. The LDMOSFET of claim 1,
the lightly doped N-type ions and the lightly doped P-type ions are both distributed in a columnar shape.
3. The LDMOSFET of claim 1,
the P-type silicon and the N-type silicon are connected to form a PN junction.
4. The LDMOSFET of claim 1,
and polycrystalline silicon is arranged above the LDMOSFET.
5. The LDMOSFET of claim 1,
and forming a thick oxidation layer on the N-type silicon, wherein the thick oxidation layer is SiO 2.
6. The LDMOSFET of claim 1,
the substrate is a P-type substrate.
7. A preparation method of an LDMOSFET is characterized by comprising the following steps:
forming a substrate, wherein an epitaxial layer is formed on the substrate;
forming first heavily doped N + ions, P-type silicon, N-type silicon and second heavily doped N + ions above the epitaxial layer in sequence;
lightly doped N-type ions are formed in the P-type silicon, and lightly doped P-type ions are formed in the N-type silicon.
8. The production method according to claim 7,
and forming a thick oxidation layer on the N-type silicon, wherein the thick oxidation layer is SiO 2.
9. The production method according to claim 7,
the lightly doped N-type ions and the lightly doped P-type ions are both distributed in a columnar shape.
10. The production method according to claim 7,
the P-type silicon and the N-type silicon are connected to form a PN junction.
11. A chip comprising an LDMOSFET as claimed in any one of claims 1 to 6.
12. A circuit comprising an LDMOSFET as claimed in any one of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210159453.3A CN114220847B (en) | 2022-02-22 | 2022-02-22 | LDMOSFET, preparation method, chip and circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210159453.3A CN114220847B (en) | 2022-02-22 | 2022-02-22 | LDMOSFET, preparation method, chip and circuit |
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| Publication Number | Publication Date |
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| CN114220847A true CN114220847A (en) | 2022-03-22 |
| CN114220847B CN114220847B (en) | 2022-05-17 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW434903B (en) * | 1999-12-02 | 2001-05-16 | United Microelectronics Corp | Lateral diffused metal oxide semiconductor transistor |
| CN102097480A (en) * | 2010-12-22 | 2011-06-15 | 东南大学 | N-type super-junction transverse double-diffusion metal oxide semiconductor tube |
| CN102157560A (en) * | 2011-03-02 | 2011-08-17 | 电子科技大学 | High-voltage LDMOS (landscape diffusion metal oxide semiconductor) device |
| US20130214355A1 (en) * | 2010-10-28 | 2013-08-22 | University Of Electronic Science And Technology Of China | High voltage ldmos device |
| CN103515432A (en) * | 2012-06-21 | 2014-01-15 | 上海华虹Nec电子有限公司 | P-type super node lateral double diffusion MOSFET device |
| CN103915506A (en) * | 2014-04-28 | 2014-07-09 | 重庆大学 | Double-gate LDMOS device with longitudinal NPN structure |
-
2022
- 2022-02-22 CN CN202210159453.3A patent/CN114220847B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW434903B (en) * | 1999-12-02 | 2001-05-16 | United Microelectronics Corp | Lateral diffused metal oxide semiconductor transistor |
| US20130214355A1 (en) * | 2010-10-28 | 2013-08-22 | University Of Electronic Science And Technology Of China | High voltage ldmos device |
| CN102097480A (en) * | 2010-12-22 | 2011-06-15 | 东南大学 | N-type super-junction transverse double-diffusion metal oxide semiconductor tube |
| CN102157560A (en) * | 2011-03-02 | 2011-08-17 | 电子科技大学 | High-voltage LDMOS (landscape diffusion metal oxide semiconductor) device |
| CN103515432A (en) * | 2012-06-21 | 2014-01-15 | 上海华虹Nec电子有限公司 | P-type super node lateral double diffusion MOSFET device |
| CN103915506A (en) * | 2014-04-28 | 2014-07-09 | 重庆大学 | Double-gate LDMOS device with longitudinal NPN structure |
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| CN114220847B (en) | 2022-05-17 |
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