CN107275388A - A kind of lateral high-voltage device - Google Patents
A kind of lateral high-voltage device Download PDFInfo
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- CN107275388A CN107275388A CN201710496712.0A CN201710496712A CN107275388A CN 107275388 A CN107275388 A CN 107275388A CN 201710496712 A CN201710496712 A CN 201710496712A CN 107275388 A CN107275388 A CN 107275388A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 20
- 229920005591 polysilicon Polymers 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 17
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims 1
- 230000009467 reduction Effects 0.000 abstract description 9
- 238000010586 diagram Methods 0.000 description 11
- 230000015556 catabolic process Effects 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000005684 electric field Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7394—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
Abstract
The present invention provides a kind of lateral high-voltage device, including media slot, lower section, left side, at least one position of right side of media slot are provided with the doping bar overlapping configuration that different doping types are arranged alternately, also include oxide layer, the first N-type heavily doped region, the second N-type heavily doped region, p-type heavily doped region under dielectric layer, body field plate, polysilicon gate, grid, p-well region, the first n-type doping article, the second n-type doping article, the 3rd n-type doping article, the doping article of the first p-type, the doping article of the second p-type, the bottom of conductive path is P type substrate；The present invention reduces device surface area by introducing media slot in drift region while retainer member is pressure-resistant, effectively reduction device compares conducting resistance；The heavy doping N bars and heavy doping P bars of stacking are introduced in device drift region, low resistance conductive path is provided for device ON state, further reduction device is finally reached than conducting resistance and effectively reduces device area, reduces the purpose of conducting resistance.
Description
Technical field
The invention belongs to semiconductor power device technology field, and in particular to a kind of lateral high-voltage device.
Background technology
Lateral double diffused metal-Oxide-Semiconductor Field effect transistor (Lateral Double-diffused
Metal-Oxide-Semiconductor Field Effect Transistor, LDMOSFET) it is used as power integrated circuit
Core devices in (Power Integrated Circuit, PIC), with small, negative temperature coefficient of easy of integration, driving power etc.
Advantage, for many years always towards high-breakdown-voltage (Breakdown Voltage, BV) and low than conducting resistance (Specific
On-Resistance, Ron, sp) direction develop.Higher breakdown voltage need device have longer drift region length and
Relatively low drift doping concentration, this causes device to have higher conducting resistance.Breakdown voltage and than between conducting resistance
This contradictory relation, exactly perplexs " the silicon limit " problem of industry.
In order to alleviate this contradiction, make device while having high withstand voltage with low than conducting resistance, researcher is horizontal in LDMOS
Media slot is introduced in drift region.Media slot shortens lateral device dimensions while can bearing most of laterally pressure-resistant, significantly
The area of degree reduction chip.But it is still more larger than conducting resistance by traditional media slot LDMOS, fail further to alleviate pressure-resistant
With the contradiction than conducting resistance.
The content of the invention
The shortcoming of prior art in view of the above, the present invention proposes a kind of lateral high-voltage device, it is therefore intended that keep
Reduction device compares conducting resistance while device high breakdown voltage.
For achieving the above object, technical solution of the present invention is as follows：
A kind of lateral high-voltage device, including：Media slot, lower section, left side, at least one position of right side of media slot are provided with not
The doping bar overlapping configuration being arranged alternately with doping type, the upper surface of media slot is dielectric layer, and body field plate is from device upper surface
Extend to the inside of media slot, body field plate is bordered by below polysilicon gate, polysilicon gate being oxide layer under grid, Source contact electrode and
Polysilicon gate is isolated by dielectric layer, and body field plate and drain contact electrode are isolated by dielectric layer, is below drain contact electrode
It is adjacent p-type heavily doped region and the first N-type heavily doped region below second N-type heavily doped region, Source contact electrode, p-type is heavily doped
Miscellaneous area and the first N-type heavily doped region are located at the inner upper of p-well region, and dielectric layer is located at the top of p-well region, the both sides of media slot and
Bottom is respectively equipped with the conductive path that the first n-type doping article, the second n-type doping article, the 3rd n-type doping article are constituted, conductive path
Both sides there is the first p-type to adulterate bar, the second p-type doping bar respectively, the bottom of conductive path is P type substrate；If the bar that adulterates is handed over
Stack structure adulterates article overlapping configuration successively including the 3rd n-type doping article, the doping article of the 3rd p-type, the 6th N below media slot, then
Type doping bar；If adulterating bar overlapping configuration on the right side of media slot, doping bar overlapping configuration includes the second n-type doping successively
Article, the doping article of the second p-type, the 7th n-type doping article, and the doping article of the n-type doping article, p-type and n-type doping article upper surface and the
Two N-type heavily doped regions are in contact；If doping bar overlapping configuration is on the left of media slot, doping article overlapping configuration includes the successively
One n-type doping article, the doping article of the first p-type, the 5th n-type doping article, and doping article has the 4th N-type between overlapping configuration and p-well region
Adulterate bar.
The total technical scheme of the present invention, adds media slot in drift region, and media slot reduces while bearing laterally pressure-resistant
On the other hand, in drift region the size of device, reduction device introduces heavily doped N-type doping bar, is device ON state than conducting resistance
Electronic current provides low resistance conductive path, further reduces device on-resistance；Body field plate, assisted depletion are introduced in media slot
Heavily doped N-type doping bar, raising device is pressure-resistant, and heavily doped P-type doping bar is introduced also in drift region, N-type is exhausted during OFF state and is mixed
While miscellaneous bar, an extra electric field is formed, so as to improve the breakdown voltage of device.
It is preferred that, adjacent n-type doping bar, p-type doping bar are one group, and the overlapping configuration is more than 2 for group number
Multigroup n-type doping bar, the overlapping configuration that is arranged alternately of p-type doping bar.
It is preferred that, the device is SOI device, and substrate is N-type silicon or P-type silicon for SOI device.
It is preferred that, there is epitaxial layer between P type substrate and conductive path, or epitaxial layer is arranged at SOI oxygen buried layers
Between conductive path.
It is preferred that, oxide layer constitutes groove grid under polysilicon gate and grid, and now Source contact electrode and body field plate face
Connect.Conventional shallow slot grid technique is more easy to realize but its border flex point being located inside drift region can cause a peak electric field, holds
Device is easily caused in advance to puncture, it is pressure-resistant not as expected.
It is preferred that, the groove grid that oxide layer is constituted under the polysilicon gate and grid are extended to inside P type substrate, now
Source contact electrode and body field plate are bordered by.Groove grid are accomplished into substrate interior, its border flex point is guided in substrate, elimination is hit in advance
The possibility worn.
It is preferred that, the groove grid that oxide layer is constituted under the polysilicon gate and grid are located inside media slot.
It is preferred that, the second N-type heavily doped region is changed into colelctor electrode p-type heavily doped region, the device is by LDMOS devices
Part is changed into LIGBT devices.
It is preferred that, the n-type doping bar is differed with p-type doping bar width.
It is preferred that, each doping type is accordingly changed into opposite doping in the device architecture, i.e. p-type doping is changed into
While n-type doping, n-type doping is changed into p-type doping.
Beneficial effects of the present invention are：By introducing media slot in drift region, reduced while retainer member is pressure-resistant
Device surface area, effectively reduction device compares conducting resistance；Heavy doping N bars and the heavy doping of stacking are introduced in device drift region
P bars, low resistance conductive path is provided for device ON state, and further reduction device is finally reached than conducting resistance and effectively reduces device
Area, the purpose for reducing conducting resistance.
Brief description of the drawings
Fig. 1 is traditional horizontal media slot high-voltage device structure schematic diagram；
Fig. 2 is device architecture schematic diagram of the doping bar overlapping configuration of the embodiment of the present invention 1 on the left of media slot；
Fig. 3 is device architecture schematic diagram of the doping bar overlapping configuration of the embodiment of the present invention 2 on the right side of media slot；
Fig. 4 is device architecture schematic diagram of the doping bar overlapping configuration of the embodiment of the present invention 3 below media slot；
Fig. 5 is device architecture schematic diagram of the doping bar overlapping configuration of the embodiment of the present invention 4 on the left of media slot with right side；
Fig. 6 be the embodiment of the present invention 5 on the left of media slot, right side, lower section have the device junction of doping bar overlapping configuration
Structure schematic diagram；
Fig. 7 is the device architecture schematic diagram for having epitaxial layer between the P type substrate and conductive path of the embodiment of the present invention 6；
Fig. 8 is the device architecture schematic diagram of shallow slot grid structure in the embodiment of the present invention 7；
Fig. 9 is the device architecture schematic diagram of deep slot grid structure in the embodiment of the present invention 8；
Figure 10 is device architecture schematic diagram of the slot grid structure in groove in the embodiment of the present invention 9；
Figure 11 is that the device of the embodiment of the present invention 10 is LIGBT structural representation；
Figure 12 be the embodiment of the present invention 11 the present invention be placed on SOI bases, the structural representation without epitaxial layer；
Figure 13 is that the present invention of the embodiment of the present invention 12 is placed on SOI bases, has the structural representation of epitaxial layer
Figure 14 is structure devices simulation architecture schematic diagram of the present invention；
Figure 15 is the ON state current distribution map of structure devices emulation of the present invention；
Figure 16 is structure devices emulation ON state linear zone map of current of the present invention.
Wherein, 1 is P type substrate, and 2 be media slot, and 21 be oxide layer under grid, and 22 be dielectric layer, and 23 be SOI oxygen buried layers, 31
It is the first n-type doping bar for the first N-type heavily doped region, 32,33 be the second n-type doping bar, and 34 be the 3rd n-type doping article, and 35 are
Second N-type heavily doped region, 36 be the 4th n-type doping article, and 37 be the 5th n-type doping article, and 38 be the 6th n-type doping article, and 39 be the
Seven n-type doping bars, 41 be p-type heavily doped region, and 42 be p-well region, and 43 be the first p-type doping bar, and 44 be the second p-type doping bar, 45
It is epitaxial layer for the 3rd p-type doping article, 46,47 be colelctor electrode p-type heavily doped region, and 51 be Source contact electrode, and 52 be polysilicon
Grid, 53 be body field plate, and 54 be drain contact electrode.
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
The present invention reduces the chi of device by adding media slot in drift region while media slot bears laterally pressure-resistant
Very little, on the other hand, in drift region reduction device introduces heavily doped N-type doping bar, is device ON state electronic current than conducting resistance
Low resistance conductive path is provided, device on-resistance is further reduced；Body field plate 53, assisted depletion heavy doping are introduced in media slot
N-type doping bar, raising device is pressure-resistant, and heavily doped P-type doping bar is introduced also in drift region, n-type doping bar is exhausted during OFF state
Meanwhile, an extra electric field is formed, so as to improve the breakdown voltage of device.
Figure 15 is a kind of lateral high-voltage device ON state current distribution map in the present invention.As can be seen, when device ON state works,
CURRENT DISTRIBUTION is in two low resistance conductive paths provided by heavy doping N bars so that in the case that surface area is constant, current capacity
The conducting resistance reduction of enhancing, i.e. device.Figure 16 is structure devices emulation ON state linear zone map of current of the present invention.Pass through MEDICI
Two-dimensional device is emulated, and its linear zone conducting resistance of a kind of exemplary construction of the invention reduces 27% compared to traditional structure；Tradition
Structure is under pressure-resistant 627V, and it is up to 38m Ω cm than conducting resistance2, and a kind of the resistance to of exemplary construction of the present invention is pressed in
During 620V, there was only 26m Ω cm than conducting resistance2.The present invention greatly reduces conducting while high breakdown voltage is obtained
Resistance.
Embodiment 1
As shown in Fig. 2 a kind of lateral high-voltage device, including：Handed over provided with different doping types in media slot 2, the left side of media slot 2
For the doping bar overlapping configuration of setting, doping bar overlapping configuration include successively the first n-type doping bar 32, the first p-type doping bar 43,
There is the 4th n-type doping article 36 between 5th n-type doping article 37, and doping article overlapping configuration and p-well region 42.The upper table of media slot 2
Face is dielectric layer 22, and body field plate 53 extends to the inside of media slot 2 from device upper surface, and body field plate 53 is bordered by polysilicon gate 52,
The lower section of polysilicon gate 52 is oxide layer 21 under grid, and Source contact electrode 51 and polysilicon gate 52 are isolated by dielectric layer 22, body
Plate 53 and drain contact electrode 54 are isolated by dielectric layer 22, and the lower section of drain contact electrode 54 is the second N-type heavily doped region 35, source
The lower section of pole contact electrode 51 is the adjacent N-type heavily doped region 31 of p-type heavily doped region 41 and first, the N of p-type heavily doped region 41 and the first
Type heavily doped region 31 is located at the inner upper of p-well region 42, and dielectric layer 21 is located at the top of p-well region 42, the both sides and bottom of media slot 2
Portion is respectively equipped with the conductive path that the first n-type doping article 32, the second n-type doping article 33, the 3rd n-type doping article 34 are constituted, conductive
There are the first p-type doping bar 43, the second p-type doping bar 44 in the both sides of path respectively, and the bottom of conductive path is P type substrate 1.
Adjacent n-type doping bar, p-type doping bar are one group, and the overlapping configuration is more than 2 multigroup n-type doping for group number
The overlapping configuration that bar, p-type doping bar are arranged alternately.
Specifically, the p-type doping bar and n-type doping bar, its order arranged can be exchanged with position.For example can be
N-P-N-P ..., or P-N-P-N ... arrangements.
Specifically, the n-type doping bar can be differed with p-type doping bar width.
Specifically, each doping type is accordingly changed into opposite doping in the device architecture, i.e. p-type doping is changed into N-type and mixed
While miscellaneous, n-type doping is changed into p-type doping.
Embodiment 2
As shown in figure 3, the present invention and embodiment 1 are essentially identical, difference is：The bar overlapping configuration that adulterates is located at media slot 2
Right side.Bar overlapping configuration adulterate at 2 right side of media slot, doping bar overlapping configuration includes the second n-type doping bar 33, second successively
P-type doping article the 44, the 7th n-type doping article 39, and the n-type doping bar 33, p-type doping bar 44 and the upper surface of n-type doping bar 39
It is in contact with the second N-type heavily doped region 35.
Embodiment 3
As shown in figure 4, the present invention and embodiment 1 are essentially identical, difference is：The bar overlapping configuration that adulterates is located at media slot 2
Lower section.When adulterating bar overlapping configuration below media slot 2, doping article overlapping configuration includes the 3rd n-type doping article the 34, the 3rd successively
P-type doping article the 45, the 6th n-type doping article 38.
Embodiment 4
As shown in figure 5, the present invention and embodiment 1 are essentially identical, difference is：The bar overlapping configuration that adulterates is located at media slot 2
Left side and the right side of media slot 2.
The doping article overlapping configuration on the right side of media slot 2 includes the second n-type doping article 33, the second p-type doping article 44, the successively
Seven n-type doping bars 39, and the n-type doping bar 33, p-type doping bar 44 and the upper surface of n-type doping bar 39 and the second N-type heavy doping
Area 35 is in contact；The doping bar overlapping configuration in the left side of media slot 2 includes the first n-type doping bar 32, the first p-type doping bar successively
43rd, there is the 4th n-type doping article 36 between the 5th n-type doping article 37, and doping article overlapping configuration and p-well region 42.
Embodiment 5
As shown in fig. 6, the present invention and embodiment 1 are essentially identical, difference is：The lower section of media slot 2, left side, right side have
Adulterate bar overlapping configuration；
The doping article overlapping configuration of the lower section of media slot 2 includes the 3rd n-type doping article 34, the 3rd p-type doping article 45, the successively
Six n-type doping bars 38；
The doping article overlapping configuration on the right side of media slot 2 includes the second n-type doping article 33, the second p-type doping article 44, the successively
Seven n-type doping bars 39, and the n-type doping bar 33, p-type doping bar 44 and the upper surface of n-type doping bar 39 and the second N-type heavy doping
Area 35 is in contact；
The doping article overlapping configuration in the left side of media slot 2 includes the first n-type doping article 32, the first p-type doping article 43, the successively
There is the 4th n-type doping article 36 between five n-type doping bars 37, and doping article overlapping configuration and p-well region 42.
Embodiment 6
As shown in fig. 7, the present invention and embodiment 5 are essentially identical, the lower section of media slot 2, left side, right side have doping bar to overlap
Structure；Difference is：There is epitaxial layer 46 between P type substrate 1 and conductive path.
Embodiment 7
As shown in figure 8, the present invention and embodiment 5 are essentially identical, the lower section of media slot 2, left side, right side have doping bar to overlap
Structure；Difference is：Oxide layer 21 constitutes groove grid under polysilicon gate 52 and grid, and now Source contact electrode 51 and body field plate 53 face
Connect.
Embodiment 8
As shown in figure 9, the present invention and embodiment 7 are essentially identical, difference is：Oxide layer under the polysilicon gate 52 and grid
The 21 groove grid constituted are extended to inside P type substrate 1, and now Source contact electrode 51 and body field plate 53 are bordered by.
Embodiment 9
As shown in Figure 10, the present invention and embodiment 7 are essentially identical, and difference is：Aoxidized under the polysilicon gate 52 and grid
The groove grid that layer 21 is constituted are located inside media slot 2.
Embodiment 10
As shown in figure 11, the present invention and embodiment 5 are essentially identical, and difference is：Second N-type heavily doped region 35 is changed into collection
Electrode p-type heavily doped region 47, the device is changed into LIGBT devices from LDMOS device.
Embodiment 11
As shown in figure 12, the present invention and embodiment 5 are essentially identical, and difference is：Structure of the present invention is placed on SOI bases, is situated between
It is SOI oxygen buried layers 23 below the doping bar overlapping configuration of the lower section of matter groove 2, substrate 1 is N-type silicon or p-type for SOI device
Silicon.
Embodiment 12
As shown in figure 13, the present invention and embodiment 11 are essentially identical, and difference is：Structure of the present invention, which is placed on SOI bases, to be situated between
The lower section of the doping bar overlapping configuration of the lower section of matter groove 2 is epitaxial layer 46, and epitaxial layer 46 is arranged at SOI oxygen buried layers 23 and conductive path
Between.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, all those of ordinary skill in the art without departing from disclosed spirit with being completed under technological thought
All equivalent modifications or change, should by the present invention claim be covered.
Claims (10)
1. a kind of lateral high-voltage device, it is characterised in that including：Media slot (2), the lower section of media slot (2), left side, right side are extremely
A few position is provided with the doping bar overlapping configuration that different doping types are arranged alternately, and the upper surface of media slot (2) is dielectric layer
(22), body field plate (53) extends to the inside of media slot (2) from device upper surface, and body field plate (53) is bordered by polysilicon gate (52),
It is oxide layer (21) under grid below polysilicon gate (52), Source contact electrode (51) and polysilicon gate (52) pass through dielectric layer (22)
Isolation, body field plate (53) and drain contact electrode (54) are isolated by dielectric layer (22), and drain contact electrode (54) lower section is the
Two N-type heavily doped regions (35), are adjacent p-type heavily doped region (41) and the first N-type heavy doping below Source contact electrode (51)
Area (31), p-type heavily doped region (41) and the first N-type heavily doped region (31) are located at the inner upper of p-well region (42), dielectric layer (21)
Top positioned at p-well region (42), the both sides and bottom of media slot (2) are respectively equipped with the first n-type doping bar (32), the second N-type and mixed
There is the first p-type doping bar the conductive path that miscellaneous article (33), the 3rd n-type doping article (34) are constituted, the both sides of conductive path respectively
(43), the second p-type doping bar (44), the bottom of conductive path is P type substrate (1)；If the bar overlapping configuration that adulterates is in media slot
(2) lower section, the then article overlapping configuration that adulterates is mixed including the 3rd n-type doping article (34), the 3rd p-type doping article (45), the 6th N-type successively
Miscellaneous bar (38)；If adulterating bar overlapping configuration on the right side of media slot (2), doping bar overlapping configuration is mixed including the second N-type successively
Miscellaneous article (33), the second p-type doping article (44), the 7th n-type doping article (39), and the n-type doping bar (33), p-type doping bar
(44) it is in contact with n-type doping bar (39) upper surface with the second N-type heavily doped region (35)；If the bar overlapping configuration that adulterates is in medium
On the left of groove (2), then article overlapping configuration that adulterates includes the first n-type doping article (32), the first p-type doping article (43), the 5th N-type successively
Adulterating between bar (37), and doping article overlapping configuration and p-well region (42) has the 4th n-type doping article (36).
2. a kind of lateral high-voltage device according to claim 1, it is characterised in that：Adjacent n-type doping bar, p-type doping
Bar is one group, the overlapping configuration that the overlapping configuration is more than 2 multigroup n-type doping bar for group number, p-type doping bar is arranged alternately.
3. a kind of lateral high-voltage device according to claim 1, it is characterised in that：It is SOI device, for SOI device
For substrate (1) be N-type silicon or P-type silicon.
4. a kind of lateral high-voltage device according to claim 1, it is characterised in that：P type substrate (1) is between conductive path
There is epitaxial layer (46), or epitaxial layer (46) is arranged at SOI oxygen buried layers (23) between conductive path.
5. a kind of lateral high-voltage device according to claim 1, it is characterised in that：Oxide layer under polysilicon gate (52) and grid
(21) groove grid are constituted, now Source contact electrode (51) and body field plate (53) are bordered by.
6. a kind of lateral high-voltage device according to claim 5, it is characterised in that：Oxygen under the polysilicon gate (52) and grid
The groove grid for changing layer (21) composition extend to P type substrate (1) inside, and now Source contact electrode (51) and body field plate (53) are bordered by.
7. a kind of lateral high-voltage device according to claim 5, it is characterised in that：Oxygen under the polysilicon gate (52) and grid
The groove grid for changing layer (21) composition are located at media slot (2) inside.
8. a kind of lateral high-voltage device according to claim 1, it is characterised in that：Second N-type heavily doped region (35) is become
For colelctor electrode p-type heavily doped region (47), the device is changed into LIGBT devices from LDMOS device.
9. a kind of lateral high-voltage device according to claim 1, it is characterised in that：The n-type doping bar and p-type doping bar
Width is differed.
10. a kind of lateral high-voltage device according to claim 1, it is characterised in that：Each doping class in the device architecture
Type is accordingly changed into opposite doping, i.e., while p-type doping is changed into n-type doping, and n-type doping is changed into p-type doping.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108389892A (en) * | 2018-02-02 | 2018-08-10 | 电子科技大学 | A kind of lateral resistance to pressure area of the shallow/deep groove type with longitudinal varying doping dosage |
| CN109166915A (en) * | 2018-08-28 | 2019-01-08 | 电子科技大学 | A kind of medium superjunction MOS type power semiconductor and preparation method thereof |
| CN111524960A (en) * | 2020-04-28 | 2020-08-11 | 电子科技大学 | Transverse high-voltage device |
| CN111524798A (en) * | 2020-04-03 | 2020-08-11 | 电子科技大学 | Preparation method of deep-groove transverse pressure-resistant region with longitudinal linear variable doping |
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| CN103715238A (en) * | 2013-12-30 | 2014-04-09 | 电子科技大学 | Transverse high-voltage component with ultra-low specific on-resistance |
| CN103904124A (en) * | 2014-04-10 | 2014-07-02 | 电子科技大学 | SOI groove type LDMOS device with U-shaped extension gate |
| CN104538446A (en) * | 2014-12-23 | 2015-04-22 | 电子科技大学 | Bidirectional MOS type device and manufacturing method thereof |
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2017
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103715238A (en) * | 2013-12-30 | 2014-04-09 | 电子科技大学 | Transverse high-voltage component with ultra-low specific on-resistance |
| CN103904124A (en) * | 2014-04-10 | 2014-07-02 | 电子科技大学 | SOI groove type LDMOS device with U-shaped extension gate |
| CN104538446A (en) * | 2014-12-23 | 2015-04-22 | 电子科技大学 | Bidirectional MOS type device and manufacturing method thereof |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108389892A (en) * | 2018-02-02 | 2018-08-10 | 电子科技大学 | A kind of lateral resistance to pressure area of the shallow/deep groove type with longitudinal varying doping dosage |
| CN108389892B (en) * | 2018-02-02 | 2020-08-11 | 电子科技大学 | Deep-groove-type transverse voltage-resistant region with longitudinal variable doping dose |
| CN109166915A (en) * | 2018-08-28 | 2019-01-08 | 电子科技大学 | A kind of medium superjunction MOS type power semiconductor and preparation method thereof |
| CN111524798A (en) * | 2020-04-03 | 2020-08-11 | 电子科技大学 | Preparation method of deep-groove transverse pressure-resistant region with longitudinal linear variable doping |
| CN111524798B (en) * | 2020-04-03 | 2022-05-03 | 电子科技大学 | Preparation method of deep-groove transverse pressure-resistant region with longitudinal linear variable doping |
| CN111524960A (en) * | 2020-04-28 | 2020-08-11 | 电子科技大学 | Transverse high-voltage device |
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