CN107359192A - A kind of lateral high-voltage device - Google Patents
A kind of lateral high-voltage device Download PDFInfo
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- CN107359192A CN107359192A CN201710631105.0A CN201710631105A CN107359192A CN 107359192 A CN107359192 A CN 107359192A CN 201710631105 A CN201710631105 A CN 201710631105A CN 107359192 A CN107359192 A CN 107359192A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 23
- 229920005591 polysilicon Polymers 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 230000005684 electric field Effects 0.000 abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 238000010276 construction Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 239000004020 conductor Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000001413 cellular effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
Abstract
The present invention provides a kind of lateral high-voltage device, and overlapping the first type doping bar of Z-direction forms horizontal super-junction structure with Second-Type doping bar, improved while reducing device on-resistance pressure-resistant；Media slot is introduced on this basis, and media slot can effectively reduce device surface product, while bear pressure-resistant, retainer member high withstand voltage while reducing the ratio conducting resistance of device；Body field plate is introduced in media slot, body field plate modulated electric fields assisted depletion in device OFF state is effectively pressure-resistant using being shared on the left of device, and introducing electric charge in device ON state improves drift region carrier quantity；The present invention while device electric breakdown strength is improved, can reduce the ratio conducting resistance of device.
Description
Technical field
The invention belongs to semiconductor power device technology field, and in particular to a kind of lateral high-voltage device.
Background technology
Lateral double diffused metal-Oxide-Semiconductor Field effect transistor (Lateral Double-diffused
Metal-Oxide-Semiconductor Field Effect Transistor, LDMOSFET) it is used as power integrated circuit
Core devices in (Power Integrated Circuit, PIC), have that easy of integration, driving power is small, negative temperature coefficient etc.
Advantage, for many years always towards high-breakdown-voltage (Breakdown Voltage, BV) and low than conducting resistance (Specific
On-Resistance, Ron, sp) direction develop.Higher breakdown voltage need device have longer drift region length and
Relatively low drift doping concentration, this causes device to have higher conducting resistance.Breakdown voltage and than between conducting resistance
This contradictory relation, exactly perplex " the silicon limit " problem of industry.
In order to alleviate this contradiction, make device while have high withstand voltage with low than conducting resistance, the present invention is in LDMOS transverse directions
Media slot is introduced in drift region.Media slot shortens lateral device dimensions while can bearing most of laterally pressure-resistant, significantly
Degree reduces the area of chip.But it is still more larger than conducting resistance by traditional media slot LDMOS, fail further to alleviate pressure-resistant
With the contradiction than conducting resistance.
The content of the invention
In view of the above the shortcomings that prior art, it is an object of the invention to provide a kind of lateral high-voltage device, purpose
It is to reduce device on-resistance while improving device electric breakdown strength.
For achieving the above object, technical solution of the present invention is as follows：
A kind of lateral high-voltage device, its structure cell include Second-Type doped substrate, gate oxide, blanket dielectric layer, source
Pole the first type heavily doped region, the first type doping bar, the first type heavily doped region of drain electrode, Second-Type heavily doped region, Second-Type dopant well
Area, Second-Type doping bar, Source contact electrode, drain contact electrode, polysilicon gate, body field plate, media slot area；The Second-Type
Doped substrate upper surface is provided with the first type doping bar and Second-Type doping bar of Z-direction arrangement, first type doping article, the
Two types doping bar surrounds media slot area and is cut into by the media slot area U-shaped, and media slot area inside left is equipped with polysilicon
Grid, the polysilicon gate left side is not adjacent with media slot area edge and its lower surface and body field plate are adjacent, and body field version is left
Side does not abut with media slot area edge, and the polysilicon gate left hand edge abuts gate oxide, and the gate oxide left hand edge is with being situated between
Matter groove area edge is concordant, and the gate oxide left lower is equipped with Second-Type doped well region, and the gate oxide left upper portion is put
There is a source electrode first type heavily doped region adjacent with Second-Type doped well region, adjacent the on the left of the first type of source electrode heavily doped region
Two type heavily doped regions, source electrode the first type heavily doped region and Second-Type heavily doped region upper surface adjoining Source contact electrode, institute
State Source contact electrode to be isolated by surface covering oxide layer with drain contact electrode, and surface covering oxide layer is being situated between
Above Zhi Cao areas upper surface, the drain contact electrode lower surface is equipped with the first type heavily doped region of drain electrode, the first type of the drain electrode
Abutted on the left of heavily doped region with media slot area, lower surface and the first type doping bar, Second-Type doping bar adjoining.
The total technical scheme of the present invention：Overlapping the first type doping bar of Z-direction forms horizontal superjunction with Second-Type doping bar
Structure, improved while reducing device on-resistance pressure-resistant；Media slot is introduced on this basis, and media slot can effectively reduce device
Part surface area, while bear pressure-resistant, retainer member high withstand voltage while reducing the ratio conducting resistance of device；Draw in media slot
Enter body field plate, body field plate modulated electric fields assisted depletion in device OFF state is effectively pressure-resistant using being shared on the left of device, is opened in device
Electric charge is introduced when state and improves drift region carrier quantity；To sum up, the present invention can drop while device electric breakdown strength is improved
The ratio conducting resistance of low device.
Specifically, the body field plate can be metal or DOPOS doped polycrystalline silicon, it can be any electric conductor or partly lead
Body.
It is preferred that the device is SOI device, substrate is the first type silicon or Second-Type for SOI device
Silicon.
It is preferred that have epitaxial layer between Second-Type doped substrate and the first type doping bar, Second-Type doping bar, or
Person's epitaxial layer is arranged between SOI oxygen buried layers and the first type doping bar, Second-Type doping bar.
Specifically, the epitaxial layer is the first type silicon or Second-Type silicon.
It is preferred that the media slot area, is divided into first medium groove, second medium groove, the 3rd media slot ..., from
Top to bottm dielectric constant increases successively.
It is preferred that lower section adjacent body field plate on the left of the drain contact electrode, to evade drain terminal high electric field, is avoided
Puncture in advance.
Specifically, the body field plate can be metal or DOPOS doped polycrystalline silicon, it can be any electric conductor or partly lead
Body.
It is preferred that the polysilicon gate and gate oxide in the structure are slot grid structure.Now source contact electricity
Pole and body field plate are bordered by.Conventional shallow slot grid technique is more easy to realize but its border flex point being located inside drift region can cause one
Peak electric field, easily cause device to puncture in advance, it is pressure-resistant not as expected.
It is preferred that the polysilicon gate of the slot grid structure is extended in Second-Type doped substrate with gate oxide
Portion.Now Source contact electrode and the adjoining of body field plate.Its border flex point is guided in substrate, eliminates the possibility punctured in advance.
It is preferred that the first type heavily doped region of drain electrode is changed into colelctor electrode Second-Type heavily doped region, the device by
LDMOS is changed into LIGBT.
It is preferred that the Second-Type doping bar differs with the first type doping bar width.
It is preferred that the first type is p-type, Second-Type is N-type；Or first type be N-type, Second-Type is p-type.
Beneficial effects of the present invention are：Overlapping the first type doping bar of Z-direction forms horizontal superjunction with Second-Type doping bar
Structure, improved while reducing device on-resistance pressure-resistant；Media slot is introduced on this basis, and media slot can effectively reduce device
Part surface area, while bear pressure-resistant, retainer member high withstand voltage while reducing the ratio conducting resistance of device；Draw in media slot
Enter body field plate, body field plate modulated electric fields assisted depletion in device OFF state is effectively pressure-resistant using being shared on the left of device, is opened in device
Electric charge is introduced when state and improves drift region carrier quantity；To sum up, the present invention can drop while device electric breakdown strength is improved
The ratio conducting resistance of low device.
Brief description of the drawings
Fig. 1 is a kind of lateral high-voltage device structural representation of the embodiment of the present invention 1；
Fig. 2 is that one kind that media slot region is made up of upper and lower two kinds of differing dielectric constant media in the embodiment of the present invention 2 is shown
Example structural representation；
Fig. 3 is a kind of example knot that media slot region is made up of three kinds of differing dielectric constant media in the embodiment of the present invention 3
Structure schematic diagram；
Fig. 4 is a kind of exemplary construction signal that drain electrode drain contact electrode introduces drain electrode body field plate in the embodiment of the present invention 4
Figure；
Fig. 5 is a kind of exemplary construction schematic diagram that media slot region is placed on epitaxial layer in the embodiment of the present invention 5；
Fig. 6 is a kind of exemplary construction schematic diagram of shallow slot grid structure in the embodiment of the present invention 6；
Fig. 7 is a kind of exemplary construction schematic diagram of deep slot grid structure in the embodiment of the present invention 7；
Fig. 8 is that the device of the embodiment of the present invention 8 is a kind of LIGBT exemplary construction schematic diagram；
Fig. 9 is a kind of exemplary construction schematic diagram that the cellular of the embodiment of the present invention 9 is placed on SOI bases；
Figure 10 is the exemplary construction signal that the cellular of the embodiment of the present invention 10 is placed in above the epitaxial layer on SOI base oxygen buried layers
Figure.
Wherein, 1 is Second-Type doped substrate, and 2 be media slot area, and 3 be SOI oxygen buried layers, and 21 be gate oxide, and 22 be covering
Dielectric layer, 31 be source electrode the first type heavily doped region, and 32 be that the first type adulterates bar, and 33 be the first type heavily doped region of drain electrode, and 41 be the
Two type heavily doped regions, 42 be Second-Type doped well region, and 43 be that Second-Type adulterates bar, and 46 be colelctor electrode Second-Type heavily doped region, 47
It is Source contact electrode for epitaxial layer, 51,52 be polysilicon gate, and 53 be body field plate, and 54 be drain contact electrode, and 56 be body field
Plate, 61 be first medium groove, and 62 be second medium groove, and 63 be the 3rd media slot.
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
The first type that the present invention is overlapped by Z-direction adulterates bar and forms horizontal super-junction structure with Second-Type doping bar, reduces
Improved while device on-resistance pressure-resistant；Media slot is introduced on this basis, media slot can effectively reduce device surface product,
Bear pressure-resistant, retainer member high withstand voltage while reducing the ratio conducting resistance of device simultaneously；Body field plate is introduced in media slot,
Body field plate modulated electric fields assisted depletion in device OFF state, it is effectively pressure-resistant using being shared on the left of device, draw in device ON state
Enter electric charge and improve drift region carrier quantity；To sum up, the present invention can reduce device while device electric breakdown strength is improved
Compare conducting resistance.
Embodiment 1
Fig. 1 show a kind of lateral high-voltage device of the present invention, a kind of lateral high-voltage device, and its structure cell includes second
Type doped substrate 1, gate oxide 21, blanket dielectric layer 22, the first type of source electrode heavily doped region 31, the first type doping bar 32, drain electrode
First type heavily doped region 33, Second-Type heavily doped region 41, Second-Type doped well region 42, Second-Type doping bar 43, source contact electricity
Pole 51, drain contact electrode 54, polysilicon gate 52, body field plate 53, media slot area 2；The upper surface of Second-Type doped substrate 1 is set
It is equipped with the first type doping bar 32 and Second-Type doping bar 43 of Z-direction arrangement, the first type doping bar 32, Second-Type doping bar
43 encirclement media slot areas 2 and it is cut into by the media slot area 2 U-shaped, the inside left of media slot area 2 is equipped with polysilicon gate 52,
The left side of polysilicon gate 52 is not adjacent with the edge of media slot area 2 and its lower surface and body field plate 53 are adjacent, body field version
53 left sides do not abut with the edge of media slot area 2, and the left hand edge of polysilicon gate 52 abuts gate oxide 21, the gate oxide 21
Left hand edge is concordant with the edge of media slot area 2, and the left lower of gate oxide 21 is equipped with Second-Type doped well region 42, the grid oxygen
Change the left upper portion of layer 21 and be equipped with the source electrode first type heavily doped region 31 adjacent with Second-Type doped well region 42, the source electrode first
The adjacent Second-Type heavily doped region 41 in the left side of type heavily doped region 31, the first type of source electrode heavily doped region 31 and Second-Type heavily doped region
41 upper surfaces abut Source contact electrode 51, and the Source contact electrode 51 is covered by surface with drain contact electrode 54 and aoxidized
Layer 22 is isolated, and the surface covers oxide layer 22 above the upper surface of media slot area 2, the lower end of drain contact electrode 54
Face is equipped with the first type heavily doped region 33 of drain electrode, and the left side of the first type heavily doped region of the drain electrode 33 abuts with media slot area 2, lower surface
Abutted with the first type doping bar 32, Second-Type doping bar 43.
Specifically, the body field plate can be metal or DOPOS doped polycrystalline silicon, it can be any electric conductor or partly lead
Body.
Specifically, adjacent first type doping bar, Second-Type doping bar are one group, multigroup the of stackable group of number more than 2
One type doping bar, Second-Type doping bar.
Specifically, the Second-Type doping bar can differ with the first type doping bar width.
Embodiment 2
As shown in Fig. 2 the present embodiment and embodiment 1 are essentially identical, difference is：The media slot area 2, by different up and down
First medium groove 61, the second medium groove 62 of dielectric constant form, and the dielectric constant of first medium groove 61 is less than second medium groove 62.
Embodiment 3
Shown in Fig. 3, the present embodiment and embodiment 1 are essentially identical, and difference is：The media slot area 2, is divided into first medium
Groove 61, second medium groove 62, the 3rd media slot 63, from top to bottom dielectric constant increase successively.
Embodiment 4
As shown in figure 4, the present embodiment and embodiment 1 are essentially identical, difference is：Under the left side of drain contact electrode 54
Square adjacent body field plate 56, to evade drain terminal high electric field, avoid puncturing in advance.
Specifically, the body field plate can be metal or DOPOS doped polycrystalline silicon, it can be any electric conductor or partly lead
Body.
Embodiment 5
As shown in figure 5, the present embodiment and embodiment 1 are essentially identical, difference is：The type of Second-Type doped substrate 1 and first
There is epitaxial layer 47 between doping bar 32, Second-Type doping bar 43.
Specifically, the epitaxial layer is the 1st type silicon or the 2nd type silicon.
Embodiment 6
As shown in fig. 6, the present embodiment and embodiment 1 are essentially identical, difference is：Polysilicon gate 52 in the structure with
Gate oxide 21 is slot grid structure.Now Source contact electrode and body field plate are bordered by.Conventional shallow slot grid technique be more easy to realize but
Its border flex point being located inside drift region can cause a peak electric field, easily cause device to puncture in advance, pressure-resistant not as pre-
Phase.
Embodiment 7
As shown in fig. 7, the present embodiment and embodiment 6 are essentially identical, difference is：The polysilicon gate 52 of the slot grid structure
Extended to gate oxide 21 inside Second-Type doped substrate 1.Now Source contact electrode and the adjoining of body field plate.Its border is turned
Point is guided in substrate, eliminates the possibility punctured in advance.
Embodiment 8
As shown in figure 8, the present embodiment and embodiment 1 are essentially identical, difference is：The first type heavily doped region 33 of drain electrode is become
For colelctor electrode Second-Type heavily doped region 46, the device is changed into LIGBT from LDMOS.
Embodiment 9
As shown in figure 9, the present embodiment and embodiment 1 are essentially identical, difference is：The structure cell is placed in SOI and buries oxygen
On layer 3.
Specifically, the epitaxial layer is the 1st type silicon or the 2nd type silicon.
Embodiment 10
As shown in Figure 10, the present embodiment and embodiment 1 are essentially identical, and difference is：The top of Second-Type doped substrate 1 is provided with
Oxygen buried layer 3, one layer of epitaxial layer 47 of extension on oxygen buried layer 3, the structure cell are placed on epitaxial layer 47.
Specifically, the epitaxial layer is the 1st type silicon or the 2nd type silicon.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, all those of ordinary skill in the art without departing from disclosed spirit with being completed under technological thought
All equivalent modifications or change, should by the present invention claim be covered.
Claims (10)
- A kind of 1. lateral high-voltage device, it is characterised in that：Its structure cell includes Second-Type doped substrate (1), gate oxide (21), blanket dielectric layer (22), source electrode the first type heavily doped region (31), the first type doping bar (32), the first type heavy doping of drain electrode Area (33), Second-Type heavily doped region (41), Second-Type doped well region (42), Second-Type doping bar (43), Source contact electrode (51), drain contact electrode (54), polysilicon gate (52), body field plate (53), media slot area (2)；The Second-Type doped substrate (1) upper surface is provided with the first type doping bar (32) and Second-Type doping bar (43) of Z-direction arrangement, and first type adulterates bar (32), Second-Type doping bar (43) surrounds media slot area (2) and is cut into U-shaped, the media slot area by the media slot area (2) (2) inside left is equipped with polysilicon gate (52), it is not adjacent with media slot area (2) edge on the left of the polysilicon gate (52) and its under Surface and body field plate (53) are adjacent, are not abutted on the left of body field version (53) with media slot area (2) edge, the polysilicon gate (52) left hand edge adjoining gate oxide (21), gate oxide (21) left hand edge is concordant with media slot area (2) edge, the grid Oxide layer (21) left lower is equipped with Second-Type doped well region (42), and gate oxide (21) left upper portion is equipped with and Second-Type Adjacent source electrode the first type heavily doped region (31) in doped well region (42), the first type of source electrode heavily doped region (31) left side are adjacent Second-Type heavily doped region (41), the first type of source electrode heavily doped region (31) and Second-Type heavily doped region (41) upper surface contiguous sources Pole contact electrode (51), the Source contact electrode (51) cover oxide layer (22) phase with drain contact electrode (54) by surface Isolation, and the surface covers oxide layer (22) above media slot area (2) upper surface, drain contact electrode (54) lower end Face is equipped with the first type heavily doped region (33) of drain electrode, and the first type heavily doped region (33) of drain electrode left side and media slot area (2) are adjacent, Lower surface and the first type doping bar (32), Second-Type doping bar (43) are adjacent.
- A kind of 2. lateral high-voltage device according to claim 1, it is characterised in that：The device is SOI device, for Substrate is the first type silicon or Second-Type silicon for SOI device.
- A kind of 3. lateral high-voltage device according to claim 1, it is characterised in that：Second-Type doped substrate (1) and first There is epitaxial layer (47) between type doping bar (32), Second-Type doping bar (43), or epitaxial layer (47) is arranged at SOI oxygen buried layers (3) between the first type doping bar (32), Second-Type doping bar (43).
- A kind of 4. lateral high-voltage device according to claim 1, it is characterised in that：The media slot area (2), is divided into first Media slot (61), second medium groove (62), the 3rd media slot (63) ..., dielectric constant increases successively from top to bottom.
- A kind of 5. lateral high-voltage device according to claim 1, it is characterised in that：On the left of the drain contact electrode (54) Lower section adjacent body field plate (56).
- A kind of 6. lateral high-voltage device according to claim 1, it is characterised in that：Polysilicon gate (52) in the structure It is slot grid structure with gate oxide (21).
- A kind of 7. lateral high-voltage device according to claim 6, it is characterised in that：The polysilicon gate of the slot grid structure (52) it is internal that Second-Type doped substrate (1) is extended to gate oxide (21).
- A kind of 8. lateral high-voltage device according to claim 1, it is characterised in that：To be drained the first type heavily doped region (33) It is changed into colelctor electrode Second-Type heavily doped region (46), the device is changed into LIGBT from LDMOS.
- A kind of 9. lateral high-voltage device according to claim 1, it is characterised in that：Second-Type doping article (43) and the One type doping bar (32) width differs.
- A kind of 10. lateral high-voltage device according to claim 1 to 9 any one, it is characterised in that：First type is p-type, Second-Type is N-type；Or first type be N-type, Second-Type is p-type.
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| CN201710631105.0A CN107359192A (en) | 2017-07-28 | 2017-07-28 | A kind of lateral high-voltage device |
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| CN201710631105.0A CN107359192A (en) | 2017-07-28 | 2017-07-28 | A kind of lateral high-voltage device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108389892A (en) * | 2018-02-02 | 2018-08-10 | 电子科技大学 | A kind of lateral resistance to pressure area of the shallow/deep groove type with longitudinal varying doping dosage |
| CN113206145A (en) * | 2021-04-22 | 2021-08-03 | 电子科技大学 | Power semiconductor device with improved hot carrier injection |
Citations (6)
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