CN104269441A - SOI voltage resistance structure with charge regions fixed at equal intervals and SOI power device - Google Patents
SOI voltage resistance structure with charge regions fixed at equal intervals and SOI power device Download PDFInfo
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- CN104269441A CN104269441A CN201410564619.5A CN201410564619A CN104269441A CN 104269441 A CN104269441 A CN 104269441A CN 201410564619 A CN201410564619 A CN 201410564619A CN 104269441 A CN104269441 A CN 104269441A
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- 239000000758 substrate Substances 0.000 claims abstract description 28
- 239000003989 dielectric material Substances 0.000 claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 15
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- 230000005855 radiation Effects 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 4
- 229910052792 caesium Inorganic materials 0.000 claims description 3
- FKNQFGJONOIPTF-UHFFFAOYSA-N Sodium cation Chemical compound [Na+] FKNQFGJONOIPTF-UHFFFAOYSA-N 0.000 claims description 2
- HYFJXBYGHMZZPQ-UHFFFAOYSA-N boron(1+) Chemical compound [B+] HYFJXBYGHMZZPQ-UHFFFAOYSA-N 0.000 claims description 2
- -1 caesium cation Chemical class 0.000 claims description 2
- OCVXZQOKBHXGRU-UHFFFAOYSA-N iodine(1+) Chemical compound [I+] OCVXZQOKBHXGRU-UHFFFAOYSA-N 0.000 claims description 2
- 230000005684 electric field Effects 0.000 abstract description 18
- 239000004065 semiconductor Substances 0.000 description 15
- 108091006146 Channels Proteins 0.000 description 13
- 239000000463 material Substances 0.000 description 11
- 230000015556 catabolic process Effects 0.000 description 10
- 238000009826 distribution Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
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- 238000010586 diagram Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
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- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- TVFDJXOCXUVLDH-UHFFFAOYSA-N caesium atom Chemical compound [Cs] TVFDJXOCXUVLDH-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/408—Electrodes ; Multistep manufacturing processes therefor with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
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Abstract
The invention discloses an SOI voltage resistance structure with charge regions fixed at equal intervals and a power device. The SOI voltage resistance structure comprises a substrate layer, a dielectric buried layer, an active layer and a plurality of high-concentration fixed charge regions with the concentration larger than or equal to 1*10<13> cm<-2>, wherein the substrate layer, the dielectric buried layer, the active layer and the high-concentration fixed charge regions are stacked in sequence from top to bottom. The high-concentration fixed charge regions are made of a dielectric material, and the charge polarity is positive. The high-concentration fixed charge regions are all located on the dielectric buried layer, arranged in a spaced mode and distributed at equal intervals. According to the SOI voltage resistance structure with the charge regions fixed at equal intervals and the power device, the electric field of the dielectric buried layer can be greatly enhanced, and the voltage resistance capacity is effectively improved; a technology is easy to implement, and is completely compatible with a common CMOS technology.
Description
Technical field
The invention belongs to field of semiconductor, be specifically related to a kind of equidistantly fixed charge district SOI pressure-resistance structure and SOI power device.
Background technology
SOI (Silicon On Insulator, silicon in dielectric substrate) power device has high operating rate and integrated level, reliably insulation property, strong Radiation hardness and without controllable silicon self-locking effect, is widely used in the fields such as power electronics, industrial automation, Aero-Space and weaponry.
The puncture voltage of SOI power device is carried out ionization integral and calculating by electric field along withstand voltage length and is obtained, depend on longitudinally withstand voltage and horizontal withstand voltage in smaller.SOI laterally withstand voltage design principle can continue to use ripe silica-based principle and technology, such as RESURF (Reduce SURface electric Field reduces surface field), variety lateral doping, field plate and super-junction structure etc.And prevent the depletion region of device to expand to substrate due to dielectric buried layer, can only be born by top layer silicon and dielectric buried layer so SOI is longitudinally withstand voltage.But by the restriction of device architecture, self-heating effect and technique, top layer silicon and dielectric buried layer all can not be too thick, so cause longitudinally withstand voltage lower, become the main cause of the horizontal SOI power device of restriction and integrated circuit development and application.
Typical conventional n-type SOI LDMOS (Lateral Double Diffused Metal Oxide Semiconductor, lateral double diffusion metal oxide semiconductor) structure of device, as shown in Figure 1, it is primarily of source electrode, n+ source region, gate oxide, N-shaped active semiconductor layer, n+ drain region, drain electrode, p-type channel region, p-type substrate semiconductor layer and dielectric buried layer composition.Be SiO for dielectric buried layer
2conventional SOI device, by the restriction of Gauss theorem, dielectric buried layer electric field E during device breakdown
i" E need be met with semiconductor active layer electric field ES
i=3E
s".Under regular situation, the critical breakdown electric field of silicon is 20-40V/um, so during device breakdown, EI is only about 100V/um, does not reach SiO far away
2more than critical breakdown electric field 600V/um, so SiO
2withstand voltage potentiality fail to be fully used.
In order to the longitudinal direction improving SOI device is withstand voltage, notification number is that the Chinese invention patent of CN101477999A discloses one " for power device have interface charge island SOI pressure-resistance structure ", and it is primarily of semiconductor substrate layer, dielectric buried layer and semiconductor active layer.The multiple high concentration n+ districts stretched in described semiconductor active layer are provided with in the four corner or part range of the interface of described dielectric buried layer and semiconductor active layer, multiple high concentration n+ interval is disconnected to be arranged, described high concentration n+ district is semiconductor material, multiple high concentration n+ district forms interface charge island, and the concentration range in high concentration n+ district is greater than 1 × 10
16cm
-3.This invention, in the active layer of conventional SOI power device, is provided with at least one interface island buried regions on dielectric buried layer, the conduction type of active layer is contrary with the conduction type of interface island buried regions.When applying reversed bias voltage when draining, simultaneously source, grid and Substrate ground time, the upper interface of dielectric buried layer is by adaptively collecting hole, and hole concentration increases from source to thread cast-off.Although, these interface cavity energies effectively increase dielectric buried layer electric field and improve withstand voltage, but this structure affects larger by subsequent manufacturing procedures, during high temperature, the horizontal and vertical expansion of silicon layer charge-islands is serious, and brings difficulty for thin silicone layer SOI device structural design.
Summary of the invention
Technical problem to be solved by this invention is the resistance to voltage device of the conventional SOI longitudinally resistance to deficiency forced down, and provide a kind of equidistantly fixed charge district SOI pressure-resistance structure and SOI power device, it not only can improve dielectric buried layer electric field greatly, thus effectively improves withstand voltage; And technique realizes simple, completely compatible with stand CMOS.
For solving the problem, the present invention is achieved by the following technical solutions:
A kind of equidistantly fixed charge district SOI pressure-resistance structure, comprise the substrate layer, dielectric buried layer and the active layer that stack successively from bottom to top, its difference is: also comprise multiple concentration further and be more than or equal to 1 × 10
13cm
-2high concentration fixed charge district; These high concentration fixed charge districts are formed by dielectric material, and charge polarity is just; These high concentration fixed charge districts are all positioned at dielectric buried layer top, and arrange in being interrupted each other, and equally distribute.
In such scheme, the concentration in all high concentration fixed charge districts is preferably all equal.
In such scheme, described high concentration fixed charge district is injected in dielectric buried layer by ion implantation mode, and the ion injected is preferably caesium cation, sodium cation, iodine cation, boron cation and/or siliconium ion.
In such scheme, the height in all high concentration fixed charge districts is preferably all equal.
In such scheme, the top in all high concentration fixed charge districts is preferably equal to the distance of dielectric buried layer upper surface.
In such scheme, described dielectric buried layer preferably has the heat radiation silicon window of up/down perforation substrate layer and active layer.
There is the SOI power device of above-mentioned equidistant fixed charge island SOI pressure-resistance structure, i.e. SOI LDMOS (lateral double diffusion metal oxide semiconductor) device, comprise the substrate layer, dielectric buried layer and the active layer that stack successively from bottom to top; On both sides in described active layer, edge is provided with source region, channel region and drain region; Source region and channel region are affixed, and edge on the side being simultaneously arranged on active layer; Edge on the opposite side that drain region is then arranged on active layer; The surface of active layer is provided with source electrode, grid and drain electrode; Source electrode is overlying on the top in source region, and grid is overlying on the top of source region and channel region simultaneously; Drain electrode is overlying on the top in drain region; Its difference is, described in bury in dielectric layer and be also provided with multiple high concentration fixed charge district further; These high concentration fixed charge districts are formed by dielectric material, and charge polarity is just; These high concentration fixed charge districts are all positioned at the top of dielectric buried layer, and arrange in being interrupted each other, and equally distribute.
There is the SOI power device of above-mentioned equidistant fixed charge island SOI pressure-resistance structure, i.e. SOI IGBT (insulated gate bipolar transistor) device, comprise the substrate layer, dielectric buried layer and the active layer that stack successively from bottom to top; On both sides in described active layer, edge is provided with negative electrode charged region, channel region and anode charged region; Negative electrode charged region and channel region are affixed, and edge on the side being simultaneously arranged on active layer; Edge on the opposite side that anode charged region is then arranged on active layer; The surface of active layer is provided with negative electrode, grid and anode; Negative electrode is overlying on the top of negative electrode charged region, and grid is overlying on the top of negative electrode charged region and channel region simultaneously; Anode is overlying on the top of anode charged region; Its difference is, described in bury in dielectric layer and be also provided with multiple high concentration fixed charge district further; These high concentration fixed charge districts are formed by dielectric material, and charge polarity is just; These high concentration fixed charge districts are all positioned at the top of dielectric buried layer, and arrange in being interrupted each other, and equally distribute.
There is the SOI power device of above-mentioned equidistant fixed charge island SOI pressure-resistance structure, i.e. power diode device, comprise the substrate layer, dielectric buried layer and the active layer that stack successively from bottom to top; On both sides in described active layer, corner place is provided with negative electrode charged region and anode charged region respectively; The surface of active layer is provided with negative electrode and anode; Negative electrode is overlying on the top of negative electrode charged region; Anode is overlying on the top of anode charged region; Its difference is, described in bury in dielectric layer and be also provided with multiple high concentration fixed charge district further; These high concentration fixed charge districts are formed by dielectric material, and charge polarity is just; These high concentration fixed charge districts are all positioned at the top of dielectric buried layer, and arrange in being interrupted each other, and equally distribute.
Compared with prior art, the present invention has following features:
1, high concentration fixed charge district acts on the shape high concentration electric subarea, interface of dielectric buried layer directly over it and semiconductor active layer by Coulomb force, the hole of high concentration can be accumulated again between two adjacent electronic area, substantially increase the interface charge of burying dielectric layer surface.According to Gauss theorem, this interface charge meeting amplified medium buried regions electric field strength, thus effectively improve longitudinally withstand voltage;
2, the material in high concentration fixed charge district is medium, the mode of ion implantation can be directly adopted to realize, and the cation injected is very little at dielectric buried layer diffusion coefficient, be approximately fixed charge, must affect by subsequent high temperature processes hardly, simultaneously completely compatible with conventional cmos/SOI technology, technique realizes simple; In addition, the material due to high concentration fixed charge district is medium, compared with the structure of existing change dielectric buried layer shape, can not adopt too much insulating material, and also just not additional self-heating effect produces;
3, the fixed charge district concentration range of high concentration is equal to or greater than 1 × 10
13cm
-2, when being equal to or greater than this value, fixed charge concentration does not almost affect puncture voltage, and process allowance is better;
4, multiple high concentration fixed charge district equally arranges, and structure parameter optimizing relation is simple.Especially, when layout design, because fixed charge district is equidistantly distribution, the requirement of device directional contraposition is reduced.
5, on dielectric buried layer, have the silicon window of heat radiation, thus form PSOI structure, while raising is withstand voltage, self-heating effect can be alleviated further;
6, will equidistant fixed charge island SOI pressure-resistance structure be had be applicable to the SOI lateral power of all main flows, it is withstand voltage due to the remarkable enhancing of dielectric buried layer electric field comparatively conventional structure SOI device greatly improve.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing conventional n-type SOI LDMOS device.
Fig. 2 is a kind of equidistantly fixed charge island SOI pressure-resistance structure schematic diagram of the present invention.
Fig. 3 is the another kind of equidistantly fixed charge island SOI pressure-resistance structure schematic diagram of the present invention.
Fig. 4 is the structural representation of a kind of equidistant fixed charge island of the present invention SOI LDMOS device.
Fig. 5 a is the two-dimentional equipotential lines distribution map of the present invention's equidistant fixed charge island SOI LDMOS device when reaching breakdown conditions.Fig. 5 b is the two-dimentional equipotential lines distribution map of conventional SOI LDMOS device when reaching breakdown conditions.
Fig. 6 is the present invention's equidistant fixed charge island SOI LDMOS device and conventional SOI LDMOS device longitudinal electric field distribution map when reaching breakdown conditions.
Fig. 7 is the structural representation of a kind of equidistant fixed charge island of the present invention SOI IGBT device.
Fig. 8 is the structural representation of a kind of equidistant fixed charge island of the present invention SOI power diode component.
Mark in figure: 1, source electrode, 2, source region, 3, grid, 4, active layer, 5, drain region, 6, drain, 7, channel region, 8, substrate layer, 9, dielectric buried layer, 10, high concentration fixed charge district, 11, negative electrode, 12, negative electrode charged region, 13, anode charged region, 14, anode, 15, heat radiation silicon window.
Embodiment
Embodiment 1:
A kind of equidistantly fixed charge island SOI pressure-resistance structure, as shown in Figure 2, this pressure-resistance structure at least comprises substrate layer 8, dielectric buried layer 9 and active layer 4, and substrate layer 8, dielectric buried layer 9 and active layer 4 stack from bottom to top successively.Substrate layer 8, dielectric buried layer 9 are identical or close with the basic structure of the existing power device of prior art with the structure of active layer 4.The material of wherein said active layer 4 can be Si, SiC, GaAs, SiGe, GaN or other semi-conducting materials.The material of described dielectric buried layer 9 can be SiO2 or low-k materials, and wherein low-k materials (low-k) can be carbon doped oxide or SiOF.But the material of the material of active layer 4 and dielectric buried layer 9 is not limited to above-mentioned cited material.Above-mentioned dielectric buried layer 9 can be a complete horizontal expansion structure, and completely by substrate layer 8 and active layer 4 longitudinally-spaced; Also can be as shown in Figure 3, dielectric buried layer 9 is offered the heat radiation silicon window 15 of up/down perforation substrate layer 8 and active layer 4, this heat radiation silicon window 15 for heat radiation, to alleviate self-heating effect further, now, certain media buried regions 9 is provided with between substrate layer 8 and active layer 4.In order to improve the withstand voltage of SOI device, the present invention is in described dielectric buried layer 9 in four corner or be provided with multiple high concentration fixed charge district 10 in part range.
Described high concentration fixed charge district 10 is medium material, and charge polarity is just.In the present invention, described high concentration fixed charge district 10 is by ion implantation mode in dielectric buried layer 9, and its ion injected is the cations such as caesium, sodium, iodine, boron and silicon.The injection figure in each high concentration fixed charge district 10 is circle, rectangle, trapezoidal, triangle, square or hexagon.All high concentration fixed charge districts 10 can adopt same to inject figure, also can adopt different injection figures.In addition, the height in all high concentration fixed charge districts 10 and its shape are without direct relation, and it highly can be equal, also can be unequal.But in order to simplify production technology, in a preferred embodiment of the invention, all high concentration fixed charge districts 10 all adopt same inject figure, and the height in each high concentration fixed charge district 10 and size all consistent.
The concentration in each high concentration fixed charge district 10 is more than or equal to 1 × 10
13cm
-2.The concentration in all high concentration fixed charge districts 10 can be equal, also can be unequal.But in order to reduce the quantity of mask plate, in a preferred embodiment of the invention, the concentration in all high concentration fixed charge districts 10 can be equal.Owing to being without fixed charge district or low concentration fixed charge district for dielectric buried layer 9 between each high concentration fixed charge district 10, fixed charge polarity is plus or minus, therefore when high concentration fixed charge district 10 is higher compared to the concentration of dielectric buried layer 9, can in the formation hole, surface of dielectric buried layer 9, thus amplified medium buried regions 9 electric field strength, effectively improve withstand voltage.
In the inside of dielectric buried layer 9, multiple high concentration fixed charge district 10 is arranged in being interrupted each other, its mode of being interrupted is equally spaced discontinuous manner, namely described high concentration fixed charge district 10 equally distributes in the inside of dielectric buried layer 9, and the distance namely between every 2 high concentration fixed charge districts 10 is equal.In the present invention, only need the top each high concentration fixed charge district 10 being injected into dielectric buried layer 9, its degree of depth imbedded can be identical or different.For reducing processing step, the top in all high concentration fixed charge districts 10 is preferably equal to the distance of dielectric buried layer 9 upper surface.
Embodiment 2:
There is a SOI power device for equidistant fixed charge island SOI pressure-resistance structure, i.e. SOI LDMOS device, as shown in Figure 4, comprise the substrate layer 8, dielectric buried layer 9 and the active layer 4 that stack successively from bottom to top.On both sides in described active layer 4, edge is provided with source region 2, channel region 7 and drain region 5.Source region 2 and channel region 7 are affixed, and edge on the side being simultaneously arranged on active layer 4.Edge on the opposite side that 5, drain region is arranged on active layer 4.The surface of active layer 4 is provided with source electrode 1, grid 3 and drain electrode 6.Source electrode 1 is overlying on the top in source region 2, and grid 3 is overlying on the top of source region 2 and channel region 7 simultaneously.Drain electrode 6 is overlying on the top in drain region 5.Describedly bury in dielectric layer the multiple high concentration fixed charge districts 10 be also provided with further as described in example 1 above; These high concentration fixed charge districts 10 are formed by dielectric material, and charge polarity is just; These high concentration fixed charge districts 10 are all positioned at the top of dielectric buried layer 9, and arrange in being interrupted each other, and equally distribute.
When power device blocks resistance to pressure condition, act in Coulomb force, movable interface charge-the hole of high concentration can be produced directly between every two high concentration fixed charge districts 10, the electric field of active layer 4 silicon side is reduced, electric field simultaneously in remarkable amplified medium buried regions 9, longitudinal direction is withstand voltage to be born primarily of dielectric buried layer 9, thus significantly improves puncture voltage.
Under the parameter of identical structure, optimization: have the SOI LDMOS two dimension equipotential lines distribution of equidistant fixed charge island SOI pressure-resistance structure as Fig. 5 a, its reverse breakdown voltage is 597V; Conventional SOI LDMOS two dimension equipotential lines distribution is as Fig. 5 b, and its reverse breakdown voltage is 208V.Longitudinal electric field when having the reverse breakdown of the SOI LDMOS of equidistant fixed charge island SOI pressure-resistance structure and the SOI LDMOS of routine is distributed as Fig. 6, and its electric field having in the SOI LDMOS dielectric buried layer 9 of SOI pressure-resistance structure is 5.8 × 10
6v/cm, the electric field in the SOI LDMOS dielectric buried layer 9 of its routine is 0.9 × 10
6v/cm.
Embodiment 3:
Another kind has the SOI power device of equidistant fixed charge island SOI pressure-resistance structure, i.e. SOI IGBT device, as shown in Figure 7, comprises the substrate layer 8, dielectric buried layer 9 and the active layer 4 that stack successively from bottom to top.On both sides in described active layer 4, edge is provided with negative electrode charged region 12, channel region 7 and anode charged region 13.Negative electrode charged region 12 and channel region 7 are affixed, and edge on the side being simultaneously arranged on active layer 4.Edge on the opposite side that anode charged region 13 is arranged on active layer 4.The surface of active layer 4 is provided with negative electrode 11, grid 3 and anode 14.Negative electrode 11 is overlying on the top of negative electrode charged region 12, and grid 3 is overlying on the top of negative electrode charged region 12 and channel region 7 simultaneously.Anode 14 is overlying on the top of anode charged region 13.Describedly bury in dielectric layer the multiple high concentration fixed charge districts 10 be also provided with further as described in example 1 above; These high concentration fixed charge districts 10 are formed by dielectric material, and charge polarity is just; These high concentration fixed charge districts 10 are all positioned at the top of dielectric buried layer 9, and arrange in being interrupted each other, and equally distribute.
Embodiment 4:
Another has the SOI power device of equidistant fixed charge island SOI pressure-resistance structure, i.e. SOI power diode component, as shown in Figure 8, comprises the substrate layer 8, dielectric buried layer 9 and the active layer 4 that stack successively from bottom to top.On both sides in described active layer 4, corner place is provided with negative electrode charged region 12 and anode charged region 13 respectively.The surface of active layer 4 is provided with negative electrode 11 and anode 14.Negative electrode 11 is overlying on the top of negative electrode charged region 12.Anode 14 is overlying on the top of anode charged region 13.Describedly bury in dielectric layer the multiple high concentration fixed charge districts 10 be also provided with further as described in example 1 above; These high concentration fixed charge districts 10 are formed by dielectric material, and charge polarity is just; These high concentration fixed charge districts 10 are all positioned at the top of dielectric buried layer 9, and arrange in being interrupted each other, and equally distribute.
The present invention is not limited only to above-described embodiment, as not only can designed equidistant fixed charge island SOI pressure-resistance structure being applied in diode and power MOS (Metal Oxide Semiconductor) device, can be used in power integrated circuit, as long as have in addition can the crystal structure of the substrate layer 8 of this pressure-resistance structure accommodating (i.e. high concentration fixed charge district 10), dielectric buried layer 9 and active layer 4 for this power device or circuit.
Claims (9)
1. an equidistant fixed charge island SOI pressure-resistance structure, comprise the substrate layer (8), dielectric buried layer (9) and the active layer (4) that stack successively from bottom to top, it is characterized in that: also comprise multiple concentration further and be more than or equal to 1 × 10
13cm
-2high concentration fixed charge district (10); These high concentration fixed charge districts (10) are formed by dielectric material, and charge polarity is just; These high concentration fixed charge districts (10) are all positioned at the top of dielectric buried layer (9), and arrange in being interrupted each other, and equally distribute.
2. one according to claim 1 equidistant fixed charge island SOI pressure-resistance structure, is characterized in that: the concentration of all high concentration fixed charge districts (10) is all equal.
3. one according to claim 1 equidistant fixed charge island SOI pressure-resistance structure, it is characterized in that: described high concentration fixed charge district (10) is injected in dielectric buried layer (9) by ion implantation mode, and the ion injected is caesium cation, sodium cation, iodine cation, boron cation and/or siliconium ion.
4. one according to claim 1 equidistant fixed charge island SOI pressure-resistance structure, is characterized in that: the height of all high concentration fixed charge districts (10) is all equal.
5. one according to claim 1 equidistant fixed charge island SOI pressure-resistance structure, is characterized in that: the top of all high concentration fixed charge districts (10) is equal to the distance of dielectric buried layer (9) upper surface.
6. one according to claim 1 equidistant fixed charge island SOI pressure-resistance structure, is characterized in that: the heat radiation silicon window (15) described dielectric buried layer (9) having up/down perforation substrate layer (8) and active layer (4).
7. there is in claim 1 ~ 6 the SOI power device described in any one with equidistant fixed charge island SOI pressure-resistance structure, it is characterized in that: comprise the substrate layer (8), dielectric buried layer (9) and the active layer (4) that stack successively from bottom to top; On both sides in described active layer (4), edge is provided with source region (2), channel region (7) and drain region (5); Source region (2) and channel region (7) are affixed, and edge on the side being simultaneously arranged on active layer (4); Edge on the opposite side that drain region (5) is then arranged on active layer (4); The surface of active layer (4) is provided with source electrode (1), grid (3) and drain electrode (6); Source electrode (1) is overlying on the top of source region (2), and grid (3) is overlying on the top of source region (2) and channel region (7) simultaneously; Drain electrode (6) is overlying on the top of drain region (5); It is characterized in that: described in bury in dielectric layer and be also provided with multiple high concentration fixed charge district (10) further; These high concentration fixed charge districts (10) are formed by dielectric material, and charge polarity is just; These high concentration fixed charge districts (10) are all positioned at the top of dielectric buried layer (9), and arrange in being interrupted each other, and equally distribute.
8. there is in claim 1 ~ 6 the SOI power device described in any one with equidistant fixed charge island SOI pressure-resistance structure, it is characterized in that: comprise the substrate layer (8), dielectric buried layer (9) and the active layer (4) that stack successively from bottom to top; On both sides in described active layer (4), edge is provided with negative electrode charged region (12), channel region (7) and anode charged region (13); Negative electrode charged region (12) and channel region (7) are affixed, and edge on the side being simultaneously arranged on active layer (4); Edge on the opposite side that anode charged region (13) is then arranged on active layer (4); The surface of active layer (4) is provided with negative electrode (11), grid (3) and anode (14); Negative electrode (11) is overlying on the top of negative electrode charged region (12), and grid (3) is overlying on the top of negative electrode charged region (12) and channel region (7) simultaneously; Anode (14) is overlying on the top of anode charged region (13); It is characterized in that: described in bury in dielectric layer and be also provided with multiple high concentration fixed charge district (10) further; These high concentration fixed charge districts (10) are formed by dielectric material, and charge polarity is just; These high concentration fixed charge districts (10) are all positioned at the top of dielectric buried layer (9), and arrange in being interrupted each other, and equally distribute.
9. there is in claim 1 ~ 6 the SOI power device described in any one with equidistant fixed charge island SOI pressure-resistance structure, it is characterized in that: comprise the substrate layer (8), dielectric buried layer (9) and the active layer (4) that stack successively from bottom to top; On both sides in described active layer (4), corner place is provided with negative electrode charged region (12) and anode charged region (13) respectively; The surface of active layer (4) is provided with negative electrode (11) and anode (14); Negative electrode (11) is overlying on the top of negative electrode charged region (12); Anode (14) is overlying on the top of anode charged region (13); It is characterized in that: described in bury in dielectric layer and be also provided with multiple high concentration fixed charge district (10) further; These high concentration fixed charge districts (10) are formed by dielectric material, and charge polarity is just; These high concentration fixed charge districts (10) are all positioned at the top of dielectric buried layer (9), and arrange in being interrupted each other, and equally distribute.
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