CN104269441B - SOI voltage resistance structure with charge regions fixed at equal intervals and SOI power device - Google Patents
SOI voltage resistance structure with charge regions fixed at equal intervals and SOI power device Download PDFInfo
- Publication number
- CN104269441B CN104269441B CN201410564619.5A CN201410564619A CN104269441B CN 104269441 B CN104269441 B CN 104269441B CN 201410564619 A CN201410564619 A CN 201410564619A CN 104269441 B CN104269441 B CN 104269441B
- Authority
- CN
- China
- Prior art keywords
- fixed charge
- layer
- active layer
- high concentration
- soi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000003989 dielectric material Substances 0.000 claims abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 150000002500 ions Chemical class 0.000 claims description 9
- 230000005611 electricity Effects 0.000 claims description 4
- 229910052792 caesium Inorganic materials 0.000 claims description 3
- FKNQFGJONOIPTF-UHFFFAOYSA-N Sodium cation Chemical compound [Na+] FKNQFGJONOIPTF-UHFFFAOYSA-N 0.000 claims description 2
- HYFJXBYGHMZZPQ-UHFFFAOYSA-N boron(1+) Chemical compound [B+] HYFJXBYGHMZZPQ-UHFFFAOYSA-N 0.000 claims description 2
- -1 caesium cation Chemical class 0.000 claims description 2
- OCVXZQOKBHXGRU-UHFFFAOYSA-N iodine(1+) Chemical compound [I+] OCVXZQOKBHXGRU-UHFFFAOYSA-N 0.000 claims description 2
- 230000005684 electric field Effects 0.000 abstract description 17
- 239000004065 semiconductor Substances 0.000 description 14
- 108091006146 Channels Proteins 0.000 description 12
- 230000015556 catabolic process Effects 0.000 description 12
- 239000000463 material Substances 0.000 description 12
- 230000000694 effects Effects 0.000 description 7
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 229910020177 SiOF Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- TVFDJXOCXUVLDH-UHFFFAOYSA-N caesium atom Chemical compound [Cs] TVFDJXOCXUVLDH-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 150000001768 cations Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- PNDPGZBMCMUPRI-UHFFFAOYSA-N iodine Chemical compound II PNDPGZBMCMUPRI-UHFFFAOYSA-N 0.000 description 1
- 230000035800 maturation Effects 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052708 sodium Inorganic materials 0.000 description 1
- 239000011734 sodium Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/408—Electrodes ; Multistep manufacturing processes therefor with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
Abstract
The invention discloses an SOI voltage resistance structure with charge regions fixed at equal intervals and a power device. The SOI voltage resistance structure comprises a substrate layer, a dielectric buried layer, an active layer and a plurality of high-concentration fixed charge regions with the concentration larger than or equal to 1*10＜13＞ cm＜-2＞, wherein the substrate layer, the dielectric buried layer, the active layer and the high-concentration fixed charge regions are stacked in sequence from top to bottom. The high-concentration fixed charge regions are made of a dielectric material, and the charge polarity is positive. The high-concentration fixed charge regions are all located on the dielectric buried layer, arranged in a spaced mode and distributed at equal intervals. According to the SOI voltage resistance structure with the charge regions fixed at equal intervals and the power device, the electric field of the dielectric buried layer can be greatly enhanced, and the voltage resistance capacity is effectively improved; a technology is easy to implement, and is completely compatible with a common CMOS technology.
Description
Technical field
The invention belongs to field of semiconductor, and in particular to a kind of equidistant fixed charge area SOI pressure-resistance structures
And SOI power device.
Background technology
SOI (Silicon On Insulator, the silicon in dielectric substrate) power device has high operating rate and collection
Cheng Du, reliable insulating properties, strong Radiation hardness and without controllable silicon self-locking effect, are widely used in power electronics, industry
The fields such as automation, Aero-Space and weaponry.
The breakdown voltage of SOI power device carries out ionization integral and calculating and obtains by electric field along pressure length, depending on longitudinal direction
It is pressure and it is horizontal it is pressure in smaller.SOI laterally pressure design principle can continue to use the silicon substrate principle and technology of maturation, for example
RESURF (Reduce SURface electric Field reduce surface field), variety lateral doping, field plate and super-junction structure
Deng.And because dielectric buried layer prevents the depletion region of device to extend to substrate, so SOI is longitudinally pressure can only be by top layer silicon and Jie
Matter buried regions undertakes.But limited by device architecture, self-heating effect and technique, top layer silicon and dielectric buried layer all can not be too thick,
So causing longitudinal direction pressure relatively low, become the main cause for limiting horizontal SOI power device and integrated circuit development and applying.
Typical conventional n-type SOI LDMOS (Lateral Double Diffused Metal Oxide
Semiconductor, lateral double diffusion metal oxide semiconductor) device structure, as shown in figure 1, it is mainly by source electrode,
N+ source regions, gate oxide, N-shaped active semiconductor layer, n+ drain regions, drain electrode, p-type channel region, p-substrate semiconductor layer and medium
Buried regions is constituted.For dielectric buried layer is SiO2Conventional SOI device, limited by Gauss theorem, medium during device breakdown is buried
Layer electric field EINeed to meet " E with semiconductor active layer electric field ESI=3ES”.Under regular situation, the critical breakdown electric field of silicon is 20-
40V/um, so during device breakdown, EI is only for about 100V/um, much not up to SiO2Critical breakdown electric field 600V/um with
On, so SiO2Pressure potentiality fail to be fully used.
In order to the longitudinal direction for improving SOI device is pressure, notification number discloses one for the Chinese invention patent of CN101477999A
" for power device with interface charge island SOI pressure-resistance structures " is planted, it is mainly by semiconductor substrate layer, dielectric buried layer and half
Conductor active layer.It is provided with the four corner or part range of the dielectric buried layer and the interface of semiconductor active layer and stretches
Enter the multiple high concentration n+ areas to the semiconductor active layer, the interval disconnected setting of multiple high concentrations n+, the high concentration n+ area
For semiconductor material, multiple high concentration n+ areas formation interface charge islands, the concentration range in high concentration n+ area is more than 1 × 1016cm-3。
The invention is provided with least one interface island buried regions in the active layer of conventional SOI power device on dielectric buried layer, active
The conduction type of layer is contrary with the conduction type of interface island buried regions.When drain electrode applies reversed bias voltage, while source, grid and substrate
During ground connection, the upper interface of dielectric buried layer will adaptively collect hole, and hole concentration is linearly increasing to leaking from source.Although, these
Interface hole can effectively increase dielectric buried layer electric field and improve pressure, but, the structure is affected larger by subsequent manufacturing procedures,
Silicon layer charge-islands are horizontally and vertically scalable serious during high temperature, and bring difficulty for thin silicone layer SOI device structure design.
The content of the invention
The technical problem to be solved is the resistance to voltage devices of the conventional SOI longitudinally resistance to deficiency forced down, there is provided one kind etc.
Spacing fixed charge area SOI pressure-resistance structures and SOI power device, it not only can greatly improve dielectric buried layer electric field, so as to have
Effect improves pressure；It is completely compatible with stand CMOS and technique is realized simply.
To solve the above problems, the present invention is achieved by the following technical solutions：
A kind of equidistant fixed charge area SOI pressure-resistance structures, including the substrate layer, dielectric buried layer that stack successively from bottom to top
And active layer, it is a difference in that：Multiple concentration are still further comprised more than or equal to 1 × 1013cm-2High concentration fixed charge
Area；These high concentration fixed charge areas are formed by dielectric material, and charge polarity is for just；These equal positions in high concentration fixed charge area
In dielectric buried layer top, and each other in interruption setting, and equally it is distributed.
In such scheme, the concentration in all high concentration fixed charge areas is preferably equal.
In such scheme, the high concentration fixed charge area is injected in dielectric buried layer by ion implanting mode, and is noted
The ion for entering is preferably caesium cation, sodium cation, iodine cation, boron cation and/or siliconium ion.
In such scheme, the height in all high concentration fixed charge areas is preferably equal.
In such scheme, the top in all high concentration fixed charge areas is preferably equal to the distance of dielectric buried layer upper surface.
In such scheme, the radiating silicon window of up/down perforation substrate layer and active layer is preferably provided with the dielectric buried layer.
SOI power device with above-mentioned equidistant fixed charge island SOI pressure-resistance structures, i.e. SOI LDMOS are (laterally double to expand
Dispersed metallic oxide semiconductor) device, including the substrate layer, dielectric buried layer and active layer that stack successively from bottom to top；It is described to have
Edge arranges active area, channel region and drain region on both sides in active layer；Source region and channel region are affixed, and while are arranged on active
Edge on the side of layer；Drain region is then arranged on edge on the opposite side of active layer；The surface of active layer is provided with source electrode, grid
And drain electrode；Source electrode is overlying on the top of source region, and grid is overlying on the top of source region and channel region simultaneously；Drain electrode is overlying on the top in drain region；
It is a difference in that described burying in dielectric layer is also further provided with multiple high concentration fixed charge areas；These high concentrations fix electricity
He Qu is formed by dielectric material, and charge polarity is for just；These high concentration fixed charge areas are respectively positioned on the top of dielectric buried layer, and
Arrange in interruption each other, and be equally distributed.
SOI power device with above-mentioned equidistant fixed charge island SOI pressure-resistance structures, i.e. (insulated gate is double for SOI IGBT
Bipolar transistor) device, including the substrate layer, dielectric buried layer and active layer that stack successively from bottom to top；In the active layer
Edge is provided with negative electrode charged region, channel region and anode charged region on both sides；Negative electrode charged region and channel region are affixed, and while
It is arranged on edge on the side of active layer；Anode charged region is then arranged on edge on the opposite side of active layer；Active layer
Surface is provided with negative electrode, grid and anode；Negative electrode is overlying on the top of negative electrode charged region, and grid is overlying on negative electrode charged region and raceway groove simultaneously
The top in area；Anode is overlying on the top of anode charged region；It is a difference in that, it is described bury also be further provided with dielectric layer it is multiple
High concentration fixed charge area；These high concentration fixed charge areas are formed by dielectric material, and charge polarity is for just；These high concentrations
Fixed charge area is respectively positioned on the top of dielectric buried layer, and each other in interruption setting, and be equally distributed.
SOI power device with above-mentioned equidistant fixed charge island SOI pressure-resistance structures, i.e. power diode device, bag
Include substrate layer, dielectric buried layer and the active layer for stacking successively from bottom to top；Set respectively at corner on both sides in the active layer
It is equipped with negative electrode charged region and anode charged region；The surface of active layer is provided with negative electrode and anode；Negative electrode is overlying on the upper of negative electrode charged region
Side；Anode is overlying on the top of anode charged region；It is a difference in that described burying in dielectric layer is also further provided with multiple high concentrations
Fixed charge area；These high concentration fixed charge areas are formed by dielectric material, and charge polarity is for just；These high concentrations fix electricity
He Qu is respectively positioned on the top of dielectric buried layer, and each other in interruption setting, and be equally distributed.
Compared with prior art, the present invention has following features：
1st, high concentration fixed charge area acts on dielectric buried layer directly over it and semiconductor active layer by Coulomb force
Interface shape high concentration electric sub-district, can accumulate the hole of high concentration again between two adjacent electronic areas, substantially increase and bury Jie
The interface charge of matter layer surface.According to Gauss theorem, interface charge meeting amplified medium buried regions electric-field intensity, so as to effectively improve
Longitudinal direction is pressure；
2nd, the material in high concentration fixed charge area is medium, can be directly to realize using ion implanting by the way of, and note
The cation for entering diffusion coefficient in dielectric buried layer is very little, is approximately fixed charge, is hardly obtained shadow by subsequent high temperature processes
Ring, while completely compatible with conventional cmos/SOI technology, technique is realized simple；Further, since the material in high concentration fixed charge area
Matter is medium, compared with the structure of existing change dielectric buried layer shape, will not adopt excessive insulating materials, also just not attached
Plus self-heating effect produce；
3rd, the fixed charge area concentration range of high concentration is equal to or more than 1 × 1013cm-2, during equal to or more than the value, Gu
Determine concentration of electric charges to have little to no effect breakdown voltage, process allowance is preferable；
4th, multiple high concentration fixed charge areas equally arrange, and structure parameter optimizing relation is simple.Especially set in domain
Timing, because fixed charge area is equidistantly distributed, reduces the requirement of device directional contraposition.
5th, the silicon window of radiating is provided with dielectric buried layer, so as to form PSOI structures, can be entered while improving pressure
One step alleviates self-heating effect；
6th, the SOI lateral powers of all main flows will be applied to equidistant fixed charge island SOI pressure-resistance structures, its
It is pressure that due to significantly increasing for dielectric buried layer electric field, more conventional structure SOI device is greatly improved.
Description of the drawings
Fig. 1 is the structural representation of existing conventional n-type SOI LDMOS device.
Fig. 2 is a kind of equidistant fixed charge island SOI pressure-resistance structure schematic diagrames of the present invention.
Fig. 3 is another kind of equidistantly fixed charge island SOI pressure-resistance structure schematic diagrames of the invention.
Fig. 4 is a kind of structural representation of equidistant fixed charge island SOI LDMOS devices of the present invention.
Fig. 5 a are that two-dimentional equipotential lines when equidistantly fixed charge island SOI LDMOS devices of the invention reach breakdown conditions is divided
Butut.Fig. 5 b are two-dimentional equipotential lines distribution maps when conventional SOI LDMOS devices reach breakdown conditions.
Fig. 6 is that equidistant fixed charge island SOI LDMOS devices of the invention and routine SOI LDMOS devices reach and puncture shape
Longitudinal electric field distribution map during state.
Fig. 7 is a kind of structural representation of equidistant fixed charge island SOI IGBT devices of the present invention.
Fig. 8 is a kind of structural representation of equidistant fixed charge island SOI power diode component of the present invention.
Mark in figure：1st, source electrode, 2, source region, 3, grid, 4, active layer, 5, drain region, 6, drain electrode, 7, channel region, 8, substrate
Layer, 9, dielectric buried layer, 10, high concentration fixed charge area, 11, negative electrode, 12, negative electrode charged region, 13, anode charged region, 14, sun
Pole, 15, radiating silicon window.
Specific embodiment
Embodiment 1：
A kind of equidistant fixed charge island SOI pressure-resistance structures, as shown in Fig. 2 the pressure-resistance structure at least include substrate layer 8,
Dielectric buried layer 9 and active layer 4, and substrate layer 8, dielectric buried layer 9 and active layer 4 stack successively from bottom to top.Substrate layer 8, medium
The structure of buried regions 9 and active layer 4 is same or like seemingly with the basic structure of the existing power device of prior art.It is wherein described to have
The material of active layer 4 can be Si, SiC, GaAs, SiGe, GaN or other semi-conducting materials.The material of the dielectric buried layer 9 can be with
It is SiO2 or low-k materials, wherein low-k materials (low-k) can be carbon doped oxide or SiOF.But the material of active layer 4
The material of matter and dielectric buried layer 9 is not limited to above-mentioned cited material.Above-mentioned dielectric buried layer 9 complete can be extended laterally for one
Structure, and completely by substrate layer 8 and active layer 4 is longitudinally spaced opens；Can also be as shown in figure 3, opening up on dielectric buried layer 9 up and down
The radiating silicon window 15 of Through-substrate layer 8 and active layer 4, the radiating silicon window 15 is used to radiate, further to alleviate from thermal effect
Should, now, certain media buried regions 9 is provided between substrate layer 8 and active layer 4.In order to improve the pressure of SOI device, the present invention exists
Multiple high concentration fixed charge areas 10 are provided with the dielectric buried layer 9 in four corner or in part range.
The high concentration fixed charge area 10 is medium material, and charge polarity is for just.In the present invention, the high concentration
Fixed charge area 10 by ion implanting mode to dielectric buried layer 9, the ion of its injection be caesium, sodium, iodine, boron and silicon etc. just from
Son.The injection figure in each high concentration fixed charge area 10 is circle, rectangle, trapezoidal, triangle, square or hexagon.Institute
There is high concentration fixed charge area 10 to adopt same injection figure, it would however also be possible to employ different injection figures.Additionally, all
The height in high concentration fixed charge area 10 is with its shape without direct relation, and it highly can be with equal, it is also possible to unequal.But in order to
Simplify production technology, in a preferred embodiment of the invention, all high concentration fixed charge areas 10 adopt same injection figure,
And the height and size in each high concentration fixed charge area 10 are consistent.
The concentration in each high concentration fixed charge area 10 is more than or equal to 1 × 1013cm-2.All high concentration fixed charge areas 10
Concentration can be with equal, it is also possible to it is unequal.But in order to reduce the quantity of mask plate, in a preferred embodiment of the invention, own
The concentration in high concentration fixed charge area 10 can be with equal.Due to being for dielectric buried layer 9 between each high concentration fixed charge area 10
Without fixed charge area or low concentration fixed charge area, fixed charge polarity is positive or negative, therefore when high concentration fixed charge area 10
When higher compared to the concentration of dielectric buried layer 9, hole can be formed on the surface of dielectric buried layer 9, so as to the electric field of amplified medium buried regions 9
Intensity, effectively improves pressure.
In the inside of dielectric buried layer 9, multiple high concentration fixed charge areas 10 are arranged each other in interruption, the side of its interruption
Formula is equidistant discontinuous manner, i.e., described high concentration fixed charge area 10 is equally distributed in the inside of dielectric buried layer 9, i.e.,
It is equal per the distance between 2 high concentration fixed charge areas 10.In the present invention, it is only necessary to by each high concentration fixed charge area
10 tops for being injected into dielectric buried layer 9, the depth of its embedment can be with identical or different.To reduce processing step, Suo Yougao
The top in concentration fixed charge area 10 is preferably equal to the distance of the upper surface of dielectric buried layer 9.
Embodiment 2：
A kind of SOI power device with equidistant fixed charge island SOI pressure-resistance structures, i.e. SOI LDMOS devices, such as scheme
Shown in 4, including the substrate layer 8, dielectric buried layer 9 and active layer 4 that stack successively from bottom to top.On both sides in the active layer 4
Edge arranges active area 2, channel region 7 and drain region 5.Source region 2 and channel region 7 are affixed, and while are arranged on the side of active layer 4
Upper edge.Drain region 5 is then arranged on edge on the opposite side of active layer 4.The surface of active layer 4 is provided with source electrode 1, the and of grid 3
Drain electrode 6.Source electrode 1 is overlying on the top of source region 2, and grid 3 is overlying on the top of source region 2 and channel region 7 simultaneously.Drain electrode 6 is overlying on drain region 5
Top.It is described to bury the multiple high concentration fixed charge areas 10 being also further provided with dielectric layer as described in example 1 above；These are high
Concentration fixed charge area 10 is formed by dielectric material, and charge polarity is for just；These high concentration fixed charge areas 10 are respectively positioned on Jie
The top of matter buried regions 9, and each other in interruption setting, and be equally distributed.
When power device blocks resistance to pressure condition, act in Coulomb force, between each two high concentration fixed charge area 10
Surface can produce the movable interface charge-hole of high concentration so that the electric field of the silicon side of active layer 4 is reduced, while significantly increasing
Electric field in strong medium buried regions 9, longitudinal direction is pressure mainly to be undertaken by dielectric buried layer 9, so as to significantly improve breakdown voltage.
Under identical structure, the parameter of optimization：SOI LDMOS with equidistant fixed charge island SOI pressure-resistance structures
Two-dimentional equipotential lines distribution such as Fig. 5 a, its breakdown reverse voltage is 597V；Conventional SOI LDMOS two dimension equipotential lines distributions are as schemed
5b, its breakdown reverse voltage is 208V.The SOI of the SOI LDMOS with equidistant fixed charge island SOI pressure-resistance structures and routine
The longitudinal electric field during reverse breakdown of LDMOS is distributed as Fig. 6, and it has in the SOI LDMOS dielectric buried layers 9 of SOI pressure-resistance structures
Electric field be 5.8 × 106Electric field in V/cm, its conventional SOI LDMOS dielectric buried layer 9 is 0.9 × 106V/cm。
Embodiment 3：
SOI power device of the another kind with equidistant fixed charge island SOI pressure-resistance structures, i.e. SOI IGBT devices, such as
Shown in Fig. 7, including the substrate layer 8, dielectric buried layer 9 and active layer 4 that stack successively from bottom to top.Both sides in the active layer 4
Upper edge is provided with negative electrode charged region 12, channel region 7 and anode charged region 13.Negative electrode charged region 12 and channel region 7 are affixed, and
It is arranged on edge on the side of active layer 4 simultaneously.Anode charged region 13 is then arranged on edge on the opposite side of active layer 4.
The surface of active layer 4 is provided with negative electrode 11, grid 3 and anode 14.Negative electrode 11 is overlying on the top of negative electrode charged region 12, and grid 3 is simultaneously
It is overlying on the top of negative electrode charged region 12 and channel region 7.Anode 14 is overlying on the top of anode charged region 13.It is described to bury in dielectric layer also
It is further provided with multiple high concentration fixed charge areas 10 as described in example 1 above；These high concentration fixed charge areas 10 are by being situated between
Material is formed, and charge polarity is for just；These high concentration fixed charge areas 10 are respectively positioned on the top of dielectric buried layer 9, and mutually
Between arrange in interruption, and be equally distributed.
Embodiment 4：
Another has the SOI power device of equidistant fixed charge island SOI pressure-resistance structures, i.e. SOI power diode device
Part, as shown in figure 8, including the substrate layer 8, dielectric buried layer 9 and active layer 4 that stack successively from bottom to top.In the active layer 4
It is provided with negative electrode charged region 12 and anode charged region 13 on both sides at corner respectively.The surface of active layer 4 is provided with negative electrode 11 and sun
Pole 14.Negative electrode 11 is overlying on the top of negative electrode charged region 12.Anode 14 is overlying on the top of anode charged region 13.It is described to bury in dielectric layer
Also it is further provided with multiple high concentration fixed charge areas 10 as described in example 1 above；These high concentration fixed charge areas 10 by
Dielectric material is formed, and charge polarity is for just；These high concentration fixed charge areas 10 are respectively positioned on the top of dielectric buried layer 9, and phase
Arrange in interruption between mutually, and be equally distributed.
The present invention is not limited only to above-described embodiment, such as not only can be pressure by designed equidistant fixed charge island SOI
Structure is applied in diode and power MOS (Metal Oxide Semiconductor) device, can be used in power integrated circuit, if the power device or
Circuit also has can house the substrate layer 8 of the pressure-resistance structure (i.e. high concentration fixed charge area 10), dielectric buried layer 9 and active
The crystal structure of layer 4.
Claims (9)
1. a kind of equidistant fixed charge island SOI pressure-resistance structures, bury including the substrate layer (8), medium for stacking successively from bottom to top
Layer (9) and active layer (4), it is characterised in that：Multiple concentration are still further comprised more than or equal to 1 × 1013cm-2High concentration consolidate
Determine charged region (10)；These high concentration fixed charge areas (10) are formed by dielectric material, and charge polarity is for just；These high concentrations
Fixed charge area (10) is respectively positioned on the top of dielectric buried layer (9), and each other in interruption setting, and be equally distributed.
2. a kind of equidistant fixed charge island SOI pressure-resistance structures according to claim 1, it is characterised in that：It is all highly concentrated
The concentration of degree fixed charge area (10) is equal.
3. a kind of equidistant fixed charge island SOI pressure-resistance structures according to claim 1, it is characterised in that：It is described highly concentrated
Degree fixed charge area (10) is injected in dielectric buried layer (9) by ion implanting mode, and the ion for injecting is caesium cation, sodium
Cation, iodine cation, boron cation and/or siliconium ion.
4. a kind of equidistant fixed charge island SOI pressure-resistance structures according to claim 1, it is characterised in that：It is all highly concentrated
The height of degree fixed charge area (10) is equal.
5. a kind of equidistant fixed charge island SOI pressure-resistance structures according to claim 1, it is characterised in that：It is all highly concentrated
The top of degree fixed charge area (10) is equal to the distance of dielectric buried layer (9) upper surface.
6. a kind of equidistant fixed charge island SOI pressure-resistance structures according to claim 1, it is characterised in that：The medium
Radiating silicon window (15) of up/down perforation substrate layer (8) and active layer (4) is provided with buried regions (9).
7. there is the SOI power described in any one in claim 1～6 with equidistant fixed charge island SOI pressure-resistance structures
Device, it is characterised in that：Including the substrate layer (8), dielectric buried layer (9) and active layer (4) that stack successively from bottom to top；It is described to have
Edge arranges active area (2), channel region (7) and drain region (5) on both sides in active layer (4)；Source region (2) and channel region (7) phase
Patch, and while it is arranged on edge on the side of active layer (4)；Drain region (5) is then arranged on corner on the opposite side of active layer (4)
Place；The surface of active layer (4) is provided with source electrode (1), grid (3) and drain electrode (6)；Source electrode (1) is overlying on the top of source region (2), grid
(3) while being overlying on the top of source region (2) and channel region (7)；Drain electrode (6) is overlying on the top of drain region (5)；It is characterized in that：It is described
Multiple high concentration fixed charge areas (10) are also further provided with dielectric buried layer (9)；These high concentration fixed charge areas (10) by
Dielectric material is formed, and charge polarity is for just；These high concentration fixed charge areas (10) are respectively positioned on the top of dielectric buried layer (9),
And each other in interruption setting, and be equally distributed.
8. there is the SOI power described in any one in claim 1～6 with equidistant fixed charge island SOI pressure-resistance structures
Device, it is characterised in that：Including the substrate layer (8), dielectric buried layer (9) and active layer (4) that stack successively from bottom to top；It is described to have
Edge is provided with negative electrode charged region (12), channel region (7) and anode charged region (13) on both sides in active layer (4)；Negative electrode electricity
He Qu (12) and channel region (7) are affixed, and while are arranged on edge on the side of active layer (4)；Anode charged region (13) is then
It is arranged on edge on the opposite side of active layer (4)；The surface of active layer (4) is provided with negative electrode (11), grid (3) and anode
(14)；Negative electrode (11) is overlying on the top of negative electrode charged region (12), and grid (3) is while be overlying on negative electrode charged region (12) and channel region
(7) top；Anode (14) is overlying on the top of anode charged region (13)；It is characterized in that：Also enter one in the dielectric buried layer (9)
Step is provided with multiple high concentration fixed charge areas (10)；These high concentration fixed charge areas (10) are formed by dielectric material, and electric charge
Polarity is for just；These high concentration fixed charge areas (10) are respectively positioned on the top of dielectric buried layer (9), and set in interruption each other
Put, and be equally distributed.
9. there is the SOI power described in any one in claim 1～6 with equidistant fixed charge island SOI pressure-resistance structures
Device, it is characterised in that：Including the substrate layer (8), dielectric buried layer (9) and active layer (4) that stack successively from bottom to top；It is described to have
It is provided with negative electrode charged region (12) and anode charged region (13) on both sides in active layer (4) at corner respectively；The table of active layer (4)
Face is provided with negative electrode (11) and anode (14)；Negative electrode (11) is overlying on the top of negative electrode charged region (12)；Anode (14) is overlying on anode electricity
The top of He Qu (13)；It is characterized in that：Multiple high concentration fixed charge areas are also further provided with the dielectric buried layer (9)
(10)；These high concentration fixed charge areas (10) are formed by dielectric material, and charge polarity is for just；These high concentration fixed charges
Area (10) is respectively positioned on the top of dielectric buried layer (9), and each other in interruption setting, and be equally distributed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410564619.5A CN104269441B (en) | 2014-10-22 | 2014-10-22 | SOI voltage resistance structure with charge regions fixed at equal intervals and SOI power device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410564619.5A CN104269441B (en) | 2014-10-22 | 2014-10-22 | SOI voltage resistance structure with charge regions fixed at equal intervals and SOI power device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104269441A CN104269441A (en) | 2015-01-07 |
| CN104269441B true CN104269441B (en) | 2017-05-10 |
Family
ID=52160948
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410564619.5A Active CN104269441B (en) | 2014-10-22 | 2014-10-22 | SOI voltage resistance structure with charge regions fixed at equal intervals and SOI power device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104269441B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106876441B (en) * | 2017-02-17 | 2020-07-07 | 桂林电子科技大学 | Power device with fixed interface charge field limiting ring |
| CN106847925B (en) * | 2017-02-17 | 2020-07-07 | 桂林电子科技大学 | Power device with surface inversion type fixed interface charges |
| CN106803518B (en) * | 2017-02-17 | 2020-07-03 | 桂林电子科技大学 | Power device based on field oxide layer electric field modulation |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101083278A (en) * | 2006-10-25 | 2007-12-05 | 电子科技大学 | Pressure resistant layer structure having dual-medium buried layer and SOI power device using the same |
| CN101477999A (en) * | 2009-01-19 | 2009-07-08 | 电子科技大学 | SOI voltage resistant structure having interface charge island for power device |
| CN102142460A (en) * | 2010-12-29 | 2011-08-03 | 电子科技大学 | SOI (Silicon On Insulator) type P-LDMOS (Lateral Diffused Metal-Oxide Semiconductor) |
| CN102361031A (en) * | 2011-10-19 | 2012-02-22 | 电子科技大学 | Semiconductor device used for SOI (silicon-on-insulator) high-voltage integrated circuit |
| CN102790092A (en) * | 2012-08-24 | 2012-11-21 | 电子科技大学 | Transverse high-voltage DMOS (double-diffusion metal oxide semiconductor) device |
| CN204179089U (en) * | 2014-10-22 | 2015-02-25 | 桂林电子科技大学 | Equidistant fixed charge district SOI pressure-resistance structure and SOI power device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004102672A1 (en) * | 2003-05-13 | 2004-11-25 | Cambridge Semiconductor Limited | Lateral soi semiconductor device |
| WO2010014281A1 (en) * | 2008-07-30 | 2010-02-04 | Maxpower Semiconductor Inc. | Semiconductor on insulator devices containing permanent charge |
-
2014
- 2014-10-22 CN CN201410564619.5A patent/CN104269441B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101083278A (en) * | 2006-10-25 | 2007-12-05 | 电子科技大学 | Pressure resistant layer structure having dual-medium buried layer and SOI power device using the same |
| CN101477999A (en) * | 2009-01-19 | 2009-07-08 | 电子科技大学 | SOI voltage resistant structure having interface charge island for power device |
| CN102142460A (en) * | 2010-12-29 | 2011-08-03 | 电子科技大学 | SOI (Silicon On Insulator) type P-LDMOS (Lateral Diffused Metal-Oxide Semiconductor) |
| CN102361031A (en) * | 2011-10-19 | 2012-02-22 | 电子科技大学 | Semiconductor device used for SOI (silicon-on-insulator) high-voltage integrated circuit |
| CN102790092A (en) * | 2012-08-24 | 2012-11-21 | 电子科技大学 | Transverse high-voltage DMOS (double-diffusion metal oxide semiconductor) device |
| CN204179089U (en) * | 2014-10-22 | 2015-02-25 | 桂林电子科技大学 | Equidistant fixed charge district SOI pressure-resistance structure and SOI power device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104269441A (en) | 2015-01-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8264033B2 (en) | Semiconductor device having a floating semiconductor zone | |
| US10020388B2 (en) | Insulated gate bipolar transistor including charge injection regions | |
| CN102376762B (en) | Super junction LDMOS(Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof | |
| CN104241376A (en) | Super junction structure, preparation method of super junction structure and semiconductor device | |
| CN101969073A (en) | Rapid superjunction longitudinal double-diffusion metal oxide semiconductor transistor | |
| CN106816468B (en) | Lateral diffusion metal oxide semiconductor field effect transistor with RESURF structure | |
| CN103280457B (en) | A kind of horizontal high voltage power device of Ultra-low Specific conducting resistance and manufacture method | |
| CN103199104B (en) | A kind of crystal circle structure and apply its power device | |
| CN104518007B (en) | Semiconductor device | |
| CN102194818A (en) | P-type epitaxial layer-based binary coded decimal (BCD) integrated device and manufacturing method thereof | |
| CN103337498A (en) | BCD semiconductor device and manufacturing method thereof | |
| CN107658214A (en) | A kind of low on-resistance silicon carbide MOSFET device and preparation method with floating area of double grooves | |
| CN104269441B (en) | SOI voltage resistance structure with charge regions fixed at equal intervals and SOI power device | |
| CN204102902U (en) | Linear pitch distribution fixed charge island SOI pressure-resistance structure and power device | |
| CN107731922B (en) | A kind of low on-resistance silicon carbide super-junction MOSFET device and preparation method with floating area | |
| CN204179089U (en) | Equidistant fixed charge district SOI pressure-resistance structure and SOI power device | |
| JP2008060152A (en) | Semiconductor device, and its manufacturing method | |
| CN103730355B (en) | A kind of manufacture method of super-junction structure | |
| CN104269403B (en) | Linear spacing distribution fixed charge island SOI pressure-resistance structures and power device | |
| CN104201203B (en) | High withstand voltage LDMOS device and manufacture method thereof | |
| CN203941904U (en) | Based on SOI pressure-resistance structure and the power device of folding drift region | |
| CN109994549B (en) | Semiconductor power device | |
| CN113363322A (en) | N-channel groove type VDMOS and groove type IGBT | |
| CN104505403A (en) | SOI power device with medium layer fixed charges | |
| CN109994468B (en) | Semiconductor super junction power device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |