CN102088022A - Laterally diffused metal oxide semiconductor (LDMOS) and manufacturing method thereof - Google Patents
Laterally diffused metal oxide semiconductor (LDMOS) and manufacturing method thereof Download PDFInfo
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- CN102088022A CN102088022A CN200910201890.1A CN200910201890A CN102088022A CN 102088022 A CN102088022 A CN 102088022A CN 200910201890 A CN200910201890 A CN 200910201890A CN 102088022 A CN102088022 A CN 102088022A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000004065 semiconductor Substances 0.000 title description 2
- 229910044991 metal oxide Inorganic materials 0.000 title 1
- 150000004706 metal oxides Chemical class 0.000 title 1
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 15
- 238000005516 engineering process Methods 0.000 claims description 24
- 238000005468 ion implantation Methods 0.000 claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000000407 epitaxy Methods 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000035755 proliferation Effects 0.000 description 1
- 238000007363 ring formation reaction Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure
Abstract
The invention discloses an LDMOS. Two PN junctions isolated are arranged between a drain end (181) and a substrate (10). The P area of the first PN junction is a p-shaped substrate (10), and the N area is an n-shaped buried layer (11). The P area of the second PN junction is a p-shaped epitaxial layer (20), and the N area is an n-pit (171) and an n-shaped heavily doped area (181). The isolating ring consisting of an n-shaped heavily doped area (184), an n pit (173) and an n pit (12) is arranged on the four sides of the LDMOS device. The bottom of the whole isolating ring is contacted with the n-shaped buried layer (11). The invention also discloses a method for manufacturing the LDMOS. The LDMOS and the method can effectively solve the problem that the drain end (181) and the substrate (10) may be connected electrically.
Description
Technical field
The present invention relates to a kind of LDMOS (laterally diffused MOS, laterally diffused MOS transistor) device.
Background technology
See also Fig. 1, this is the generalized section of existing LDMOS.Having n type buried regions 11 on p type substrate 10, up then is n trap 12 again.The degree of depth of n trap 12 is also referred to as dark n trap usually greater than 2 μ m.A plurality of isolated areas 13 are arranged in the n trap 12, and these isolated areas 13 are isolated n trap 171 in the n trap 12 and p trap 172 mutually.Has n type heavily doped region 181 in the n trap 171, as the drain electrode of LDMOS device.Have n type heavily doped region 182 and p type heavily doped region 183 in the p trap 172, both link to each other as the source electrode of LDMOS device.Having gate oxide 13 on the n trap 12, up is grid 14, as the grid of LDMOS device again.Gate oxide 13 and grid 14 both sides have side wall 15.The below of grid 14 comprises isolated area 13, n trap 12 and 172 3 parts of p trap.
The drift region of above-mentioned LDMOS is made of jointly n trap 12 and n trap 171.But the structure of n trap 171 can be omitted, and this moment, the drift region then only was made up of n trap 12.Increase the puncture voltage that n trap 171 helps improving the LDMOS device.
Among the above-mentioned LDMOS, the doping type of each several part structure being become on the contrary, also is feasible.LDMOS shown in Figure 1 is a symmetrical structure, and practical devices does not also require certain symmetrical structure that is.
Among the above-mentioned LDMOS, have only a PN junction to isolate between drain terminal 181 and the substrate 10, the P district of described PN junction is a p type substrate 10, and the N district is n type buried regions 11, n trap 12, n trap 171 and n type heavily doped region 181.Under inductive load and some special applications, the current potential of drain terminal 181 may be lower than zero potential, and substrate 10 is always zero potential, and the described PN junction between this moment drain terminal 181 and the substrate 10 can forward conduction, and this can cause the LDMOS device electric leakage to occur.
Summary of the invention
Technical problem to be solved by this invention provides a kind of LDMOS device, stopped between drain terminal and the substrate may conducting problem.
For solving the problems of the technologies described above, LDMOS of the present invention has buried regions 11 on substrate 10, up then is epitaxial loayer 20 again; A plurality of isolated areas 13 are arranged in the epitaxial loayer 20, and these isolated areas 13 are isolated the trap in the epitaxial loayer 20 12, trap 171 and trap 172 mutually; The bottom of trap 12 contacts with buried regions 11; Has trap 173 in the trap 12; Has heavily doped region 184 in the trap 173; Has heavily doped region 181 in the trap 171, as the drain electrode of LDMOS device; Have heavily doped region 182 and heavily doped region 183 in the trap 172, both link to each other as the source electrode of LDMOS device; Having gate oxide 13 on the trap 12, up is grid 14, as the grid of LDMOS device again; Gate oxide 13 and grid 14 both sides have side wall 15; The below of grid 14 comprises isolated area 13, n trap 171, epitaxial loayer 20 and 172 4 parts of trap.
Among the above-mentioned LDMOS, substrate 10, epitaxial loayer 20, trap 172, heavily doped region 183 are the p type; Buried regions 11, trap 12, trap 171, heavily doped region 181, heavily doped region 182, heavily doped region 184 are the n type.
Perhaps, among the above-mentioned LDMOS, substrate 10, epitaxial loayer 20, trap 172, heavily doped region 183 are the n type; Buried regions 11, trap 12, trap 171, heavily doped region 181, heavily doped region 182, heavily doped region 184 are the p type.
The manufacture method of above-mentioned LDMOS comprises the steps:
In the 1st step, in p type substrate 10, form n type buried regions 11 with ion implantation technology;
The 2nd step, on n type buried regions 11 with epitaxy technique growth one deck p type epitaxial loayer 20;
In the 3rd step, in p type epitaxial loayer 20, form n trap 12 with ion implantation technology;
In the 4th step, in p type epitaxial loayer 20, form a plurality of isolated areas 13;
The 5th step formed n trap 171 with ion implantation technology in p type epitaxial loayer 20, form n trap 173 simultaneously in n trap 12;
In the 6th step, form gate oxide 14, grid 15 at silicon chip surface;
In the 7th step, in p type epitaxial loayer 20, form p trap 172 with ion implantation technology;
In the 8th step, form side wall 16 at silicon chip surface;
The 9th step formed n type heavily doped region 181 with ion implantation technology in n trap 171, form n type heavily doped region 182 simultaneously in p trap 172, formed n type heavily doped region 184 simultaneously in n trap 173;
In p trap 172, form p type heavily doped region 183 with ion implantation technology.
In the said method, each step ion injects type opposite, and the doping type of formed each several part structure is opposite, also is feasible.
Among the LDMOS of the present invention, there are two PN junctions to isolate between drain terminal 181 and the substrate.The P district of first PN junction is a p type substrate 10, and the N district is a n type buried regions 11.The P district of second PN junction is a p type epitaxial loayer 20, and the N district is n trap 171 and n type heavily doped region 181.And isolated by shading ring around the LDMOS device, described shading ring is made up of n type heavily doped region 184, n trap 173 and n trap 12.This has just stopped under inductive load and some special applications fully, problem that may conducting between drain terminal 181 and the substrate 10.
Description of drawings
Fig. 1 is the generalized section of existing LDMOS;
Fig. 2 is the generalized section of LDMOS of the present invention.
Description of reference numerals among the figure:
10 is p type substrate; 11 is n type buried regions; 12 is the n trap; 13 is isolated area; 14 is gate oxide; 15 is grid; 16 is side wall; 171,173 is the n trap; 172 is the p trap; 181,182,184 is n type heavily doped region; 183 is p type heavily doped region; 20 is p type epitaxial loayer.
Embodiment
See also Fig. 2, the structure of LDMOS of the present invention is: having n type buried regions 11 on the p type substrate 10, up then is p type epitaxial loayer 20 again.A plurality of isolated areas 13 are arranged in the p type epitaxial loayer 20, and these isolated areas 13 are isolated the n trap 12 in the p type epitaxial loayer 20, n trap 171 and p trap 172 mutually.The bottom of n trap 12 contacts with n type buried regions 11, and the thickness with p type epitaxial loayer 20 is identical at least to that is to say the degree of depth of n trap 12, so n trap 12 is also referred to as dark n trap.Have n trap 173 in the n trap 12, therefore n trap 173 is follow-up will be also referred to as low pressure n trap as low pressure applications.Has n type heavily doped region 184 in the n trap 173.Therefore n trap 171 is follow-up also will be also referred to as low pressure n trap as low pressure applications.Has n type heavily doped region 181 in the n trap 171,181 the drain electrodes of n type heavily doped region as the LDMOS device.Have n type heavily doped region 182 and p type heavily doped region 183 in the p trap 172, both link to each other n type heavily doped region 182 and p type heavily doped region 183 as the source electrode of LDMOS device.Having gate oxide 13 on the n trap 12, up is grid 14 again.Grid 14 is generally polycrystalline silicon material, as the grid of LDMOS device.Gate oxide 13 and grid 14 both sides have side wall 15, are generally silicon nitride material.The below of grid 14 comprises isolated area 13, n trap 171, epitaxial loayer 20 and 172 4 parts of trap.
In the above-mentioned LDMOS device, substrate 10, epitaxial loayer 20, trap 172, heavily doped region 183 change the n type into; Buried regions 11, trap 12, trap 171, heavily doped region 181, heavily doped region 182, heavily doped region 184 change the p type into, then become another embodiment of LDMOS device of the present invention.
The drift region of LDMOS of the present invention is a n trap 171.This drift region diffuses laterally into the below of grid 14, and the horizontal proliferation of this drift region helps reducing the conducting resistance of LDMOS device.
LDMOS device of the present invention has two PN junctions to isolate between drain terminal 181 and substrate 10.The P district of first PN junction is a p type substrate 10, and the N district is a n type buried regions 11.The P district of second PN junction is a p type epitaxial loayer 20, and the N district is n trap 171 and n type heavily doped region 181.These two PN junctions can effectively stop between drain terminal 181 and the substrate 10 may conducting problem.
Also be provided with shading ring around the LDMOS device of the present invention, described shading ring is made up of n type heavily doped region 184, n trap 173 and n trap 12.Because n trap 12 bottoms contact with n type buried regions 11, so whole isolated ring bottom contacts with n type buried regions 11.Shown in Figure 2 only is generalized section,, is surrounded the described shading ring formation bowl structure that also is connected with the n type buried regions 11 of LDMOS device bottom around the LDMOS device then of the present invention fully if observe the entire circuit domain from the angle of overlooking by described shading ring.If described shading ring structure is not set, then may be between drain terminal 181 and the substrate 10 from the conducting of shading ring peripheral circuit.And be provided with after the described shading ring structure, can only be connected by two PN junctions of series connection between drain terminal 181 and the substrate 10.
LDMOS shown in Figure 2 is a symmetrical structure, and practical devices does not also require certain symmetrical structure that is.
The manufacture method of LDMOS of the present invention comprises the steps:
The 1st step, in p type substrate 10, inject n type impurity with ion implantation technology, as phosphorus, arsenic, antimony etc., thereby form n type buried regions 11 at the surf zone of p type substrate 10.
The 2nd step, on n type buried regions 11 with epitaxy technique growth one deck p type monocrystalline silicon, as p type epitaxial loayer 20.
The 3rd step, in p type epitaxial loayer 20, inject n type impurity with ion implantation technology, carry out high temperature furnace annealing or rapid thermal anneal process again, thereby in p type epitaxial loayer 20, form n trap 12.The bottom of formed n trap 12 will touch n type buried regions 11 upper surfaces, and promptly the degree of depth of n trap 12 will equal the thickness of p type epitaxial loayer 20 at least.N trap 12 is also referred to as dark n trap, high pressure n trap usually.
The 4th step, in p type epitaxial loayer 20, make a plurality of isolated areas 13 with field oxygen isolation (LOCOS) technology or shallow-trench isolation (STI) technology, these isolated areas 13 are at the upper surface place of p type epitaxial loayer 20, and isolated area 13 is generally silica or other dielectric materials.
The 5th step, in p type epitaxial loayer 20, inject n type impurity, thereby in p type epitaxial loayer 20, form n trap 171 with ion implantation technology, same step ion injects also and forms n trap 173 at n trap 12 simultaneously.N trap 171,173 is also referred to as low pressure n trap usually.
Described n trap 171 to isolated area 13 of major general is surrounded in the horizontal.
In the 6th step, at silicon chip surface deposit or thermal oxide growth one deck silica, deposit one deck polysilicon with photoetching and described polysilicon of etching technics etching and silica, forms the gate oxide 14 of grid 15 and below thereof again.Grid 15 is generally polysilicon, also can be other high k metals.
At this moment, the below of grid 15 has comprised isolated area 13, n trap 171 and p type epitaxial loayer 20.
In the 7th step, in p type epitaxial loayer 20, inject p type impurity, thereby in p type epitaxial loayer 20, form p trap 172 with ion implantation technology.P trap 172 is also referred to as low pressure p trap usually.
As shown in Figure 2, this step ion injects window between two grids 14, and formed p trap 172 extends to the below of grid 15, but does not contact with n trap 171.The p type epitaxial loayer 20 that also has part between n trap 171 and the p trap 172.At this moment, the below of grid 15 comprises isolated area 13, n trap 171, p type epitaxial loayer 20 and p trap 172.
The 8th step at silicon chip surface deposit one deck medium, as silicon nitride etc., anti-carved this layer medium and stop etching when etching into p type epitaxial loayer 20, and be formed with side wall 16 in the both sides of gate oxide 14 and polysilicon gate 15 this moment.
The 9th step, in n trap 171, inject n type impurity with ion implantation technology (source is leaked and injected), thereby form n type heavily doped region 181 in n trap 171, same step ion injects also and forms n type heavily doped region 182 at p trap 172 simultaneously, and forms n type heavily doped region 184 simultaneously in n trap 173.
In p trap 172, inject p type impurity, thereby in p trap 172, form p type heavily doped region 183 with ion implantation technology.
In the said method, each step ion injects type opposite, and the doping type of formed each several part structure is opposite, also is feasible.
The order of each step of said method, technology only are example, and under same principle, the those skilled in the art in semiconductor integrated circuit manufacturing field can adopt the manufacture method of other orders or technology.
In sum, the invention discloses a kind of LDMOS and manufacture method thereof, can effectively avoid the conduction problem when special applications between drain terminal and the substrate.
Claims (6)
1. a LDMOS is characterized in that, has buried regions (11) on substrate (10), up then is epitaxial loayer (20) again; A plurality of isolated areas (13) are arranged in the epitaxial loayer (20), and these isolated areas (13) are isolated the trap (12) in the epitaxial loayer (20), trap (171) and trap (172) mutually; The bottom of trap (12) contacts with buried regions (11); Has trap (173) in the trap (12); Has heavily doped region (184) in the trap (173); Has heavily doped region (181) in the trap (171), as the drain electrode of LDMOS device; Have heavily doped region (182) and heavily doped region (183) in the trap (172), both link to each other as the source electrode of LDMOS device; Having gate oxide (13) on the trap (12), up is grid (14), as the grid of LDMOS device again; Gate oxide (13) and grid (14) both sides have side wall (15); The below of grid (14) comprises isolated area (13), n trap (171), epitaxial loayer (20) and (172) four parts of trap.
2. LDMOS according to claim 1 is characterized in that, described substrate (10), epitaxial loayer (20), trap (172), heavily doped region (183) are the p type; Buried regions (11), trap (12), trap (171), heavily doped region (181), heavily doped region (182), heavily doped region (184) are the n type;
Perhaps, described substrate (10), epitaxial loayer (20), trap (172), heavily doped region (183) are the n type; Buried regions (11), trap (12), trap (171), heavily doped region (181), heavily doped region (182), heavily doped region (184) are the p type.
3. LDMOS according to claim 1 is characterized in that, has two PN junctions to isolate between described drain terminal (181) and the substrate (10); The P district of first PN junction is a p type substrate (10), and the N district is a n type buried regions (11); The P district of second PN junction is a p type epitaxial loayer (20), and the N district is n trap (171) and n type heavily doped region (181).
4. LDMOS according to claim 1, it is characterized in that, around the described LDMOS shading ring structure is arranged, described shading ring structure is made up of n type heavily doped region (184), n trap (173) and n trap (12), and described shading ring structural base contacts with n type buried regions (11).
5. LDMOS according to claim 1 is characterized in that, the drift region of described LDMOS is n trap (171), and n trap (171) extends to the below of grid (14).
6. the manufacture method of LDMOS as claimed in claim 1 is characterized in that, comprises the steps:
In the 1st step, in p type substrate (10), form n type buried regions (11) with ion implantation technology;
The 2nd step, on n type buried regions (11) with epitaxy technique growth one deck p type epitaxial loayer (20);
In the 3rd step, in p type epitaxial loayer (20), form n trap (12) with ion implantation technology;
In the 4th step, in p type epitaxial loayer (20), form a plurality of isolated areas (13);
The 5th step formed n trap (171) with ion implantation technology in p type epitaxial loayer (20), form n trap (173) simultaneously in n trap (12);
In the 6th step, form gate oxide (14), grid (15) at silicon chip surface;
In the 7th step, in p type epitaxial loayer (20), form p trap (172) with ion implantation technology;
In the 8th step, form side wall (16) at silicon chip surface;
The 9th step formed n type heavily doped region (181) with ion implantation technology in n trap (171), form n type heavily doped region (182) simultaneously in p trap (172), formed n type heavily doped region (184) simultaneously in n trap (173);
In p trap (172), form p type heavily doped region (183) with ion implantation technology.
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| CN200910201890.1A CN102088022B (en) | 2009-12-03 | 2009-12-03 | Laterally diffused metal oxide semiconductor (LDMOS) and manufacturing method thereof |
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| CN103633082A (en) * | 2012-08-13 | 2014-03-12 | 上海华虹宏力半导体制造有限公司 | LDMOS power transistor array structure and realization method of layout of LDMOS power transistor array structure |
| CN103681839A (en) * | 2012-09-10 | 2014-03-26 | 上海华虹宏力半导体制造有限公司 | NLDMOS (N-type laterally diffused metal oxide semiconductor) device and manufacture method |
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| CN114068517A (en) * | 2020-08-05 | 2022-02-18 | 圣邦微电子（北京）股份有限公司 | Semiconductor chip |
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