CN102088022B - Laterally diffused metal oxide semiconductor (LDMOS) and manufacturing method thereof - Google Patents
Laterally diffused metal oxide semiconductor (LDMOS) and manufacturing method thereof Download PDFInfo
- Publication number
- CN102088022B CN102088022B CN200910201890.1A CN200910201890A CN102088022B CN 102088022 B CN102088022 B CN 102088022B CN 200910201890 A CN200910201890 A CN 200910201890A CN 102088022 B CN102088022 B CN 102088022B
- Authority
- CN
- China
- Prior art keywords
- trap
- heavily doped
- doped region
- epitaxial loayer
- ldmos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 239000004065 semiconductor Substances 0.000 title description 2
- 229910044991 metal oxide Inorganic materials 0.000 title 1
- 150000004706 metal oxides Chemical class 0.000 title 1
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 19
- 238000005516 engineering process Methods 0.000 claims description 20
- 238000005468 ion implantation Methods 0.000 claims description 18
- 238000002955 isolation Methods 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000000407 epitaxy Methods 0.000 claims description 3
- 101100204059 Caenorhabditis elegans trap-2 gene Proteins 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 238000002513 implantation Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000035755 proliferation Effects 0.000 description 1
- 238000007363 ring formation reaction Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses an LDMOS. Two PN junctions isolated are arranged between a drain end (181) and a substrate (10). The P area of the first PN junction is a p-shaped substrate (10), and the N area is an n-shaped buried layer (11). The P area of the second PN junction is a p-shaped epitaxial layer (20), and the N area is an n-pit (171) and an n-shaped heavily doped area (181). The isolating ring consisting of an n-shaped heavily doped area (184), an n pit (173) and an n pit (12) is arranged on the four sides of the LDMOS device. The bottom of the whole isolating ring is contacted with the n-shaped buried layer (11). The invention also discloses a method for manufacturing the LDMOS. The LDMOS and the method can effectively solve the problem that the drain end (181) and the substrate (10) may be connected electrically.
Description
Technical field
The present invention relates to a kind of LDMOS (laterally diffused MOS, laterally diffused MOS transistor) device.
Background technology
See also Fig. 1, this is the generalized section of existing LDMOS.Having N-shaped buried regions 11 at p-type substrate 10, up then is n trap 12 again.The degree of depth of n trap 12 is also referred to as dark n trap usually greater than 2 μ m.A plurality of isolated areas 13 are arranged in the n trap 12, and these isolated areas 13 are isolated the n trap 171 in the n trap 12 and p trap 172 mutually.Has N-shaped heavily doped region 181 in the n trap 171, as the drain electrode of LDMOS device.Have N-shaped heavily doped region 182 and p-type heavily doped region 183 in the p trap 172, both link to each other as the source electrode of LDMOS device.Having gate oxide 14 on the n trap 12, up is grid 15, as the grid of LDMOS device again.Gate oxide 14 and grid 15 both sides have side wall 16.The below of grid 15 comprises isolated area 13, n trap 12 and 172 3 parts of p trap.
The drift region of above-mentioned LDMOS is made of jointly n trap 12 and n trap 171.But the structure of n trap 171 can be omitted, and this moment, the drift region then only was comprised of n trap 12.Increase the puncture voltage that n trap 171 is conducive to improve the LDMOS device.
Among the above-mentioned LDMOS, the doping type of each several part structure being become on the contrary, also is feasible.LDMOS shown in Figure 1 is symmetrical structure, and practical devices does not also require certain symmetrical structure that is.
Among the above-mentioned LDMOS, only have a PN junction isolation between drain terminal 181 and the substrate 10, the P district of described PN junction is p-type substrate 10, and the N district is N-shaped buried regions 11, n trap 12, n trap 171 and N-shaped heavily doped region 181.Under inductive load and some special applications, the current potential of drain terminal 181 may be lower than zero potential, and substrate 10 is always zero potential, and the described PN junction between this moment drain terminal 181 and the substrate 10 can forward conduction, and this can cause the LDMOS device electric leakage to occur.
Summary of the invention
Technical problem to be solved by this invention provides a kind of LDMOS device, stopped between drain terminal and the substrate may conducting problem.
For solving the problems of the technologies described above, LDMOS of the present invention has buried regions 11 at substrate 10, up then is epitaxial loayer 20 again; A plurality of isolated areas 13 are arranged in the epitaxial loayer 20, and these isolated areas 13 are isolated the trap 1 in the epitaxial loayer 20, trap 2 171 and trap 3 172 mutually; The bottom of trap 1 contacts with buried regions 11; Has trap 4 173 in the trap 1; Has heavily doped region 4 184 in the trap 4 173; Has heavily doped region 1 in the trap 2 171, as the drain electrode of LDMOS device; Have heavily doped region 2 182 and heavily doped region 183 3 in the trap 3 172, both link to each other as the source electrode of LDMOS device; Having gate oxide 14 on the epitaxial loayer 20, up is grid 15, as the grid of LDMOS device again; Gate oxide 14 and grid 15 both sides have side wall 16; The below of grid 15 comprises isolated area 13, trap 2 171, epitaxial loayer 20 and 3 172 4 parts of trap.
Among the above-mentioned LDMOS, substrate 10, epitaxial loayer 20, trap 3 172, heavily doped region 3 183 are p-type; Buried regions 11, trap 1, trap 2 171, heavily doped region 1, heavily doped region 2 182, heavily doped region 4 184 are N-shaped.
Perhaps, among the above-mentioned LDMOS, substrate 10, epitaxial loayer 20, trap 3 172, heavily doped region 3 183 are N-shaped; Buried regions 11, trap 1, trap 2 171, heavily doped region 1, heavily doped region 2 182, heavily doped region 4 184 are p-type.
The manufacture method of above-mentioned LDMOS comprises the steps:
In the 1st step, in p-type substrate 10, form N-shaped buried regions 11 with ion implantation technology;
The 2nd step, on N-shaped buried regions 11 with epitaxy technique growth one deck p-type epitaxial loayer 20;
In the 3rd step, in p-type epitaxial loayer 20, form n trap 1 with ion implantation technology;
In the 4th step, in p-type epitaxial loayer 20, form a plurality of isolated areas 13;
The 5th step formed n trap 2 171 with ion implantation technology in p-type epitaxial loayer 20, form simultaneously n trap 4 173 in n trap 1;
In the 6th step, form gate oxide 14, grid 15 at silicon chip surface;
In the 7th step, in p-type epitaxial loayer 20, form p trap 3 172 with ion implantation technology;
In the 8th step, form side wall 16 at silicon chip surface;
The 9th step formed N-shaped heavily doped region 1 with ion implantation technology in n trap 2 171, form simultaneously N-shaped heavily doped region 2 182 in p trap 3 172, formed simultaneously N-shaped heavily doped region 4 184 in n trap 4 173;
In p trap 3 172, form p-type heavily doped region 3 183 with ion implantation technology.
In the said method, each step Implantation type opposite, the doping type of formed each several part structure is opposite, also is feasible.
Among the LDMOS of the present invention, two PN junction isolation are arranged between drain terminal 181 and the substrate.The P district of first PN junction is p-type substrate 10, and the N district is N-shaped buried regions 11.The P district of second PN junction is p-type epitaxial loayer 20, and the N district is n trap 2 171 and N-shaped heavily doped region 1.And isolated by shading ring around the LDMOS device, described shading ring is comprised of N-shaped heavily doped region 4 184, n trap 4 173 and one 12 of n traps.This has just stopped under inductive load and some special applications fully, problem that may conducting between drain terminal 181 and the substrate 10.
Description of drawings
Fig. 1 is the generalized section of existing LDMOS;
Fig. 2 is the generalized section of LDMOS of the present invention.
Description of reference numerals among the figure:
10 is the p-type substrate; 11 is the N-shaped buried regions; 12 is the n trap; 13 is isolated area; 14 is gate oxide; 15 is grid; 16 is side wall; 171,173 is the n trap; 172 is the p trap; 181,182,184 is the N-shaped heavily doped region; 183 is the p-type heavily doped region; 20 is the p-type epitaxial loayer.
Embodiment
See also Fig. 2, the structure of LDMOS of the present invention is: having N-shaped buried regions 11 on the p-type substrate 10, up then is p-type epitaxial loayer 20 again.A plurality of isolated areas 13 are arranged in the p-type epitaxial loayer 20, and these isolated areas 13 are isolated the n trap 12 in the p-type epitaxial loayer 20, n trap 171 and p trap 172 mutually.The bottom of n trap 12 contacts with N-shaped buried regions 11, and the thickness with p-type epitaxial loayer 20 is identical at least to that is to say the degree of depth of n trap 12, so n trap 12 is also referred to as dark n trap.Have n trap 173 in the n trap 12, n trap 173 is follow-up will as low pressure applications, therefore to be also referred to as low pressure n trap.Has N-shaped heavily doped region 184 in the n trap 173.N trap 171 is follow-up also will as low pressure applications, therefore to be also referred to as low pressure n trap.Have N-shaped heavily doped region 181 in the n trap 171, N-shaped heavily doped region 181 is as the drain electrode of LDMOS device.Have N-shaped heavily doped region 182 and p-type heavily doped region 183 in the p trap 172, both link to each other N-shaped heavily doped region 182 and p-type heavily doped region 183 as the source electrode of LDMOS device.Having gate oxide 14 on the epitaxial loayer 20, up is grid 15 again.Grid 15 is generally polycrystalline silicon material, as the grid of LDMOS device.Gate oxide 14 and grid 15 both sides have side wall 16, are generally silicon nitride material.The below of grid 15 comprises isolated area 13, n trap 171, epitaxial loayer 20 and 172 4 parts of trap.
In the above-mentioned LDMOS device, substrate 10, epitaxial loayer 20, trap 172, heavily doped region 183 change N-shaped into; Buried regions 11, trap 12, trap 171, heavily doped region 181, heavily doped region 182, heavily doped region 184 change p-type into, then become another embodiment of LDMOS device of the present invention.
The drift region of LDMOS of the present invention is n trap 171.This drift region diffuses laterally into the below of grid 15, and the horizontal proliferation of this drift region is conducive to reduce the conducting resistance of LDMOS device.
LDMOS device of the present invention has two PN junction isolation between drain terminal 181 and substrate 10.The P district of first PN junction is p-type substrate 10, and the N district is N-shaped buried regions 11.The P district of second PN junction is p-type epitaxial loayer 20, and the N district is n trap 171 and N-shaped heavily doped region 181.These two PN junctions can effectively stop between drain terminal 181 and the substrate 10 may conducting problem.
Also be provided with shading ring around the LDMOS device of the present invention, described shading ring is comprised of N-shaped heavily doped region 184, n trap 173 and n trap 12.Because n trap 12 bottoms contact with N-shaped buried regions 11, therefore whole shading ring bottom contacts with N-shaped buried regions 11.Shown in Figure 2 only is generalized section, if observe whole circuit layout from the angle of overlooking, then LDMOS device of the present invention around surrounded the described shading ring formation bowl structure that also is connected with the N-shaped buried regions 11 of LDMOS device bottom fully by described shading ring.If described shading ring structure is not set, then may be from the conducting of shading ring peripheral circuit between drain terminal 181 and the substrate 10.And be provided with after the described shading ring structure, can only be connected by two PN junctions of series connection between drain terminal 181 and the substrate 10.
LDMOS shown in Figure 2 is symmetrical structure, and practical devices does not also require certain symmetrical structure that is.
The manufacture method of LDMOS of the present invention comprises the steps:
In the 1st step, in p-type substrate 10, with ion implantation technology Implanted n-Type impurity, such as phosphorus, arsenic, antimony etc., thereby form N-shaped buried regions 11 at the surf zone of p-type substrate 10.
The 2nd step, on N-shaped buried regions 11 with epitaxy technique growth one deck p-type monocrystalline silicon, as p-type epitaxial loayer 20.
In the 3rd step, in p-type epitaxial loayer 20, with ion implantation technology Implanted n-Type impurity, carry out again high temperature furnace annealing or rapid thermal anneal process, thereby in p-type epitaxial loayer 20, form n trap 12.The bottom of formed n trap 12 will touch N-shaped buried regions 11 upper surfaces, and namely the degree of depth of n trap 12 will equal the thickness of p-type epitaxial loayer 20 at least.N trap 12 is also referred to as dark n trap, high pressure n trap usually.
The 4th step, in p-type epitaxial loayer 20, make a plurality of isolated areas 13 with field oxygen isolation (LOCOS) technique or shallow-trench isolation (STI) technique, these isolated areas 13 are at the upper surface place of p-type epitaxial loayer 20, and isolated area 13 is generally silica or other dielectric materials.
The 5th step, in p-type epitaxial loayer 20 with ion implantation technology Implanted n-Type impurity, thereby in p-type epitaxial loayer 20, form n trap 171, same step Implantation also forms n trap 173 simultaneously in n trap 12.N trap 171,173 is also referred to as low pressure n trap usually.
Described n trap 171 to isolated area 13 of major general is surrounded in the horizontal.
In the 6th step, at silicon chip surface deposit or thermal oxide growth one deck silica, deposit one deck polysilicon with photoetching and the described polysilicon of etching technics etching and silica, forms the gate oxide 14 of grid 15 and below thereof again.Grid 15 is generally polysilicon, also can be other high k metals.
At this moment, the below of grid 15 has comprised isolated area 13, n trap 171 and p-type epitaxial loayer 20.
In the 7th step, in p-type epitaxial loayer 20, inject p-type impurity with ion implantation technology, thereby in p-type epitaxial loayer 20, form p trap 172.P trap 172 is also referred to as low pressure p trap usually.
As shown in Figure 2, this step Implantation window is between two grids 15, and formed p trap 172 extends to the below of grid 15, but does not contact with n trap 171.The p-type epitaxial loayer 20 that also has part between n trap 171 and the p trap 172.At this moment, the below of grid 15 comprises isolated area 13, n trap 171, p-type epitaxial loayer 20 and p trap 172.
The 8th step at silicon chip surface deposit one deck medium, such as silicon nitride etc., anti-carved this layer medium until stop etching when etching into p-type epitaxial loayer 20, and be formed with side wall 16 in the both sides of gate oxide 14 and polysilicon gate 15 this moment.
The 9th step, in n trap 171 with ion implantation technology (source leak inject) Implanted n-Type impurity, thereby form N-shaped heavily doped region 181 in n trap 171, same step Implantation also forms N-shaped heavily doped region 182 simultaneously in p trap 172, and forms simultaneously N-shaped heavily doped region 184 in n trap 173.
In p trap 172, inject p-type impurity with ion implantation technology, thereby in p trap 172, form p-type heavily doped region 183.
In the said method, each step Implantation type opposite, the doping type of formed each several part structure is opposite, also is feasible.
The order of each step of said method, technique only are example, and under same principle, the those skilled in the art that semiconductor integrated circuit is made the field can adopt other sequentially or the manufacture method of technique.
In sum, the invention discloses a kind of LDMOS and manufacture method thereof, can effectively avoid the conduction problem when special applications between drain terminal and the substrate.
Claims (6)
1. a LDMOS is characterized in that, has buried regions (11) at substrate (10), up then is epitaxial loayer (20) again; A plurality of isolated areas (13) are arranged in the epitaxial loayer (20), and these isolated areas (13) are with the trap one (12) in the epitaxial loayer (20), trap two (171) and mutually isolation of trap three (172); The bottom of trap one (12) contacts with buried regions (11); Has trap four (173) in the trap one (12); Has heavily doped region four (184) in the trap four (173); Has heavily doped region one (181) in the trap two (171), as the drain electrode of LDMOS device; Have heavily doped region two (182) and heavily doped region three (183) in the trap three (172), both link to each other as the source electrode of LDMOS device; Having gate oxide (14) on the epitaxial loayer (20), up is grid (15), as the grid of LDMOS device again; Gate oxide (14) and grid (15) both sides have side wall (16); The below of grid (15) comprises isolated area (13), trap two (171), epitaxial loayer (20) and three (172) four parts of trap.
2. LDMOS according to claim 1 is characterized in that, described substrate (10), epitaxial loayer (20), trap three (172), heavily doped region three (183) are p-type; Buried regions (11), trap one (12), trap two (171), heavily doped region one (181), heavily doped region two (182), heavily doped region four (184) are N-shaped;
Perhaps, described substrate (10), epitaxial loayer (20), trap three (172), heavily doped region three (183) are N-shaped; Buried regions (11), trap one (12), trap (171), heavily doped region one (181), heavily doped region two (182), heavily doped region four (184) are p-type.
3. LDMOS according to claim 1 is characterized in that, two PN junction isolation are arranged between described drain terminal (181) and the substrate (10); The P district of first PN junction is p-type substrate (10), and the N district is N-shaped buried regions (11); The P district of second PN junction is p-type epitaxial loayer (20), and the N district is n trap two (171) and N-shaped heavily doped region one (181).
4. LDMOS according to claim 1, it is characterized in that, the shading ring structure is arranged around the described LDMOS, described shading ring structure is comprised of N-shaped heavily doped region four (184), n trap four (173) and n trap one (12), and described shading ring structural base contacts with N-shaped buried regions (11).
5. LDMOS according to claim 1 is characterized in that, the drift region of described LDMOS is n trap two (171), and n trap two (171) extends to the below of grid (15).
6. the manufacture method of LDMOS as claimed in claim 1 is characterized in that, comprises the steps:
In the 1st step, in p-type substrate (10), form N-shaped buried regions (11) with ion implantation technology;
The 2nd step, on N-shaped buried regions (11) with epitaxy technique growth one deck p-type epitaxial loayer (20);
In the 3rd step, in p-type epitaxial loayer (20), form n trap one (12) with ion implantation technology;
In the 4th step, in p-type epitaxial loayer (20), form a plurality of isolated areas (13);
The 5th step formed n trap two (171) with ion implantation technology in p-type epitaxial loayer (20), form simultaneously n trap four (173) in n trap one (12);
In the 6th step, form gate oxide (14), grid (15) at silicon chip surface;
In the 7th step, in p-type epitaxial loayer (20), form p trap three (172) with ion implantation technology;
In the 8th step, form side wall (16) at silicon chip surface;
The 9th step, in n trap two (171), form N-shaped heavily doped region one (181) with ion implantation technology, in p trap three (172), form simultaneously N-shaped heavily doped region two (182), in n trap four (173), form simultaneously N-shaped heavily doped region four (184);
In p trap three (172), form p-type heavily doped region three (183) with ion implantation technology.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910201890.1A CN102088022B (en) | 2009-12-03 | 2009-12-03 | Laterally diffused metal oxide semiconductor (LDMOS) and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910201890.1A CN102088022B (en) | 2009-12-03 | 2009-12-03 | Laterally diffused metal oxide semiconductor (LDMOS) and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102088022A CN102088022A (en) | 2011-06-08 |
| CN102088022B true CN102088022B (en) | 2013-03-13 |
Family
ID=44099736
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910201890.1A Active CN102088022B (en) | 2009-12-03 | 2009-12-03 | Laterally diffused metal oxide semiconductor (LDMOS) and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102088022B (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103208519B (en) * | 2012-01-12 | 2015-12-09 | 上海华虹宏力半导体制造有限公司 | With NLDMOS structure and the method for making thereof of 5 volts of CMOS technology compatibilities |
| KR101986090B1 (en) * | 2012-04-06 | 2019-06-05 | 삼성전자 주식회사 | Semiconductor device using guardring and semiconductor system comprising the same |
| CN103633082A (en) * | 2012-08-13 | 2014-03-12 | 上海华虹宏力半导体制造有限公司 | LDMOS power transistor array structure and realization method of layout of LDMOS power transistor array structure |
| CN103681839A (en) * | 2012-09-10 | 2014-03-26 | 上海华虹宏力半导体制造有限公司 | NLDMOS (N-type laterally diffused metal oxide semiconductor) device and manufacture method |
| CN103855212B (en) * | 2012-12-04 | 2018-10-23 | 中芯国际集成电路制造(上海)有限公司 | A kind of horizontal proliferation semiconductor devices |
| CN104347420B (en) * | 2013-08-07 | 2018-06-01 | 中芯国际集成电路制造(北京)有限公司 | LDMOS device and forming method thereof |
| CN105720098B (en) * | 2014-12-02 | 2019-01-29 | 中芯国际集成电路制造(上海)有限公司 | NLDMOS and preparation method thereof |
| CN105070760B (en) * | 2015-09-06 | 2017-12-19 | 电子科技大学 | A kind of power MOS (Metal Oxide Semiconductor) device |
| CN111009523B (en) * | 2019-10-08 | 2022-03-22 | 芯创智（北京）微电子有限公司 | Layout structure of substrate isolating ring |
| CN114068517B (en) * | 2020-08-05 | 2023-03-24 | 圣邦微电子（北京）股份有限公司 | Semiconductor chip |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6486034B1 (en) * | 2001-07-20 | 2002-11-26 | Taiwan Semiconductor Manufacturing Company | Method of forming LDMOS device with double N-layering |
| CN1992272A (en) * | 2005-12-27 | 2007-07-04 | 台湾积体电路制造股份有限公司 | Semiconductor structure |
| CN101288173A (en) * | 2005-08-25 | 2008-10-15 | 飞思卡尔半导体公司 | Semiconductor devices employing poly-filled trenches |
-
2009
- 2009-12-03 CN CN200910201890.1A patent/CN102088022B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6486034B1 (en) * | 2001-07-20 | 2002-11-26 | Taiwan Semiconductor Manufacturing Company | Method of forming LDMOS device with double N-layering |
| CN101288173A (en) * | 2005-08-25 | 2008-10-15 | 飞思卡尔半导体公司 | Semiconductor devices employing poly-filled trenches |
| CN1992272A (en) * | 2005-12-27 | 2007-07-04 | 台湾积体电路制造股份有限公司 | Semiconductor structure |
Non-Patent Citations (1)
| Title |
|---|
| JP特开2006-120818A 2006.05.11 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102088022A (en) | 2011-06-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102088022B (en) | Laterally diffused metal oxide semiconductor (LDMOS) and manufacturing method thereof | |
| CN101542738B (en) | Power metal oxide semiconductor field effect transistor component structure capable of being applied to high frequency | |
| CN103021958B (en) | The method of integrated high voltage device | |
| CN103050509B (en) | The semiconductor chip of integrated high-and-low-voltage device | |
| CN103748685A (en) | Insulated gate bipolar transistor | |
| CN102386124B (en) | Trench structures in direct contact | |
| CN104716177B (en) | A kind of manufacture method for the radio frequency LDMOS device for improving electric leakage | |
| CN110459539B (en) | Shielded gate trench MOSFET integrated with ESD protection and method of manufacture | |
| CN102254946B (en) | Radio frequency transverse diffusion N-type Metal Oxide Semiconductor (MOS) tube and manufacturing method thereof | |
| CN104253163A (en) | Schottky diode structure | |
| US9590039B2 (en) | Semiconductor structure and method for forming the same | |
| CN114512544A (en) | Power semiconductor element and manufacturing method thereof | |
| CN103579005A (en) | Power transistor with high voltage counter implant | |
| CN102376775B (en) | Parasitic PIN (Personal Identification Number) device in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process and manufacturing method thereof | |
| CN103456789B (en) | For forming the autoregistration injection technology in junction isolation region | |
| CN102983161B (en) | Non-buried layer double deep N well high-voltage isolation N-type LDMOS and method for manufacturing N-type LDMOS devices | |
| CN103594469A (en) | Vertical power MOSFET and methods of forming the same | |
| CN113937167B (en) | VDMOS device and manufacturing method thereof | |
| CN106941122B (en) | Semiconductor device and its manufacturing method | |
| CN112909093B (en) | Semiconductor device with a plurality of transistors | |
| CN101931004A (en) | Structure of transverse diffusion metal oxide semiconductor field effect transistor | |
| CN114005789A (en) | Manufacturing method of MOSFET (metal-oxide-semiconductor field effect transistor) of shielded gate trench | |
| CN102064193B (en) | Double diffusion drain metal oxide semiconductor field effect transistor (DDDMOS) and manufacturing method thereof | |
| CN102386183B (en) | Parasitic PIN device combing structure in BICMOS process and fabrication method | |
| CN103779416A (en) | Low VF power MOSFET device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER NAME: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI |
|
| CP03 | Change of name, title or address |
Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |